From: Jivan Hakobyan <jivanhakobyan9@gmail.com>
To: gcc-patches@gcc.gnu.org
Subject: RISC-V: Folding memory for FP + constant case
Date: Thu, 13 Jul 2023 00:59:30 +0400 [thread overview]
Message-ID: <CAHso6sPmfwnyQq4C2AQHgMbm6uxggVFGFK63_Q=yyXC+KCwTOA@mail.gmail.com> (raw)
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Accessing local arrays element turned into load form (fp + (index << C1)) +
C2 address.
In the case when access is in the loop we got loop invariant computation.
For some reason, moving out that part cannot be done in
loop-invariant passes.
But we can handle that in target-specific hook (legitimize_address).
That provides an opportunity to rewrite memory access more suitable for the
target architecture.
This patch solves the mentioned case by rewriting mentioned case to ((fp +
C2) + (index << C1))
I have evaluated it on SPEC2017 and got an improvement on leela (over 7b
instructions,
.39% of the dynamic count) and dwarfs the regression for gcc (14m
instructions, .0012%
of the dynamic count).
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_address): Handle folding.
(mem_shadd_or_shadd_rtx_p): New predicate.
--
With the best regards
Jivan Hakobyan
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diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e696ed44affe6ee8b51d635fe0eaaa33..2a7e464b855ec45f1fce4daec36d84842f3f3ea4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1754,6 +1754,22 @@ riscv_shorten_lw_offset (rtx base, HOST_WIDE_INT offset)
return addr;
}
+/* Helper for riscv_legitimize_address. Given X, return true if it
+ is a left shift by 1, 2 or 3 positions or a multiply by 2, 4 or 8.
+
+ This respectively represent canonical shift-add rtxs or scaled
+ memory addresses. */
+static bool
+mem_shadd_or_shadd_rtx_p (rtx x)
+{
+ return ((GET_CODE (x) == ASHIFT
+ || GET_CODE (x) == MULT)
+ && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && ((GET_CODE (x) == ASHIFT && IN_RANGE (INTVAL (XEXP (x, 1)), 1, 3))
+ || (GET_CODE (x) == MULT
+ && IN_RANGE (exact_log2 (INTVAL (XEXP (x, 1))), 1, 3))));
+}
+
/* This function is used to implement LEGITIMIZE_ADDRESS. If X can
be legitimized in a way that the generic machinery might not expect,
return a new address, otherwise return NULL. MODE is the mode of
@@ -1779,6 +1795,33 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
rtx base = XEXP (x, 0);
HOST_WIDE_INT offset = INTVAL (XEXP (x, 1));
+ /* Handle (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case. */
+ if (GET_CODE (base) == PLUS && mem_shadd_or_shadd_rtx_p (XEXP (base, 0))
+ && SMALL_OPERAND (offset))
+ {
+
+ rtx index = XEXP (base, 0);
+ rtx fp = XEXP (base, 1);
+ if (REGNO (fp) == VIRTUAL_STACK_VARS_REGNUM)
+ {
+
+ /* If we were given a MULT, we must fix the constant
+ as we're going to create the ASHIFT form. */
+ int shift_val = INTVAL (XEXP (index, 1));
+ if (GET_CODE (index) == MULT)
+ shift_val = exact_log2 (shift_val);
+
+ rtx reg1 = gen_reg_rtx (Pmode);
+ rtx reg2 = gen_reg_rtx (Pmode);
+ rtx reg3 = gen_reg_rtx (Pmode);
+ riscv_emit_binary (PLUS, reg1, fp, GEN_INT (offset));
+ riscv_emit_binary (ASHIFT, reg2, XEXP (index, 0), GEN_INT (shift_val));
+ riscv_emit_binary (PLUS, reg3, reg2, reg1);
+
+ return reg3;
+ }
+ }
+
if (!riscv_valid_base_register_p (base, mode, false))
base = copy_to_mode_reg (Pmode, base);
if (optimize_function_for_size_p (cfun)
next reply other threads:[~2023-07-12 20:59 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-12 20:59 Jivan Hakobyan [this message]
2023-07-15 6:16 ` Jeff Law
2023-07-25 11:24 ` Jivan Hakobyan
2023-07-26 3:31 ` Jeff Law
2023-08-01 19:14 ` Vineet Gupta
2023-08-01 20:16 ` Jivan Hakobyan
2023-08-01 21:55 ` Jeff Law
2023-08-01 22:07 ` Philipp Tomsich
2023-08-01 23:03 ` Vineet Gupta
2023-08-01 23:06 ` Philipp Tomsich
2023-08-01 23:13 ` Vineet Gupta
2023-08-01 23:27 ` Jeff Law
2023-08-01 23:38 ` Vineet Gupta
2023-08-01 23:52 ` Jeff Law
2023-08-04 9:52 ` Manolis Tsamis
2023-08-04 16:23 ` Jeff Law
2023-08-05 9:27 ` Manolis Tsamis
2023-08-01 23:22 ` Jeff Law
2023-08-01 23:28 ` Vineet Gupta
2023-08-01 23:21 ` Jeff Law
2023-08-09 19:31 ` Jeff Law
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