From: Kito Cheng <kito.cheng@sifive.com>
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com,
kito.cheng@gmail.com, palmer@dabbelt.com, palmer@rivosinc.com,
rdapp.gcc@gmail.com
Subject: Re: [PATCH] RISC-V: Add rounding mode operand for floating point instructions
Date: Mon, 15 May 2023 21:44:29 +0800 [thread overview]
Message-ID: <CALLt3Tgcxgb2NhzBRhPXZvcPqPs3CJmb2E+eTtj8eEp14iGX5A@mail.gmail.com> (raw)
In-Reply-To: <20230515114932.244397-1-juzhe.zhong@rivai.ai>
[-- Attachment #1: Type: text/plain, Size: 34334 bytes --]
LGTM
<juzhe.zhong@rivai.ai>於 2023年5月15日 週一，19:50寫道：
> From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
>
> This patch is adding rounding mode operand and FRM_REGNUM dependency
> into floating-point instructions.
>
> The floating-point instructions we added FRM and rounding mode operand:
> 1. vfadd/vfsub
> 2. vfwadd/vfwsub
> 3. vfmul
> 4. vfdiv
> 5. vfwmul
> 6. vfwmacc/vfwnmacc/vfwmsac/vfwnmsac
> 7. vfsqrt7/vfrec7
> 8. floating-point conversions.
> 9. floating-point reductions.
>
> The floating-point instructions we did NOT add FRM and rounding mode
> operand:
> 1. vfsqrt/vfneg
> 2. vfmin/vfmax
> 3. comparisons
> 4. vfclass
> 5. vfsgnj/vfsgnjn/vfsgnjx
> 6. vfmerge
> 7. vfmv.v.f
>
> TODO: floating-point ternary: FRM and rounding mode operand should be
> added but
> they are not added in this patch since it will exceed the number of
> operands can
> be handled in optabs.cc. Will add it the next patch.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-protos.h (enum frm_field_enum): New enum.
> * config/riscv/riscv-vector-builtins.cc
> (function_expander::use_widen_ternop_insn): Add default rounding mode.
> * config/riscv/riscv.cc (riscv_hard_regno_nregs): Add FRM_REGNUM.
> (riscv_hard_regno_mode_ok): Ditto.
> (riscv_conditional_register_usage): Ditto.
> * config/riscv/riscv.h (DWARF_FRAME_REGNUM): Ditto.
> (FRM_REG_P): Ditto.
> (RISCV_DWARF_FRM): Ditto.
> * config/riscv/riscv.md: Ditto.
> * config/riscv/vector-iterators.md: split smax/smin and plus/mult
> since smax/smin doesn't need FRM.
> * config/riscv/vector.md (@pred_<optab><mode>_scalar): Splitted
> pattern.
> (@pred_<optab><mode>): Ditto.
>
> ---
> gcc/config/riscv/riscv-protos.h | 10 ++
> gcc/config/riscv/riscv-vector-builtins.cc | 7 +
> gcc/config/riscv/riscv.cc | 7 +-
> gcc/config/riscv/riscv.h | 7 +-
> gcc/config/riscv/riscv.md | 1 +
> gcc/config/riscv/vector-iterators.md | 6 +-
> gcc/config/riscv/vector.md | 171 ++++++++++++++++++----
> 7 files changed, 171 insertions(+), 38 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-protos.h
> b/gcc/config/riscv/riscv-protos.h
> index 835bb802fc6..12634d0ac1a 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -231,6 +231,16 @@ enum vxrm_field_enum
> VXRM_RDN,
> VXRM_ROD
> };
> +/* Rounding mode bitfield for floating point FRM. */
> +enum frm_field_enum
> +{
> + FRM_RNE = 0b000,
> + FRM_RTZ = 0b001,
> + FRM_RDN = 0b010,
> + FRM_RUP = 0b011,
> + FRM_RMM = 0b100,
> + DYN = 0b111
> +};
> }
>
> /* We classify builtin types into two classes:
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 1de075fb90d..f10f38f6425 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -3482,6 +3482,13 @@ function_expander::use_widen_ternop_insn (insn_code
> icode)
> add_input_operand (Pmode, get_tail_policy_for_pred (pred));
> add_input_operand (Pmode, get_mask_policy_for_pred (pred));
> add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
> +
> + /* TODO: Currently, we don't support intrinsic that is modeling
> rounding mode.
> + We add default rounding mode for the intrinsics that didn't model
> rounding
> + mode yet. */
> + if (opno != insn_data[icode].n_generator_args)
> + add_input_operand (Pmode, const0_rtx);
> +
> return generate_insn (icode);
> }
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index b52e613c629..de5b87b1a87 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -6082,7 +6082,8 @@ riscv_hard_regno_nregs (unsigned int regno,
> machine_mode mode)
>
> /* mode for VL or VTYPE are just a marker, not holding value,
> so it always consume one register. */
> - if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno))
> + if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno)
> + || FRM_REG_P (regno))
> return 1;
>
> /* Assume every valid non-vector mode fits in one vector register. */
> @@ -6150,7 +6151,8 @@ riscv_hard_regno_mode_ok (unsigned int regno,
> machine_mode mode)
> if (lmul != 1)
> return ((regno % lmul) == 0);
> }
> - else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno))
> + else if (VTYPE_REG_P (regno) || VL_REG_P (regno) || VXRM_REG_P (regno)
> + || FRM_REG_P (regno))
> return true;
> else
> return false;
> @@ -6587,6 +6589,7 @@ riscv_conditional_register_usage (void)
> fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1;
> fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1;
> fixed_regs[VXRM_REGNUM] = call_used_regs[VXRM_REGNUM] = 1;
> + fixed_regs[FRM_REGNUM] = call_used_regs[FRM_REGNUM] = 1;
> }
> }
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index f74b70de562..f55bd6112a8 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -121,8 +121,9 @@ ASM_MISA_SPEC
>
> /* The mapping from gcc register number to DWARF 2 CFA column number. */
> #define DWARF_FRAME_REGNUM(REGNO)
> \
> - (VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM
> \
> - : VL_REG_P (REGNO) ? RISCV_DWARF_VL
> \
> + (FRM_REG_P (REGNO) ? RISCV_DWARF_FRM
> \
> + : VXRM_REG_P (REGNO) ? RISCV_DWARF_VXRM
> \
> + : VL_REG_P (REGNO) ? RISCV_DWARF_VL
> \
> : VTYPE_REG_P (REGNO)
> \
> ? RISCV_DWARF_VTYPE
> \
> : (GP_REG_P (REGNO) || FP_REG_P (REGNO) || V_REG_P (REGNO)
> \
> @@ -374,6 +375,7 @@ ASM_MISA_SPEC
> #define VL_REG_P(REGNO) ((REGNO) == VL_REGNUM)
> #define VTYPE_REG_P(REGNO) ((REGNO) == VTYPE_REGNUM)
> #define VXRM_REG_P(REGNO) ((REGNO) == VXRM_REGNUM)
> +#define FRM_REG_P(REGNO) ((REGNO) == FRM_REGNUM)
>
> /* True when REGNO is in SIBCALL_REGS set. */
> #define SIBCALL_REG_P(REGNO) \
> @@ -392,6 +394,7 @@ ASM_MISA_SPEC
> #define FRAME_POINTER_REGNUM 65
>
> /* Define Dwarf for RVV. */
> +#define RISCV_DWARF_FRM (4096 + 0x003)
> #define RISCV_DWARF_VXRM (4096 + 0x00a)
> #define RISCV_DWARF_VL (4096 + 0xc20)
> #define RISCV_DWARF_VTYPE (4096 + 0xc21)
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index c5cf3af9868..91808d6bd2a 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -136,6 +136,7 @@
> (VL_REGNUM 66)
> (VTYPE_REGNUM 67)
> (VXRM_REGNUM 68)
> + (FRM_REGNUM 69)
> ])
>
> (include "predicates.md")
> diff --git a/gcc/config/riscv/vector-iterators.md
> b/gcc/config/riscv/vector-iterators.md
> index a282861335d..ac87ac3d114 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -1436,8 +1436,10 @@
>
> (define_code_iterator and_ior [and ior])
>
> -(define_code_iterator any_float_binop [plus mult smax smin minus div])
> -(define_code_iterator commutative_float_binop [plus mult smax smin])
> +(define_code_iterator any_float_binop [plus mult minus div])
> +(define_code_iterator any_float_binop_nofrm [smax smin])
> +(define_code_iterator commutative_float_binop [plus mult])
> +(define_code_iterator commutative_float_binop_nofrm [smax smin])
> (define_code_iterator non_commutative_float_binop [minus div])
> (define_code_iterator any_float_unop [neg abs sqrt])
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index e0aeeea57a4..0929d19d5ec 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -5722,8 +5722,10 @@
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i")
> + (match_operand 9 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_float_binop:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (match_operand:VF 4 "register_operand" " vr, vr, vr,
> vr"))
> @@ -5733,7 +5735,7 @@
> [(set_attr "type" "<float_insn_type>")
> (set_attr "mode" "<MODE>")])
>
> -(define_insn "@pred_<optab><mode>_scalar"
> +(define_insn "@pred_<optab><mode>"
> [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> (if_then_else:VF
> (unspec:<VM>
> @@ -5744,6 +5746,28 @@
> (match_operand 8 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (any_float_binop_nofrm:VF
> + (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> + (match_operand:VF 4 "register_operand" " vr, vr, vr,
> vr"))
> + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> + "TARGET_VECTOR"
> + "vf<insn>.vv\t%0,%3,%4%p1"
> + [(set_attr "type" "<float_insn_type>")
> + (set_attr "mode" "<MODE>")])
> +
> +(define_insn "@pred_<optab><mode>_scalar"
> + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> + (if_then_else:VF
> + (unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
> + (match_operand 6 "const_int_operand" " i, i, i, i")
> + (match_operand 7 "const_int_operand" " i, i, i, i")
> + (match_operand 8 "const_int_operand" " i, i, i, i")
> + (match_operand 9 "const_int_operand" " i, i, i, i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (commutative_float_binop:VF
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f,
> f"))
> @@ -5765,6 +5789,29 @@
> (match_operand 8 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (commutative_float_binop_nofrm:VF
> + (vec_duplicate:VF
> + (match_operand:<VEL> 4 "register_operand" " f, f, f,
> f"))
> + (match_operand:VF 3 "register_operand" " vr, vr, vr,
> vr"))
> + (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> + "TARGET_VECTOR"
> + "vf<insn>.vf\t%0,%3,%4%p1"
> + [(set_attr "type" "<float_insn_type>")
> + (set_attr "mode" "<MODE>")])
> +
> +(define_insn "@pred_<optab><mode>_scalar"
> + [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> + (if_then_else:VF
> + (unspec:<VM>
> + [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> + (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
> + (match_operand 6 "const_int_operand" " i, i, i, i")
> + (match_operand 7 "const_int_operand" " i, i, i, i")
> + (match_operand 8 "const_int_operand" " i, i, i, i")
> + (match_operand 9 "const_int_operand" " i, i, i, i")
> + (reg:SI VL_REGNUM)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (non_commutative_float_binop:VF
> (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
> (vec_duplicate:VF
> @@ -5784,8 +5831,10 @@
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> (match_operand 8 "const_int_operand" " i, i, i, i")
> + (match_operand 9 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (non_commutative_float_binop:VF
> (vec_duplicate:VF
> (match_operand:<VEL> 4 "register_operand" " f, f, f,
> f"))
> @@ -6379,8 +6428,10 @@
> (match_operand 5 "const_int_operand" " i, i, i, i")
> (match_operand 6 "const_int_operand" " i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i, i, i")
> + (match_operand 8 "const_int_operand" " i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (unspec:VF
> [(match_operand:VF 3 "register_operand" " vr, vr, vr,
> vr")] VFMISC)
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> @@ -6426,8 +6477,10 @@
> (match_operand 6 "const_int_operand" "
> i, i")
> (match_operand 7 "const_int_operand" "
> i, i")
> (match_operand 8 "const_int_operand" "
> i, i")
> + (match_operand 9 "const_int_operand" "
> i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_widen_binop:VWEXTF
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "
> vr, vr"))
> @@ -6448,8 +6501,10 @@
> (match_operand 6 "const_int_operand" "
> i, i")
> (match_operand 7 "const_int_operand" "
> i, i")
> (match_operand 8 "const_int_operand" "
> i, i")
> + (match_operand 9 "const_int_operand" "
> i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_widen_binop:VWEXTF
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "
> vr, vr"))
> @@ -6471,8 +6526,10 @@
> (match_operand 6 "const_int_operand" "
> i, i")
> (match_operand 7 "const_int_operand" "
> i, i")
> (match_operand 8 "const_int_operand" "
> i, i")
> + (match_operand 9 "const_int_operand" "
> i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VWEXTF
> (match_operand:VWEXTF 3 "register_operand" "
> vr, vr")
> (float_extend:VWEXTF
> @@ -6492,8 +6549,10 @@
> (match_operand 6 "const_int_operand" "
> i, i")
> (match_operand 7 "const_int_operand" "
> i, i")
> (match_operand 8 "const_int_operand" "
> i, i")
> + (match_operand 9 "const_int_operand" "
> i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VWEXTF
> (match_operand:VWEXTF 3 "register_operand" "
> vr, vr")
> (float_extend:VWEXTF
> @@ -6521,8 +6580,10 @@
> (match_operand 6 "const_int_operand" "
> i")
> (match_operand 7 "const_int_operand" "
> i")
> (match_operand 8 "const_int_operand" "
> i")
> + (match_operand 9 "const_int_operand" "
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VWEXTF
> (mult:VWEXTF
> (float_extend:VWEXTF
> @@ -6545,8 +6606,10 @@
> (match_operand 6 "const_int_operand" "
> i")
> (match_operand 7 "const_int_operand" "
> i")
> (match_operand 8 "const_int_operand" "
> i")
> + (match_operand 9 "const_int_operand" "
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VWEXTF
> (mult:VWEXTF
> (float_extend:VWEXTF
> @@ -6570,8 +6633,10 @@
> (match_operand 6 "const_int_operand" "
> i")
> (match_operand 7 "const_int_operand" "
> i")
> (match_operand 8 "const_int_operand" "
> i")
> + (match_operand 9 "const_int_operand" "
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VWEXTF
> (neg:VWEXTF
> (mult:VWEXTF
> @@ -6595,8 +6660,10 @@
> (match_operand 6 "const_int_operand" "
> i")
> (match_operand 7 "const_int_operand" "
> i")
> (match_operand 8 "const_int_operand" "
> i")
> + (match_operand 9 "const_int_operand" "
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus_minus:VWEXTF
> (neg:VWEXTF
> (mult:VWEXTF
> @@ -6910,8 +6977,10 @@
> (match_operand 5 "const_int_operand" " i, i,
> i, i")
> (match_operand 6 "const_int_operand" " i, i,
> i, i")
> (match_operand 7 "const_int_operand" " i, i,
> i, i")
> + (match_operand 8 "const_int_operand" " i, i,
> i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (unspec:<VCONVERT>
> [(match_operand:VF 3 "register_operand" " vr, vr, vr,
> vr")] VFCVTS)
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0,
> vu, 0")))]
> @@ -6929,8 +6998,10 @@
> (match_operand 5 "const_int_operand" " i, i,
> i, i")
> (match_operand 6 "const_int_operand" " i, i,
> i, i")
> (match_operand 7 "const_int_operand" " i, i,
> i, i")
> + (match_operand 8 "const_int_operand" " i, i,
> i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_fix:<VCONVERT>
> (match_operand:VF 3 "register_operand" " vr, vr, vr,
> vr"))
> (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0,
> vu, 0")))]
> @@ -6948,8 +7019,10 @@
> (match_operand 5 "const_int_operand" " i, i, i,
> i")
> (match_operand 6 "const_int_operand" " i, i, i,
> i")
> (match_operand 7 "const_int_operand" " i, i, i,
> i")
> + (match_operand 8 "const_int_operand" " i, i, i,
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_float:VF
> (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr,
> vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> @@ -6974,8 +7047,10 @@
> (match_operand 5 "const_int_operand" " i,
> i")
> (match_operand 6 "const_int_operand" " i,
> i")
> (match_operand 7 "const_int_operand" " i,
> i")
> + (match_operand 8 "const_int_operand" " i,
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (unspec:VWCONVERTI
> [(match_operand:<VNCONVERT> 3 "register_operand" " vr,
> vr")] VFCVTS)
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu,
> 0")))]
> @@ -6993,8 +7068,10 @@
> (match_operand 5 "const_int_operand" " i, i")
> (match_operand 6 "const_int_operand" " i, i")
> (match_operand 7 "const_int_operand" " i, i")
> + (match_operand 8 "const_int_operand" " i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_fix:VWCONVERTI
> (match_operand:<VNCONVERT> 3 "register_operand" " vr,
> vr"))
> (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu,
> 0")))]
> @@ -7012,8 +7089,10 @@
> (match_operand 5 "const_int_operand" " i, i")
> (match_operand 6 "const_int_operand" " i, i")
> (match_operand 7 "const_int_operand" " i, i")
> + (match_operand 8 "const_int_operand" " i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_float:VF
> (match_operand:<VNCONVERT> 3 "register_operand" " vr,
> vr"))
> (match_operand:VF 2 "vector_merge_operand" " vu,
> 0")))]
> @@ -7031,8 +7110,10 @@
> (match_operand 5 "const_int_operand" " i,
> i")
> (match_operand 6 "const_int_operand" " i,
> i")
> (match_operand 7 "const_int_operand" " i,
> i")
> + (match_operand 8 "const_int_operand" " i,
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (float_extend:VWEXTF
> (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr,
> vr"))
> (match_operand:VWEXTF 2 "vector_merge_operand" " vu,
> 0")))]
> @@ -7057,8 +7138,10 @@
> (match_operand 5 "const_int_operand" " i, i,
> i, i, i, i")
> (match_operand 6 "const_int_operand" " i, i,
> i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i,
> i, i, i, i")
> + (match_operand 8 "const_int_operand" " i, i,
> i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (unspec:<VNCONVERT>
> [(match_operand:VF 3 "register_operand" " 0, 0,
> 0, 0, vr, vr")] VFCVTS)
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0,
> vu, 0, vu, 0")))]
> @@ -7076,8 +7159,10 @@
> (match_operand 5 "const_int_operand" " i, i,
> i, i, i, i")
> (match_operand 6 "const_int_operand" " i, i,
> i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i,
> i, i, i, i")
> + (match_operand 8 "const_int_operand" " i, i,
> i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_fix:<VNCONVERT>
> (match_operand:VF 3 "register_operand" " 0, 0,
> 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0,
> vu, 0, vu, 0")))]
> @@ -7095,8 +7180,10 @@
> (match_operand 5 "const_int_operand" " i, i,
> i, i, i, i")
> (match_operand 6 "const_int_operand" " i, i,
> i, i, i, i")
> (match_operand 7 "const_int_operand" " i, i,
> i, i, i, i")
> + (match_operand 8 "const_int_operand" " i, i,
> i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_float:<VNCONVERT>
> (match_operand:VWCONVERTI 3 "register_operand" " 0, 0,
> 0, 0, vr, vr"))
> (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0,
> vu, 0, vu, 0")))]
> @@ -7114,8 +7201,10 @@
> (match_operand 5 "const_int_operand" " i,
> i, i, i, i, i")
> (match_operand 6 "const_int_operand" " i,
> i, i, i, i, i")
> (match_operand 7 "const_int_operand" " i,
> i, i, i, i, i")
> + (match_operand 8 "const_int_operand" " i,
> i, i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0,
> 0, 0, 0, vr, vr"))
> (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu,
> 0, vu, 0, vu, 0")))]
> @@ -7133,8 +7222,10 @@
> (match_operand 5 "const_int_operand" " i,
> i, i, i, i, i")
> (match_operand 6 "const_int_operand" " i,
> i, i, i, i, i")
> (match_operand 7 "const_int_operand" " i,
> i, i, i, i, i")
> + (match_operand 8 "const_int_operand" " i,
> i, i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (unspec:<V_DOUBLE_TRUNC>
> [(float_truncate:<V_DOUBLE_TRUNC>
> (match_operand:VWEXTF 3 "register_operand" " 0,
> 0, 0, 0, vr, vr"))] UNSPEC_ROD)
> @@ -7289,8 +7380,10 @@
> (match_operand 5 "vector_length_operand" " rK,
> rK")
> (match_operand 6 "const_int_operand" " i,
> i")
> (match_operand 7 "const_int_operand" " i,
> i")
> + (match_operand 8 "const_int_operand" " i,
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_freduc:VF
> (vec_duplicate:VF
> (vec_select:<VEL>
> @@ -7311,8 +7404,10 @@
> (match_operand 5 "vector_length_operand" "
> rK, rK")
> (match_operand 6 "const_int_operand" "
> i, i")
> (match_operand 7 "const_int_operand" "
> i, i")
> + (match_operand 8 "const_int_operand" "
> i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_freduc:VF_ZVE64
> (vec_duplicate:VF_ZVE64
> (vec_select:<VEL>
> @@ -7333,8 +7428,10 @@
> (match_operand 5 "vector_length_operand" " rK,
> rK, rK, rK")
> (match_operand 6 "const_int_operand" " i,
> i, i, i")
> (match_operand 7 "const_int_operand" " i,
> i, i, i")
> + (match_operand 8 "const_int_operand" " i,
> i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (any_freduc:VF_ZVE32
> (vec_duplicate:VF_ZVE32
> (vec_select:<VEL>
> @@ -7356,8 +7453,10 @@
> (match_operand 5 "vector_length_operand" " rK,
> rK")
> (match_operand 6 "const_int_operand" " i,
> i")
> (match_operand 7 "const_int_operand" " i,
> i")
> + (match_operand 8 "const_int_operand" " i,
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus:VF
> (vec_duplicate:VF
> (vec_select:<VEL>
> @@ -7379,8 +7478,10 @@
> (match_operand 5 "vector_length_operand" "
> rK, rK")
> (match_operand 6 "const_int_operand" "
> i, i")
> (match_operand 7 "const_int_operand" "
> i, i")
> + (match_operand 8 "const_int_operand" "
> i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus:VF_ZVE64
> (vec_duplicate:VF_ZVE64
> (vec_select:<VEL>
> @@ -7402,8 +7503,10 @@
> (match_operand 5 "vector_length_operand" "
> rK, rK, rK, rK")
> (match_operand 6 "const_int_operand" "
> i, i, i, i")
> (match_operand 7 "const_int_operand" "
> i, i, i, i")
> + (match_operand 8 "const_int_operand" "
> i, i, i, i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (plus:VF_ZVE32
> (vec_duplicate:VF_ZVE32
> (vec_select:<VEL>
> @@ -7425,8 +7528,10 @@
> (match_operand 5 "vector_length_operand" " rK,
> rK")
> (match_operand 6 "const_int_operand" " i,
> i")
> (match_operand 7 "const_int_operand" " i,
> i")
> + (match_operand 8 "const_int_operand" " i,
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (match_operand:VWF 3 "register_operand" " vr,
> vr")
> (match_operand:<VWLMUL1> 4 "register_operand" " vr,
> vr")
> (match_operand:<VWLMUL1> 2 "vector_merge_operand" " vu,
> 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> @@ -7444,8 +7549,10 @@
> (match_operand 5 "vector_length_operand" " rK,
> rK")
> (match_operand 6 "const_int_operand" " i,
> i")
> (match_operand 7 "const_int_operand" " i,
> i")
> + (match_operand 8 "const_int_operand" " i,
> i")
> (reg:SI VL_REGNUM)
> - (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> + (reg:SI VTYPE_REGNUM)
> + (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
> (match_operand:VWF_ZVE64 3 "register_operand" "
> vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 4 "register_operand" "
> vr, vr")
> (match_operand:<VWLMUL1_ZVE64> 2 "vector_merge_operand" "
> vu, 0")] UNSPEC_WREDUC_SUM)] ORDER))]
> --
> 2.36.1
>
>
next prev parent reply other threads:[~2023-05-15 13:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 11:49 juzhe.zhong
2023-05-15 13:44 ` Kito Cheng [this message]
2023-05-15 13:52 ` Jeff Law
2023-05-15 13:52 ` Jeff Law
2023-05-15 13:54 ` 钟居哲
2023-05-15 14:07 ` Kito Cheng
2023-05-15 14:08 ` 钟居哲
2023-05-15 14:12 ` 钟居哲
2023-05-15 14:22 ` Kito Cheng
2023-05-15 14:24 ` 钟居哲
2023-05-15 14:28 ` 钟居哲
2023-05-15 14:37 ` 钟居哲
2023-05-15 14:41 ` Kito Cheng
2023-05-15 14:55 ` 钟居哲
2023-05-16 3:56 ` Jeff Law
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CALLt3Tgcxgb2NhzBRhPXZvcPqPs3CJmb2E+eTtj8eEp14iGX5A@mail.gmail.com \
--to=kito.cheng@sifive.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=jeffreyalaw@gmail.com \
--cc=juzhe.zhong@rivai.ai \
--cc=kito.cheng@gmail.com \
--cc=palmer@dabbelt.com \
--cc=palmer@rivosinc.com \
--cc=rdapp.gcc@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).