[PATCH v2 0/3] RISC-V: Support ZC* extensions.

[PATCH v2 0/3] RISC-V: Support ZC* extensions.

[Jiawei]

RISC-V Code Size Reduction(ZC*) extensions is a group of extensions 
which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]

The implementation of the RISC-V Code Size Reduction extension in GCC is
an important step towards making the RISC-V architecture more efficient.

The cooperation with OpenHW group has played a crucial role in this effort,
with facilitating the implementation, testing and validation. Currently
works can also find in OpenHW group's github repo.[2]

Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the 
specification, and Jeremy Bennett's patient guidance throughout the whole 
development process.a

V2 changes:
Fix Kito's comments in first version, Eswin assisted in optimizing the implementation of Zcmp extension:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html


[1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification

[2] github.com/openhwgroup/corev-gcc

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by:	Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

  RISC-V: Minimal support for ZC extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for march args being passed.


Jiawei (3):
  RISC-V: Minimal support for ZC* extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for failed march args being passed.

 gcc/common/config/riscv/riscv-common.cc   | 38 +++++++++++++++++++++++
 gcc/config/riscv/riscv-c.cc               |  2 +-
 gcc/config/riscv/riscv-opts.h             | 16 ++++++++++
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +-
 gcc/config/riscv/riscv.cc                 | 11 ++++---
 gcc/config/riscv/riscv.h                  |  2 +-
 gcc/config/riscv/riscv.opt                |  3 ++
 gcc/testsuite/gcc.target/riscv/arch-22.c  |  5 +++
 gcc/testsuite/gcc.target/riscv/arch-23.c  |  5 +++
 9 files changed, 78 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c

-- 
2.25.1

[PATCH v2 1/3] RISC-V: Minimal support for ZC* extensions.

[Jiawei]

This patch is the minimal support for ZC* extensions, include the extension
name, mask and target defination. Also define the dependencies with Zca
and Zce extension. Notes that all ZC* extensions depend on the Zca extension.
Zce includes all relevant ZC* extensions for microcontrollers using. Zce
will imply zcf when 'f' extension enabled in rv32.

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

gcc/ChangeLog:

        * common/config/riscv/riscv-common.cc (riscv_subset_list::parse): New extensions.
        * config/riscv/riscv-opts.h (MASK_ZCA): New mask.
        (MASK_ZCB): Ditto.
        (MASK_ZCE): Ditto.
        (MASK_ZCF): Ditto.
        (MASK_ZCD): Ditto.
        (MASK_ZCMP): Ditto.
        (MASK_ZCMT): Ditto.
        (TARGET_ZCA): New target.
        (TARGET_ZCB): Ditto.
        (TARGET_ZCE): Ditto.
        (TARGET_ZCF): Ditto.
        (TARGET_ZCD): Ditto.
        (TARGET_ZCMP): Ditto.
        (TARGET_ZCMT): Ditto.
        * config/riscv/riscv.opt: New target variable.

---
 gcc/common/config/riscv/riscv-common.cc | 38 +++++++++++++++++++++++++
 gcc/config/riscv/riscv-opts.h           | 16 +++++++++++
 gcc/config/riscv/riscv.opt              |  3 ++
 3 files changed, 57 insertions(+)

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 3247d526c0a..89bdbef43a5 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -111,6 +111,16 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
 
+  {"zce",  "zca"},
+  {"zce",  "zcb"},
+  {"zce",  "zcmp"},
+  {"zce",  "zcmt"},
+  {"zcf",  "zca"},
+  {"zcd",  "zca"},
+  {"zcb",  "zca"},
+  {"zcmp", "zca"},
+  {"zcmt", "zca"},
+
   {NULL, NULL}
 };
 
@@ -224,6 +234,14 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"zca",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcb",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zce",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcf",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcd",  ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmp", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zcmt", ISA_SPEC_CLASS_NONE, 1, 0},
+
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
 
@@ -1156,8 +1174,19 @@ riscv_subset_list::parse (const char *arch, location_t loc)
       subset_list->handle_implied_ext (itr);
     }
 
+  /* Zce only implies zcf when RV32 and 'f' extension exist.  */
+  if (subset_list->lookup ("zce") != NULL
+	&& subset_list->m_xlen == 32
+	&& subset_list->lookup ("f") != NULL
+	&& subset_list->lookup ("zcf") == NULL)
+    subset_list->add ("zcf", false);
+
   subset_list->handle_combine_ext ();
 
+  if (subset_list->lookup ("zcf") && subset_list->m_xlen == 64)
+    error_at (loc, "%<-march=%s%>: zcf extension supports in rv32 only"
+		  , arch);
+
   if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
     error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
 		   "extensions", arch);
@@ -1271,6 +1300,15 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
 
   {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL},
 
+  /* Code-size reduction extensions.  */
+  {"zca",     &gcc_options::x_riscv_zc_subext, MASK_ZCA},
+  {"zcb",     &gcc_options::x_riscv_zc_subext, MASK_ZCB},
+  {"zce",     &gcc_options::x_riscv_zc_subext, MASK_ZCE},
+  {"zcf",     &gcc_options::x_riscv_zc_subext, MASK_ZCF},
+  {"zcd",     &gcc_options::x_riscv_zc_subext, MASK_ZCD},
+  {"zcmp",    &gcc_options::x_riscv_zc_subext, MASK_ZCMP},
+  {"zcmt",    &gcc_options::x_riscv_zc_subext, MASK_ZCMT},
+
   {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL},
   {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT},
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 208a557b8ff..3429fc1218e 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -215,6 +215,22 @@ enum riscv_entity
 #define MASK_ZMMUL      (1 << 0)
 #define TARGET_ZMMUL    ((riscv_zm_subext & MASK_ZMMUL) != 0)
 
+#define MASK_ZCA      (1 << 0)
+#define MASK_ZCB      (1 << 1)
+#define MASK_ZCE      (1 << 2)
+#define MASK_ZCF      (1 << 3)
+#define MASK_ZCD      (1 << 4)
+#define MASK_ZCMP     (1 << 5)
+#define MASK_ZCMT     (1 << 6)
+
+#define TARGET_ZCA    ((riscv_zc_subext & MASK_ZCA) != 0)
+#define TARGET_ZCB    ((riscv_zc_subext & MASK_ZCB) != 0)
+#define TARGET_ZCE    ((riscv_zc_subext & MASK_ZCE) != 0)
+#define TARGET_ZCF    ((riscv_zc_subext & MASK_ZCF) != 0)
+#define TARGET_ZCD    ((riscv_zc_subext & MASK_ZCD) != 0)
+#define TARGET_ZCMP   ((riscv_zc_subext & MASK_ZCMP) != 0)
+#define TARGET_ZCMT   ((riscv_zc_subext & MASK_ZCMT) != 0)
+
 #define MASK_SVINVAL (1 << 0)
 #define MASK_SVNAPOT (1 << 1)
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 63d4710cb15..a6fdaef61cb 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -232,6 +232,9 @@ int riscv_zf_subext
 TargetVariable
 int riscv_zm_subext
 
+TargetVariable
+int riscv_zc_subext
+
 TargetVariable
 int riscv_sv_subext
 
-- 
2.25.1

[PATCH v2 2/3] RISC-V: Enable compressible features when use ZC* extensions.

[Jiawei]

This patch enables the compressible features with ZC* extensions.

Since all ZC* extension depends on the Zca extension, it's sufficient to only
add the target Zca to extend the target RVC.

Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>

gcc/ChangeLog:

        * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
	Enable compressed builtins when ZC* extensions enabled.
        * config/riscv/riscv-shorten-memrefs.cc:
	Enable shorten_memrefs pass when ZC* extensions enabled.
        * config/riscv/riscv.cc (riscv_compressed_reg_p):
	Enable compressible registers when ZC* extensions enabled.
        (riscv_rtx_costs): Allow adjusting rtx costs when ZC* extensions enabled.
        (riscv_address_cost): Allow adjusting address cost when ZC* extensions enabled.
        (riscv_first_stack_step): Allow compression of the register saves
	without adding extra instructions.
        * config/riscv/riscv.h (FUNCTION_BOUNDARY): Adjusts function boundary
	 to 16 bits when ZC* extensions enabled.

---
 gcc/config/riscv/riscv-c.cc               |  2 +-
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 ++-
 gcc/config/riscv/riscv.cc                 | 11 +++++++----
 gcc/config/riscv/riscv.h                  |  2 +-
 4 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc
index 6ad562dcb8b..2937c160071 100644
--- a/gcc/config/riscv/riscv-c.cc
+++ b/gcc/config/riscv/riscv-c.cc
@@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile)
 {
   builtin_define ("__riscv");
 
-  if (TARGET_RVC)
+  if (TARGET_RVC || TARGET_ZCA)
     builtin_define ("__riscv_compressed");
 
   if (TARGET_RVE)
diff --git a/gcc/config/riscv/riscv-shorten-memrefs.cc b/gcc/config/riscv/riscv-shorten-memrefs.cc
index 8f10d24ec39..6f2b973278e 100644
--- a/gcc/config/riscv/riscv-shorten-memrefs.cc
+++ b/gcc/config/riscv/riscv-shorten-memrefs.cc
@@ -65,7 +65,8 @@ public:
   /* opt_pass methods: */
   virtual bool gate (function *)
     {
-      return TARGET_RVC && riscv_mshorten_memrefs && optimize > 0;
+      return (TARGET_RVC || TARGET_ZCA)
+	&& riscv_mshorten_memrefs && optimize > 0;
     }
   virtual unsigned int execute (function *);
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 21e7d3b3caa..3a07122bf6a 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1176,7 +1176,8 @@ static bool
 riscv_compressed_reg_p (int regno)
 {
   /* x8-x15/f8-f15 are compressible registers.  */
-  return (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
+  return ((TARGET_RVC  || TARGET_ZCA)
+	  && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15)
 	  || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15)));
 }
 
@@ -2416,7 +2417,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 	  /* When optimizing for size, make uncompressible 32-bit addresses
 	     more expensive so that compressible 32-bit addresses are
 	     preferred.  */
-	  if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
+	  if ((TARGET_RVC || TARGET_ZCA)
+	      && !speed && riscv_mshorten_memrefs && mode == SImode
 	      && !riscv_compressed_lw_address_p (XEXP (x, 0)))
 	    cost++;
 
@@ -2828,7 +2830,8 @@ riscv_address_cost (rtx addr, machine_mode mode,
 {
   /* When optimizing for size, make uncompressible 32-bit addresses more
    * expensive so that compressible 32-bit addresses are preferred.  */
-  if (TARGET_RVC && !speed && riscv_mshorten_memrefs && mode == SImode
+  if ((TARGET_RVC || TARGET_ZCA)
+      && !speed && riscv_mshorten_memrefs && mode == SImode
       && !riscv_compressed_lw_address_p (addr))
     return riscv_address_insns (addr, mode, false) + 1;
   return riscv_address_insns (addr, mode, false);
@@ -5331,7 +5334,7 @@ riscv_first_stack_step (struct riscv_frame_info *frame, poly_int64 remaining_siz
       && remaining_const_size % IMM_REACH >= min_first_step)
     return remaining_const_size % IMM_REACH;
 
-  if (TARGET_RVC)
+  if (TARGET_RVC || TARGET_ZCA)
     {
       /* If we need two subtracts, and one is small enough to allow compressed
 	 loads and stores, then put that one first.  */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 4541255a8ae..a507db61900 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -186,7 +186,7 @@ ASM_MISA_SPEC
 #define PARM_BOUNDARY BITS_PER_WORD
 
 /* Allocation boundary (in *bits*) for the code of a function.  */
-#define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
+#define FUNCTION_BOUNDARY ((TARGET_RVC || TARGET_ZCA) ? 16 : 32)
 
 /* The smallest supported stack boundary the calling convention supports.  */
 #define STACK_BOUNDARY \
-- 
2.25.1

[PATCH v2 3/3] RISC-V: Add ZC* test for failed march args being passed.

[Jiawei]

Add ZC* extensions march args tests for error input cases.

Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Jiawei <jiawei@iscas.ac.cn>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/arch-22.c: New test.
        * gcc.target/riscv/arch-23.c: New test.

---
 gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +++++
 gcc/testsuite/gcc.target/riscv/arch-23.c | 5 +++++
 2 files changed, 10 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c

diff --git a/gcc/testsuite/gcc.target/riscv/arch-22.c b/gcc/testsuite/gcc.target/riscv/arch-22.c
new file mode 100644
index 00000000000..3be4ade65a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-22.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64i_zcf -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
+/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/arch-23.c b/gcc/testsuite/gcc.target/riscv/arch-23.c
new file mode 100644
index 00000000000..cecce06e474
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/arch-23.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64if_zce -mabi=lp64" } */
+int foo() {}
+/* { dg-error "'-march=rv64if_zce': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
+/* { dg-error "'-march=rv64if_zca_zcb_zce_zcf_zcmp_zcmt': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */
-- 
2.25.1

Re: [PATCH v2 0/3] RISC-V: Support ZC* extensions.

[Kito Cheng]

[-- Attachment #1: Type: text/plain, Size: 3001 bytes --]

Thanks Jiawei, v2 patch set are LGTM, but I would like to defer this until
binutils part has merged, I know you guys already implement that for a
while, so I think it’s almost there :)

Jiawei <jiawei@iscas.ac.cn>於 2023年6月7日 週三，20:57寫道：

> RISC-V Code Size Reduction(ZC*) extensions is a group of extensions
> which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
> extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]
>
> The implementation of the RISC-V Code Size Reduction extension in GCC is
> an important step towards making the RISC-V architecture more efficient.
>
> The cooperation with OpenHW group has played a crucial role in this effort,
> with facilitating the implementation, testing and validation. Currently
> works can also find in OpenHW group's github repo.[2]
>
> Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the
> specification, and Jeremy Bennett's patient guidance throughout the whole
> development process.a
>
> V2 changes:
> Fix Kito's comments in first version, Eswin assisted in optimizing the
> implementation of Zcmp extension:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html
>
> https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html
>
>
> [1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
>
> [2] github.com/openhwgroup/corev-gcc
>
> Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
> Co-Authored by: Simon Cook <simon.cook@embecosm.com>
> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
>
>   RISC-V: Minimal support for ZC extensions.
>   RISC-V: Enable compressible features when use ZC* extensions.
>   RISC-V: Add ZC* test for march args being passed.
>
>
> Jiawei (3):
>   RISC-V: Minimal support for ZC* extensions.
>   RISC-V: Enable compressible features when use ZC* extensions.
>   RISC-V: Add ZC* test for failed march args being passed.
>
>  gcc/common/config/riscv/riscv-common.cc   | 38 +++++++++++++++++++++++
>  gcc/config/riscv/riscv-c.cc               |  2 +-
>  gcc/config/riscv/riscv-opts.h             | 16 ++++++++++
>  gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +-
>  gcc/config/riscv/riscv.cc                 | 11 ++++---
>  gcc/config/riscv/riscv.h                  |  2 +-
>  gcc/config/riscv/riscv.opt                |  3 ++
>  gcc/testsuite/gcc.target/riscv/arch-22.c  |  5 +++
>  gcc/testsuite/gcc.target/riscv/arch-23.c  |  5 +++
>  9 files changed, 78 insertions(+), 7 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c
>
> --
> 2.25.1
>
>

Re: [PATCH v2 0/3] RISC-V: Support ZC* extensions.

[Kito Cheng]

Pushed to the trunk, with slight updates like rename and update testcases :)


On Wed, Jun 7, 2023 at 10:28 PM Kito Cheng via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Thanks Jiawei, v2 patch set are LGTM, but I would like to defer this until
> binutils part has merged, I know you guys already implement that for a
> while, so I think it’s almost there :)
>
> Jiawei <jiawei@iscas.ac.cn>於 2023年6月7日 週三，20:57寫道：
>
> > RISC-V Code Size Reduction(ZC*) extensions is a group of extensions
> > which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
> > extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]
> >
> > The implementation of the RISC-V Code Size Reduction extension in GCC is
> > an important step towards making the RISC-V architecture more efficient.
> >
> > The cooperation with OpenHW group has played a crucial role in this effort,
> > with facilitating the implementation, testing and validation. Currently
> > works can also find in OpenHW group's github repo.[2]
> >
> > Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the
> > specification, and Jeremy Bennett's patient guidance throughout the whole
> > development process.a
> >
> > V2 changes:
> > Fix Kito's comments in first version, Eswin assisted in optimizing the
> > implementation of Zcmp extension:
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html
> >
> > https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html
> >
> >
> > [1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification
> >
> > [2] github.com/openhwgroup/corev-gcc
> >
> > Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
> > Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
> > Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> > Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
> > Co-Authored by: Simon Cook <simon.cook@embecosm.com>
> > Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
> > Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
> >
> >   RISC-V: Minimal support for ZC extensions.
> >   RISC-V: Enable compressible features when use ZC* extensions.
> >   RISC-V: Add ZC* test for march args being passed.
> >
> >
> > Jiawei (3):
> >   RISC-V: Minimal support for ZC* extensions.
> >   RISC-V: Enable compressible features when use ZC* extensions.
> >   RISC-V: Add ZC* test for failed march args being passed.
> >
> >  gcc/common/config/riscv/riscv-common.cc   | 38 +++++++++++++++++++++++
> >  gcc/config/riscv/riscv-c.cc               |  2 +-
> >  gcc/config/riscv/riscv-opts.h             | 16 ++++++++++
> >  gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +-
> >  gcc/config/riscv/riscv.cc                 | 11 ++++---
> >  gcc/config/riscv/riscv.h                  |  2 +-
> >  gcc/config/riscv/riscv.opt                |  3 ++
> >  gcc/testsuite/gcc.target/riscv/arch-22.c  |  5 +++
> >  gcc/testsuite/gcc.target/riscv/arch-23.c  |  5 +++
> >  9 files changed, 78 insertions(+), 7 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c
> >
> > --
> > 2.25.1
> >
> >