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* [PATCH v2 0/3] RISC-V: Support ZC* extensions.
@ 2023-06-07 12:56 Jiawei
  2023-06-07 12:56 ` [PATCH v2 1/3] RISC-V: Minimal support for " Jiawei
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Jiawei @ 2023-06-07 12:56 UTC (permalink / raw)
  To: gcc-patches
  Cc: kito.cheng, palmer, christoph.muellner, jeremy.bennett,
	mary.bennett, nandni.jamnadas, charlie.keaney, simon.cook,
	tariq.kurd, ibrahim.abu.kharmeh1, gaofei, sinan.lin, wuwei2016,
	shihua, shiyulong, chenyixuan, Jiawei

RISC-V Code Size Reduction(ZC*) extensions is a group of extensions 
which define subsets of the existing C extension (Zca, Zcd, Zcf) and new
extensions(Zcb, Zcmp, Zcmt) which only contain 16-bit encodings.[1]

The implementation of the RISC-V Code Size Reduction extension in GCC is
an important step towards making the RISC-V architecture more efficient.

The cooperation with OpenHW group has played a crucial role in this effort,
with facilitating the implementation, testing and validation. Currently
works can also find in OpenHW group's github repo.[2]

Thanks to Tariq Kurd, Ibrahim Abu Kharmeh for help with explain the 
specification, and Jeremy Bennett's patient guidance throughout the whole 
development process.a

V2 changes:
Fix Kito's comments in first version, Eswin assisted in optimizing the implementation of Zcmp extension:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617440.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617442.html

https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620869.html


[1] github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification

[2] github.com/openhwgroup/corev-gcc

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by:	Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

  RISC-V: Minimal support for ZC extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for march args being passed.


Jiawei (3):
  RISC-V: Minimal support for ZC* extensions.
  RISC-V: Enable compressible features when use ZC* extensions.
  RISC-V: Add ZC* test for failed march args being passed.

 gcc/common/config/riscv/riscv-common.cc   | 38 +++++++++++++++++++++++
 gcc/config/riscv/riscv-c.cc               |  2 +-
 gcc/config/riscv/riscv-opts.h             | 16 ++++++++++
 gcc/config/riscv/riscv-shorten-memrefs.cc |  3 +-
 gcc/config/riscv/riscv.cc                 | 11 ++++---
 gcc/config/riscv/riscv.h                  |  2 +-
 gcc/config/riscv/riscv.opt                |  3 ++
 gcc/testsuite/gcc.target/riscv/arch-22.c  |  5 +++
 gcc/testsuite/gcc.target/riscv/arch-23.c  |  5 +++
 9 files changed, 78 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/arch-23.c

-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-08-14 14:12 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-07 12:56 [PATCH v2 0/3] RISC-V: Support ZC* extensions Jiawei
2023-06-07 12:56 ` [PATCH v2 1/3] RISC-V: Minimal support for " Jiawei
2023-06-07 12:56 ` [PATCH v2 2/3] RISC-V: Enable compressible features when use " Jiawei
2023-06-07 12:56 ` [PATCH v2 3/3] RISC-V: Add ZC* test for failed march args being passed Jiawei
2023-06-07 14:27 ` [PATCH v2 0/3] RISC-V: Support ZC* extensions Kito Cheng
2023-08-14 14:12   ` Kito Cheng

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