From: Kito Cheng <kito.cheng@sifive.com>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: juzhe.zhong@rivai.ai, pinskia@gmail.com, gcc-patches@gcc.gnu.org
Subject: Re: Re: RISC-V Test Errors and Failures
Date: Wed, 17 May 2023 10:20:45 +0800 [thread overview]
Message-ID: <CALLt3TifqCzDkDyHx5UKW9rDbzD=kFD8S9nVgDfSe9rOGxsEbQ@mail.gmail.com> (raw)
In-Reply-To: <mhng-092564be-d8e5-4d3f-b9c0-0b0b7d570ce2@palmer-ri-x1c9a>
Currently we are highly rely on simulator can setup correctly by ELF
attribute or -march setting, but seems not true for everyone, for
longer term we need something like
check_effective_target_aarch64_sve_hw, but as Palmer point out, we
might need...bunch of that for different extensions....
On Wed, May 17, 2023 at 10:13 AM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> On Tue, 16 May 2023 19:07:01 PDT (-0700), juzhe.zhong@rivai.ai wrote:
> > Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */
> > But not all RVV tests has use this and I not sure whether it can work.
> > I think Kito can answer it.
> > If yes, I think we should add all of them.
>
> Unless I'm missing something, it looks like that only checks if GCC is
> compiling for V. Nothing appears to be checking if the system the tests
> are running on supports V.
>
> # Return 1 if the target has RISC-V vector extension, 0 otherwise.
> # Cache the result.
>
> proc check_effective_target_riscv_vector { } {
> # Check that we are compiling for v by checking the __riscv_v marco.
> return [check_no_compiler_messages riscv_vector assembly {
> #if !defined(__riscv_v)
> #error "__riscv_v not defined!"
> #endif
> }]
> }
>
> Those are really just two different things.
>
> It seems pretty reasonably to me to just avoid running the tests when
> the DUT lacks V, but I'm never great with DG. We should probably add
> similar checks for the other ISA extensions, there's going to be a bunch
> of this.
>
> >
> > Thanks.
> >
> >
> > juzhe.zhong@rivai.ai
> >
> > From: Andrew Pinski
> > Date: 2023-05-17 10:02
> > To: juzhe.zhong@rivai.ai
> > CC: gcc-patches; palmer; Kito.cheng
> > Subject: Re: RISC-V Test Errors and Failures
> > On Tue, May 16, 2023 at 6:58 PM juzhe.zhong@rivai.ai
> > <juzhe.zhong@rivai.ai> wrote:
> >>
> >> Hi, Palmer.
> >> I saw your patch showed there are a lot of run time fail (execution fail) of C++.
> >> bug-*.C
> >>
> >> These tests are RVV api intrinsics tests coming from Kito's that I have already fixed all of them.
> >> I just double checked again they all passed.
> >> I think it may be your regression environment does not set up simulator (QEMU or SPIKE or GEM5) correctly.
> >> For example, did not enable vector extension in simulator, I don't you may try.
> >
> > So on x86_64, we test to see if you have the right vector unit before
> > running those tests? The same thing was true on powerpc (and I think
> > aarch64 does the same for SVE now too). The reason why I am asking is
> > that I would need to run the testsuite using the simulator as setup
> > for the RISCV ISA I am using rather than the one with everything on.
> > So does the RVV runtime testsuite tests to see if you can run RVV
> > before running them (or running them and return they passed)?
> >
> > Thanks,
> > Andrew Pinski
> >
> >>
> >> Thanks.
> >>
> >>
> >> juzhe.zhong@rivai.ai
> >
next prev parent reply other threads:[~2023-05-17 2:20 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 1:57 juzhe.zhong
2023-05-17 2:02 ` Andrew Pinski
2023-05-17 2:07 ` juzhe.zhong
2023-05-17 2:13 ` Palmer Dabbelt
2023-05-17 2:20 ` Kito Cheng [this message]
2023-05-17 2:21 ` Kito Cheng
2023-05-17 2:46 ` Vineet Gupta
2023-05-17 2:47 ` Palmer Dabbelt
2023-05-17 2:51 ` Patrick O'Neill
2023-05-17 2:53 ` Palmer Dabbelt
2023-05-17 3:08 ` Vineet Gupta
2023-05-17 3:11 ` Palmer Dabbelt
2023-05-17 3:33 ` Kito Cheng
2023-05-17 4:04 ` Jeff Law
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