* RISC-V Test Errors and Failures @ 2023-05-17 1:57 juzhe.zhong 2023-05-17 2:02 ` Andrew Pinski 0 siblings, 1 reply; 14+ messages in thread From: juzhe.zhong @ 2023-05-17 1:57 UTC (permalink / raw) To: gcc-patches, palmer, Kito.cheng [-- Attachment #1: Type: text/plain, Size: 479 bytes --] Hi, Palmer. I saw your patch showed there are a lot of run time fail (execution fail) of C++. bug-*.C These tests are RVV api intrinsics tests coming from Kito's that I have already fixed all of them. I just double checked again they all passed. I think it may be your regression environment does not set up simulator (QEMU or SPIKE or GEM5) correctly. For example, did not enable vector extension in simulator, I don't you may try. Thanks. juzhe.zhong@rivai.ai ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 1:57 RISC-V Test Errors and Failures juzhe.zhong @ 2023-05-17 2:02 ` Andrew Pinski 2023-05-17 2:07 ` juzhe.zhong 0 siblings, 1 reply; 14+ messages in thread From: Andrew Pinski @ 2023-05-17 2:02 UTC (permalink / raw) To: juzhe.zhong; +Cc: gcc-patches, palmer, Kito.cheng On Tue, May 16, 2023 at 6:58 PM juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> wrote: > > Hi, Palmer. > I saw your patch showed there are a lot of run time fail (execution fail) of C++. > bug-*.C > > These tests are RVV api intrinsics tests coming from Kito's that I have already fixed all of them. > I just double checked again they all passed. > I think it may be your regression environment does not set up simulator (QEMU or SPIKE or GEM5) correctly. > For example, did not enable vector extension in simulator, I don't you may try. So on x86_64, we test to see if you have the right vector unit before running those tests? The same thing was true on powerpc (and I think aarch64 does the same for SVE now too). The reason why I am asking is that I would need to run the testsuite using the simulator as setup for the RISCV ISA I am using rather than the one with everything on. So does the RVV runtime testsuite tests to see if you can run RVV before running them (or running them and return they passed)? Thanks, Andrew Pinski > > Thanks. > > > juzhe.zhong@rivai.ai ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Re: RISC-V Test Errors and Failures 2023-05-17 2:02 ` Andrew Pinski @ 2023-05-17 2:07 ` juzhe.zhong 2023-05-17 2:13 ` Palmer Dabbelt 0 siblings, 1 reply; 14+ messages in thread From: juzhe.zhong @ 2023-05-17 2:07 UTC (permalink / raw) To: pinskia; +Cc: gcc-patches, palmer, Kito.cheng [-- Attachment #1: Type: text/plain, Size: 1520 bytes --] Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */ But not all RVV tests has use this and I not sure whether it can work. I think Kito can answer it. If yes, I think we should add all of them. Thanks. juzhe.zhong@rivai.ai From: Andrew Pinski Date: 2023-05-17 10:02 To: juzhe.zhong@rivai.ai CC: gcc-patches; palmer; Kito.cheng Subject: Re: RISC-V Test Errors and Failures On Tue, May 16, 2023 at 6:58 PM juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai> wrote: > > Hi, Palmer. > I saw your patch showed there are a lot of run time fail (execution fail) of C++. > bug-*.C > > These tests are RVV api intrinsics tests coming from Kito's that I have already fixed all of them. > I just double checked again they all passed. > I think it may be your regression environment does not set up simulator (QEMU or SPIKE or GEM5) correctly. > For example, did not enable vector extension in simulator, I don't you may try. So on x86_64, we test to see if you have the right vector unit before running those tests? The same thing was true on powerpc (and I think aarch64 does the same for SVE now too). The reason why I am asking is that I would need to run the testsuite using the simulator as setup for the RISCV ISA I am using rather than the one with everything on. So does the RVV runtime testsuite tests to see if you can run RVV before running them (or running them and return they passed)? Thanks, Andrew Pinski > > Thanks. > > > juzhe.zhong@rivai.ai ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Re: RISC-V Test Errors and Failures 2023-05-17 2:07 ` juzhe.zhong @ 2023-05-17 2:13 ` Palmer Dabbelt 2023-05-17 2:20 ` Kito Cheng 0 siblings, 1 reply; 14+ messages in thread From: Palmer Dabbelt @ 2023-05-17 2:13 UTC (permalink / raw) To: juzhe.zhong; +Cc: pinskia, gcc-patches, Kito.cheng On Tue, 16 May 2023 19:07:01 PDT (-0700), juzhe.zhong@rivai.ai wrote: > Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */ > But not all RVV tests has use this and I not sure whether it can work. > I think Kito can answer it. > If yes, I think we should add all of them. Unless I'm missing something, it looks like that only checks if GCC is compiling for V. Nothing appears to be checking if the system the tests are running on supports V. # Return 1 if the target has RISC-V vector extension, 0 otherwise. # Cache the result. proc check_effective_target_riscv_vector { } { # Check that we are compiling for v by checking the __riscv_v marco. return [check_no_compiler_messages riscv_vector assembly { #if !defined(__riscv_v) #error "__riscv_v not defined!" #endif }] } Those are really just two different things. It seems pretty reasonably to me to just avoid running the tests when the DUT lacks V, but I'm never great with DG. We should probably add similar checks for the other ISA extensions, there's going to be a bunch of this. > > Thanks. > > > juzhe.zhong@rivai.ai > > From: Andrew Pinski > Date: 2023-05-17 10:02 > To: juzhe.zhong@rivai.ai > CC: gcc-patches; palmer; Kito.cheng > Subject: Re: RISC-V Test Errors and Failures > On Tue, May 16, 2023 at 6:58 PM juzhe.zhong@rivai.ai > <juzhe.zhong@rivai.ai> wrote: >> >> Hi, Palmer. >> I saw your patch showed there are a lot of run time fail (execution fail) of C++. >> bug-*.C >> >> These tests are RVV api intrinsics tests coming from Kito's that I have already fixed all of them. >> I just double checked again they all passed. >> I think it may be your regression environment does not set up simulator (QEMU or SPIKE or GEM5) correctly. >> For example, did not enable vector extension in simulator, I don't you may try. > > So on x86_64, we test to see if you have the right vector unit before > running those tests? The same thing was true on powerpc (and I think > aarch64 does the same for SVE now too). The reason why I am asking is > that I would need to run the testsuite using the simulator as setup > for the RISCV ISA I am using rather than the one with everything on. > So does the RVV runtime testsuite tests to see if you can run RVV > before running them (or running them and return they passed)? > > Thanks, > Andrew Pinski > >> >> Thanks. >> >> >> juzhe.zhong@rivai.ai > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Re: RISC-V Test Errors and Failures 2023-05-17 2:13 ` Palmer Dabbelt @ 2023-05-17 2:20 ` Kito Cheng 2023-05-17 2:21 ` Kito Cheng 0 siblings, 1 reply; 14+ messages in thread From: Kito Cheng @ 2023-05-17 2:20 UTC (permalink / raw) To: Palmer Dabbelt; +Cc: juzhe.zhong, pinskia, gcc-patches Currently we are highly rely on simulator can setup correctly by ELF attribute or -march setting, but seems not true for everyone, for longer term we need something like check_effective_target_aarch64_sve_hw, but as Palmer point out, we might need...bunch of that for different extensions.... On Wed, May 17, 2023 at 10:13 AM Palmer Dabbelt <palmer@rivosinc.com> wrote: > > On Tue, 16 May 2023 19:07:01 PDT (-0700), juzhe.zhong@rivai.ai wrote: > > Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */ > > But not all RVV tests has use this and I not sure whether it can work. > > I think Kito can answer it. > > If yes, I think we should add all of them. > > Unless I'm missing something, it looks like that only checks if GCC is > compiling for V. Nothing appears to be checking if the system the tests > are running on supports V. > > # Return 1 if the target has RISC-V vector extension, 0 otherwise. > # Cache the result. > > proc check_effective_target_riscv_vector { } { > # Check that we are compiling for v by checking the __riscv_v marco. > return [check_no_compiler_messages riscv_vector assembly { > #if !defined(__riscv_v) > #error "__riscv_v not defined!" > #endif > }] > } > > Those are really just two different things. > > It seems pretty reasonably to me to just avoid running the tests when > the DUT lacks V, but I'm never great with DG. We should probably add > similar checks for the other ISA extensions, there's going to be a bunch > of this. > > > > > Thanks. > > > > > > juzhe.zhong@rivai.ai > > > > From: Andrew Pinski > > Date: 2023-05-17 10:02 > > To: juzhe.zhong@rivai.ai > > CC: gcc-patches; palmer; Kito.cheng > > Subject: Re: RISC-V Test Errors and Failures > > On Tue, May 16, 2023 at 6:58 PM juzhe.zhong@rivai.ai > > <juzhe.zhong@rivai.ai> wrote: > >> > >> Hi, Palmer. > >> I saw your patch showed there are a lot of run time fail (execution fail) of C++. > >> bug-*.C > >> > >> These tests are RVV api intrinsics tests coming from Kito's that I have already fixed all of them. > >> I just double checked again they all passed. > >> I think it may be your regression environment does not set up simulator (QEMU or SPIKE or GEM5) correctly. > >> For example, did not enable vector extension in simulator, I don't you may try. > > > > So on x86_64, we test to see if you have the right vector unit before > > running those tests? The same thing was true on powerpc (and I think > > aarch64 does the same for SVE now too). The reason why I am asking is > > that I would need to run the testsuite using the simulator as setup > > for the RISCV ISA I am using rather than the one with everything on. > > So does the RVV runtime testsuite tests to see if you can run RVV > > before running them (or running them and return they passed)? > > > > Thanks, > > Andrew Pinski > > > >> > >> Thanks. > >> > >> > >> juzhe.zhong@rivai.ai > > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: Re: RISC-V Test Errors and Failures 2023-05-17 2:20 ` Kito Cheng @ 2023-05-17 2:21 ` Kito Cheng 2023-05-17 2:46 ` Vineet Gupta 0 siblings, 1 reply; 14+ messages in thread From: Kito Cheng @ 2023-05-17 2:21 UTC (permalink / raw) To: Palmer Dabbelt, Vineet Gupta; +Cc: juzhe.zhong, pinskia, gcc-patches Palmer: For short-term, this should help your internal test: https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 On Wed, May 17, 2023 at 10:20 AM Kito Cheng <kito.cheng@sifive.com> wrote: > > Currently we are highly rely on simulator can setup correctly by ELF > attribute or -march setting, but seems not true for everyone, for > longer term we need something like > check_effective_target_aarch64_sve_hw, but as Palmer point out, we > might need...bunch of that for different extensions.... > > On Wed, May 17, 2023 at 10:13 AM Palmer Dabbelt <palmer@rivosinc.com> wrote: > > > > On Tue, 16 May 2023 19:07:01 PDT (-0700), juzhe.zhong@rivai.ai wrote: > > > Oh, I see. Kito has add /* { dg-do run { target { riscv_vector } } } */ > > > But not all RVV tests has use this and I not sure whether it can work. > > > I think Kito can answer it. > > > If yes, I think we should add all of them. > > > > Unless I'm missing something, it looks like that only checks if GCC is > > compiling for V. Nothing appears to be checking if the system the tests > > are running on supports V. > > > > # Return 1 if the target has RISC-V vector extension, 0 otherwise. > > # Cache the result. > > > > proc check_effective_target_riscv_vector { } { > > # Check that we are compiling for v by checking the __riscv_v marco. > > return [check_no_compiler_messages riscv_vector assembly { > > #if !defined(__riscv_v) > > #error "__riscv_v not defined!" > > #endif > > }] > > } > > > > Those are really just two different things. > > > > It seems pretty reasonably to me to just avoid running the tests when > > the DUT lacks V, but I'm never great with DG. We should probably add > > similar checks for the other ISA extensions, there's going to be a bunch > > of this. > > > > > > > > Thanks. > > > > > > > > > juzhe.zhong@rivai.ai > > > > > > From: Andrew Pinski > > > Date: 2023-05-17 10:02 > > > To: juzhe.zhong@rivai.ai > > > CC: gcc-patches; palmer; Kito.cheng > > > Subject: Re: RISC-V Test Errors and Failures > > > On Tue, May 16, 2023 at 6:58 PM juzhe.zhong@rivai.ai > > > <juzhe.zhong@rivai.ai> wrote: > > >> > > >> Hi, Palmer. > > >> I saw your patch showed there are a lot of run time fail (execution fail) of C++. > > >> bug-*.C > > >> > > >> These tests are RVV api intrinsics tests coming from Kito's that I have already fixed all of them. > > >> I just double checked again they all passed. > > >> I think it may be your regression environment does not set up simulator (QEMU or SPIKE or GEM5) correctly. > > >> For example, did not enable vector extension in simulator, I don't you may try. > > > > > > So on x86_64, we test to see if you have the right vector unit before > > > running those tests? The same thing was true on powerpc (and I think > > > aarch64 does the same for SVE now too). The reason why I am asking is > > > that I would need to run the testsuite using the simulator as setup > > > for the RISCV ISA I am using rather than the one with everything on. > > > So does the RVV runtime testsuite tests to see if you can run RVV > > > before running them (or running them and return they passed)? > > > > > > Thanks, > > > Andrew Pinski > > > > > >> > > >> Thanks. > > >> > > >> > > >> juzhe.zhong@rivai.ai > > > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 2:21 ` Kito Cheng @ 2023-05-17 2:46 ` Vineet Gupta 2023-05-17 2:47 ` Palmer Dabbelt 0 siblings, 1 reply; 14+ messages in thread From: Vineet Gupta @ 2023-05-17 2:46 UTC (permalink / raw) To: Kito Cheng, Palmer Dabbelt Cc: juzhe.zhong, pinskia, gcc-patches, Patrick O'Neill On 5/16/23 19:21, Kito Cheng wrote: > Palmer: > > For short-term, this should help your internal test: > https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 That only helps if using bleeding edge toolchain scripts (which I regularly do and so did Patrick). Palmer has a fork of toolchain scripts and I'm assuming he hasn't caught up to that point ;-) -Vineet ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 2:46 ` Vineet Gupta @ 2023-05-17 2:47 ` Palmer Dabbelt 2023-05-17 2:51 ` Patrick O'Neill 0 siblings, 1 reply; 14+ messages in thread From: Palmer Dabbelt @ 2023-05-17 2:47 UTC (permalink / raw) To: Vineet Gupta Cc: kito.cheng, juzhe.zhong, pinskia, gcc-patches, Patrick O'Neill On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote: > On 5/16/23 19:21, Kito Cheng wrote: >> Palmer: >> >> For short-term, this should help your internal test: >> https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 > > That only helps if using bleeding edge toolchain scripts (which I > regularly do and so did Patrick). > > Palmer has a fork of toolchain scripts and I'm assuming he hasn't caught > up to that point ;-) I'm fine dropping the fork if the bugs have been fixed. IIRC last week we were still waiting for them to merge something? > -Vineet ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 2:47 ` Palmer Dabbelt @ 2023-05-17 2:51 ` Patrick O'Neill 2023-05-17 2:53 ` Palmer Dabbelt 0 siblings, 1 reply; 14+ messages in thread From: Patrick O'Neill @ 2023-05-17 2:51 UTC (permalink / raw) To: Palmer Dabbelt, Vineet Gupta Cc: kito.cheng, juzhe.zhong, pinskia, gcc-patches On 5/16/23 19:47, Palmer Dabbelt wrote: > On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote: >> On 5/16/23 19:21, Kito Cheng wrote: >>> Palmer: >>> >>> For short-term, this should help your internal test: >>> https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 >> >> That only helps if using bleeding edge toolchain scripts (which I >> regularly do and so did Patrick). >> >> Palmer has a fork of toolchain scripts and I'm assuming he hasn't caught >> up to that point ;-) > > I'm fine dropping the fork if the bugs have been fixed. IIRC last > week we were still waiting for them to merge something? The testsuite was broken last week, but was fixed by https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1247 which was merged last Friday. That might be the thing you were thinking about? ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 2:51 ` Patrick O'Neill @ 2023-05-17 2:53 ` Palmer Dabbelt 2023-05-17 3:08 ` Vineet Gupta 0 siblings, 1 reply; 14+ messages in thread From: Palmer Dabbelt @ 2023-05-17 2:53 UTC (permalink / raw) To: Patrick O'Neill Cc: Vineet Gupta, kito.cheng, juzhe.zhong, pinskia, gcc-patches On Tue, 16 May 2023 19:51:48 PDT (-0700), Patrick O'Neill wrote: > > On 5/16/23 19:47, Palmer Dabbelt wrote: >> On Tue, 16 May 2023 19:46:28 PDT (-0700), Vineet Gupta wrote: >>> On 5/16/23 19:21, Kito Cheng wrote: >>>> Palmer: >>>> >>>> For short-term, this should help your internal test: >>>> https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1233 >>> >>> That only helps if using bleeding edge toolchain scripts (which I >>> regularly do and so did Patrick). >>> >>> Palmer has a fork of toolchain scripts and I'm assuming he hasn't caught >>> up to that point ;-) >> >> I'm fine dropping the fork if the bugs have been fixed. IIRC last >> week we were still waiting for them to merge something? > The testsuite was broken last week, but was fixed by > https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1247 which was > merged last Friday. > > That might be the thing you were thinking about? Probably, I'll go try and bump stuff and see if it works... Thanks! ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 2:53 ` Palmer Dabbelt @ 2023-05-17 3:08 ` Vineet Gupta 2023-05-17 3:11 ` Palmer Dabbelt 0 siblings, 1 reply; 14+ messages in thread From: Vineet Gupta @ 2023-05-17 3:08 UTC (permalink / raw) To: Palmer Dabbelt, Patrick O'Neill Cc: kito.cheng, juzhe.zhong, pinskia, gcc-patches On 5/16/23 19:53, Palmer Dabbelt wrote: > > Probably, I'll go try and bump stuff and see if it works... Word of caution: Best to not disturb your existing setup, a try a fresh checkout first ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 3:08 ` Vineet Gupta @ 2023-05-17 3:11 ` Palmer Dabbelt 2023-05-17 3:33 ` Kito Cheng 0 siblings, 1 reply; 14+ messages in thread From: Palmer Dabbelt @ 2023-05-17 3:11 UTC (permalink / raw) To: Vineet Gupta Cc: Patrick O'Neill, kito.cheng, juzhe.zhong, pinskia, gcc-patches On Tue, 16 May 2023 20:08:26 PDT (-0700), Vineet Gupta wrote: > > On 5/16/23 19:53, Palmer Dabbelt wrote: >> >> Probably, I'll go try and bump stuff and see if it works... > > Word of caution: Best to not disturb your existing setup, a try a fresh > checkout first Even easier, I think I can get away with just diff --git a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run index 94d6ec5..efc3a80 100755 --- a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run +++ b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run @@ -12,4 +12,4 @@ done xlen="$(readelf -h $1 | grep 'Class' | cut -d: -f 2 | xargs echo | sed 's/^ELF//')" -qemu-riscv$xlen -r 5.10 "${qemu_args[@]}" -L ${RISC_V_SYSROOT} -cpu rv$xlen,zba=on,zbb=on,zbc=on,zbs=on "$@" +qemu-riscv$xlen -r 5.10 "${qemu_args[@]}" -L ${RISC_V_SYSROOT} -cpu rv$xlen,zba=on,zbb=on,zbc=on,zbs=on,v=on "$@" for now. I'm going to throw together hwprobe for qemu-user, from looking at the AVX stuff it should be pretty easy to plumb that into DG and then get the detection going. ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 3:11 ` Palmer Dabbelt @ 2023-05-17 3:33 ` Kito Cheng 2023-05-17 4:04 ` Jeff Law 0 siblings, 1 reply; 14+ messages in thread From: Kito Cheng @ 2023-05-17 3:33 UTC (permalink / raw) To: Palmer Dabbelt Cc: Vineet Gupta, Patrick O'Neill, juzhe.zhong, pinskia, gcc-patches > diff --git a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > index 94d6ec5..efc3a80 100755 > --- a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > +++ b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run > @@ -12,4 +12,4 @@ done > > xlen="$(readelf -h $1 | grep 'Class' | cut -d: -f 2 | xargs echo | sed 's/^ELF//')" > > -qemu-riscv$xlen -r 5.10 "${qemu_args[@]}" -L ${RISC_V_SYSROOT} -cpu rv$xlen,zba=on,zbb=on,zbc=on,zbs=on "$@" > +qemu-riscv$xlen -r 5.10 "${qemu_args[@]}" -L ${RISC_V_SYSROOT} -cpu rv$xlen,zba=on,zbb=on,zbc=on,zbs=on,v=on "$@" This not work when you testing some combination e.g. Z*inx and zve*, but anyway I guess those configurations are not matter for you guys :P > > for now. I'm going to throw together hwprobe for qemu-user, from looking at > the AVX stuff it should be pretty easy to plumb that into DG and then get the > detection going. ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: RISC-V Test Errors and Failures 2023-05-17 3:33 ` Kito Cheng @ 2023-05-17 4:04 ` Jeff Law 0 siblings, 0 replies; 14+ messages in thread From: Jeff Law @ 2023-05-17 4:04 UTC (permalink / raw) To: Kito Cheng, Palmer Dabbelt Cc: Vineet Gupta, Patrick O'Neill, juzhe.zhong, pinskia, gcc-patches On 5/16/23 21:33, Kito Cheng via Gcc-patches wrote: >> diff --git a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run >> index 94d6ec5..efc3a80 100755 >> --- a/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run >> +++ b/scripts/wrapper/qemu/riscv64-unknown-linux-gnu-run >> @@ -12,4 +12,4 @@ done >> >> xlen="$(readelf -h $1 | grep 'Class' | cut -d: -f 2 | xargs echo | sed 's/^ELF//')" >> >> -qemu-riscv$xlen -r 5.10 "${qemu_args[@]}" -L ${RISC_V_SYSROOT} -cpu rv$xlen,zba=on,zbb=on,zbc=on,zbs=on "$@" >> +qemu-riscv$xlen -r 5.10 "${qemu_args[@]}" -L ${RISC_V_SYSROOT} -cpu rv$xlen,zba=on,zbb=on,zbc=on,zbs=on,v=on "$@" > > This not work when you testing some combination e.g. Z*inx and zve*, > but anyway I guess those configurations are not matter for you guys :P What you could do is install a suitable binfmt handler, then you don't need the wrappers at all. That's how we're handling this stuff in Ventana. It also means you don't need magic dejagnu baseboard files or anything like that. In fact from dejagnu's standpoint it looks native. jeff ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-05-17 4:04 UTC | newest] Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-05-17 1:57 RISC-V Test Errors and Failures juzhe.zhong 2023-05-17 2:02 ` Andrew Pinski 2023-05-17 2:07 ` juzhe.zhong 2023-05-17 2:13 ` Palmer Dabbelt 2023-05-17 2:20 ` Kito Cheng 2023-05-17 2:21 ` Kito Cheng 2023-05-17 2:46 ` Vineet Gupta 2023-05-17 2:47 ` Palmer Dabbelt 2023-05-17 2:51 ` Patrick O'Neill 2023-05-17 2:53 ` Palmer Dabbelt 2023-05-17 3:08 ` Vineet Gupta 2023-05-17 3:11 ` Palmer Dabbelt 2023-05-17 3:33 ` Kito Cheng 2023-05-17 4:04 ` Jeff Law
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