* [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec
@ 2023-08-24 7:11 pan2.li
2023-08-31 13:09 ` Kito Cheng
0 siblings, 1 reply; 3+ messages in thread
From: pan2.li @ 2023-08-24 7:11 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, pan2.li, yanzhang.wang, kito.cheng
From: Pan Li <pan2.li@intel.com>
There will be a case like below for intrinsic and autovec combination.
vfadd RTZ <- intrinisc static rounding
vfmsub <- autovec/autovec-opt
The autovec generated vfmsub should take DYN mode, and the
frm must be restored before the vfmsub insn. This patch
would like to fix this issue by:
* Add the frm operand to the autovec/autovec-opt pattern.
* Set the frm_mode attr to DYN.
Thus, the frm flow when combine autovec and intrinsic should be.
+------------
| frrm a5
| ...
| fsrmi 4
| vfadd <- intrinsic static rounding.
| ...
| fsrm a5
| vfmsub <- autovec/autovec-opt
| ...
+------------
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmsac/vfmsub
* config/riscv/autovec.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: New test.
---
gcc/config/riscv/autovec-opt.md | 36 ++++----
gcc/config/riscv/autovec.md | 30 ++++---
.../rvv/base/float-point-frm-autovec-2.c | 88 +++++++++++++++++++
3 files changed, 127 insertions(+), 27 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 4b07e80ad95..732a51edacd 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -583,13 +583,15 @@ (define_insn_and_split "*single_widen_fnma<mode>"
;; vect__13.182_33 = .FMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
(define_insn_and_split "*double_widen_fms<mode>"
[(set (match_operand:VWEXTF 0 "register_operand")
- (fma:VWEXTF
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
- (neg:VWEXTF
- (match_operand:VWEXTF 1 "register_operand"))))]
+ (unspec:VWEXTF
+ [(fma:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand")))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -600,17 +602,20 @@ (define_insn_and_split "*double_widen_fms<mode>"
DONE;
}
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
;; This helps to match ext + fms.
(define_insn_and_split "*single_widen_fms<mode>"
[(set (match_operand:VWEXTF 0 "register_operand")
- (fma:VWEXTF
- (float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
- (match_operand:VWEXTF 3 "register_operand")
- (neg:VWEXTF
- (match_operand:VWEXTF 1 "register_operand"))))]
+ (unspec:VWEXTF
+ [(fma:VWEXTF
+ (float_extend:VWEXTF
+ (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
+ (match_operand:VWEXTF 3 "register_operand")
+ (neg:VWEXTF
+ (match_operand:VWEXTF 1 "register_operand")))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
@@ -627,7 +632,8 @@ (define_insn_and_split "*single_widen_fms<mode>"
DONE;
}
[(set_attr "type" "vfwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
;; -------------------------------------------------------------------------
;; ---- [FP] VFWNMACC
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4894986d2a5..d9f1a10eb66 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -1218,24 +1218,29 @@ (define_insn_and_split "*fnma<VF:mode><P:mode>"
(define_expand "fms<mode>4"
[(parallel
[(set (match_operand:VF 0 "register_operand")
- (fma:VF
- (match_operand:VF 1 "register_operand")
- (match_operand:VF 2 "register_operand")
- (neg:VF
- (match_operand:VF 3 "register_operand"))))
+ (unspec:VF
+ [(fma:VF
+ (match_operand:VF 1 "register_operand")
+ (match_operand:VF 2 "register_operand")
+ (neg:VF
+ (match_operand:VF 3 "register_operand")))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
(clobber (match_dup 4))])]
"TARGET_VECTOR"
{
operands[4] = gen_reg_rtx (Pmode);
- })
+ }
+ [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
(define_insn_and_split "*fms<VF:mode><P:mode>"
[(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr")
- (fma:VF
- (match_operand:VF 1 "register_operand" " %0, vr, vr")
- (match_operand:VF 2 "register_operand" " vr, vr, vr")
- (neg:VF
- (match_operand:VF 3 "register_operand" " vr, 0, vr"))))
+ (unspec:VF
+ [(fma:VF
+ (match_operand:VF 1 "register_operand" " %0, vr, vr")
+ (match_operand:VF 2 "register_operand" " vr, vr, vr")
+ (neg:VF
+ (match_operand:VF 3 "register_operand" " vr, 0, vr")))
+ (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
(clobber (match_operand:P 4 "register_operand" "=r,r,r"))]
"TARGET_VECTOR"
"#"
@@ -1249,7 +1254,8 @@ (define_insn_and_split "*fms<VF:mode><P:mode>"
DONE;
}
[(set_attr "type" "vfmuladd")
- (set_attr "mode" "<VF:MODE>")])
+ (set_attr "mode" "<VF:MODE>")
+ (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
;; -------------------------------------------------------------------------
;; ---- [FP] VFMSAC and VFMSUB
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
new file mode 100644
index 00000000000..77d0f5ef773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
@@ -0,0 +1,88 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "riscv_vector.h"
+
+/*
+**test_1:
+** ...
+** frrm\t[axt][0-9]+
+** ...
+** fsrmi\t1
+** ...
+** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+** fsrm\t[axt][0-9]+
+** ...
+** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+** ret
+*/
+void
+test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
+ double *in1, double *in2, double *out)
+{
+ *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl);
+
+ for (int i = 0; i < vl; ++i)
+ out[i] = in1[i] * in2[i] - out[i];
+}
+
+/*
+**test_2:
+** ...
+** frrm\t[axt][0-9]+
+** ...
+** fsrmi\t1
+** ...
+** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+** fsrm\t[axt][0-9]+
+** ...
+** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+** fsrmi\t4
+** ...
+** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+** fsrm\t[axt][0-9]+
+** ...
+** ret
+*/
+void
+test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
+ double *in1, double *in2, double *out)
+{
+ op2 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl);
+
+ for (int i = 0; i < vl; ++i)
+ out[i] = out[i] * in1[i] - in2[i];
+
+ *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl);
+}
+
+/*
+**test_3:
+** ...
+** frrm\t[axt][0-9]+
+** ...
+** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+** fsrmi\t4
+** ...
+** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
+** ...
+** fsrm\t[axt][0-9]+
+** ...
+** ret
+*/
+void
+test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
+ double *in1, double *in2, double *in3, double *out)
+{
+ for (int i = 0; i < vl; ++i)
+ out[i] = in2[i] * out[i] - in1[i];
+
+ *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl);
+}
--
2.34.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec
2023-08-24 7:11 [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec pan2.li
@ 2023-08-31 13:09 ` Kito Cheng
2023-08-31 13:29 ` Li, Pan2
0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2023-08-31 13:09 UTC (permalink / raw)
To: pan2.li; +Cc: gcc-patches, juzhe.zhong, yanzhang.wang
LGTM
On Thu, Aug 24, 2023 at 3:13 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ <- intrinisc static rounding
> vfmsub <- autovec/autovec-opt
>
> The autovec generated vfmsub should take DYN mode, and the
> frm must be restored before the vfmsub insn. This patch
> would like to fix this issue by:
>
> * Add the frm operand to the autovec/autovec-opt pattern.
> * Set the frm_mode attr to DYN.
>
> Thus, the frm flow when combine autovec and intrinsic should be.
>
> +------------
> | frrm a5
> | ...
> | fsrmi 4
> | vfadd <- intrinsic static rounding.
> | ...
> | fsrm a5
> | vfmsub <- autovec/autovec-opt
> | ...
> +------------
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmsac/vfmsub
> * config/riscv/autovec.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: New test.
> ---
> gcc/config/riscv/autovec-opt.md | 36 ++++----
> gcc/config/riscv/autovec.md | 30 ++++---
> .../rvv/base/float-point-frm-autovec-2.c | 88 +++++++++++++++++++
> 3 files changed, 127 insertions(+), 27 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 4b07e80ad95..732a51edacd 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -583,13 +583,15 @@ (define_insn_and_split "*single_widen_fnma<mode>"
> ;; vect__13.182_33 = .FMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
> (define_insn_and_split "*double_widen_fms<mode>"
> [(set (match_operand:VWEXTF 0 "register_operand")
> - (fma:VWEXTF
> - (float_extend:VWEXTF
> - (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
> - (float_extend:VWEXTF
> - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
> - (neg:VWEXTF
> - (match_operand:VWEXTF 1 "register_operand"))))]
> + (unspec:VWEXTF
> + [(fma:VWEXTF
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
> + (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> @@ -600,17 +602,20 @@ (define_insn_and_split "*double_widen_fms<mode>"
> DONE;
> }
> [(set_attr "type" "vfwmuladd")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> ;; This helps to match ext + fms.
> (define_insn_and_split "*single_widen_fms<mode>"
> [(set (match_operand:VWEXTF 0 "register_operand")
> - (fma:VWEXTF
> - (float_extend:VWEXTF
> - (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
> - (match_operand:VWEXTF 3 "register_operand")
> - (neg:VWEXTF
> - (match_operand:VWEXTF 1 "register_operand"))))]
> + (unspec:VWEXTF
> + [(fma:VWEXTF
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
> + (match_operand:VWEXTF 3 "register_operand")
> + (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> @@ -627,7 +632,8 @@ (define_insn_and_split "*single_widen_fms<mode>"
> DONE;
> }
> [(set_attr "type" "vfwmuladd")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> ;; -------------------------------------------------------------------------
> ;; ---- [FP] VFWNMACC
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 4894986d2a5..d9f1a10eb66 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1218,24 +1218,29 @@ (define_insn_and_split "*fnma<VF:mode><P:mode>"
> (define_expand "fms<mode>4"
> [(parallel
> [(set (match_operand:VF 0 "register_operand")
> - (fma:VF
> - (match_operand:VF 1 "register_operand")
> - (match_operand:VF 2 "register_operand")
> - (neg:VF
> - (match_operand:VF 3 "register_operand"))))
> + (unspec:VF
> + [(fma:VF
> + (match_operand:VF 1 "register_operand")
> + (match_operand:VF 2 "register_operand")
> + (neg:VF
> + (match_operand:VF 3 "register_operand")))
> + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
> (clobber (match_dup 4))])]
> "TARGET_VECTOR"
> {
> operands[4] = gen_reg_rtx (Pmode);
> - })
> + }
> + [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> (define_insn_and_split "*fms<VF:mode><P:mode>"
> [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr")
> - (fma:VF
> - (match_operand:VF 1 "register_operand" " %0, vr, vr")
> - (match_operand:VF 2 "register_operand" " vr, vr, vr")
> - (neg:VF
> - (match_operand:VF 3 "register_operand" " vr, 0, vr"))))
> + (unspec:VF
> + [(fma:VF
> + (match_operand:VF 1 "register_operand" " %0, vr, vr")
> + (match_operand:VF 2 "register_operand" " vr, vr, vr")
> + (neg:VF
> + (match_operand:VF 3 "register_operand" " vr, 0, vr")))
> + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
> (clobber (match_operand:P 4 "register_operand" "=r,r,r"))]
> "TARGET_VECTOR"
> "#"
> @@ -1249,7 +1254,8 @@ (define_insn_and_split "*fms<VF:mode><P:mode>"
> DONE;
> }
> [(set_attr "type" "vfmuladd")
> - (set_attr "mode" "<VF:MODE>")])
> + (set_attr "mode" "<VF:MODE>")
> + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> ;; -------------------------------------------------------------------------
> ;; ---- [FP] VFMSAC and VFMSUB
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
> new file mode 100644
> index 00000000000..77d0f5ef773
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
> @@ -0,0 +1,88 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "riscv_vector.h"
> +
> +/*
> +**test_1:
> +** ...
> +** frrm\t[axt][0-9]+
> +** ...
> +** fsrmi\t1
> +** ...
> +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrm\t[axt][0-9]+
> +** ...
> +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** ret
> +*/
> +void
> +test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
> + double *in1, double *in2, double *out)
> +{
> + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl);
> +
> + for (int i = 0; i < vl; ++i)
> + out[i] = in1[i] * in2[i] - out[i];
> +}
> +
> +/*
> +**test_2:
> +** ...
> +** frrm\t[axt][0-9]+
> +** ...
> +** fsrmi\t1
> +** ...
> +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrm\t[axt][0-9]+
> +** ...
> +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrmi\t4
> +** ...
> +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrm\t[axt][0-9]+
> +** ...
> +** ret
> +*/
> +void
> +test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
> + double *in1, double *in2, double *out)
> +{
> + op2 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl);
> +
> + for (int i = 0; i < vl; ++i)
> + out[i] = out[i] * in1[i] - in2[i];
> +
> + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl);
> +}
> +
> +/*
> +**test_3:
> +** ...
> +** frrm\t[axt][0-9]+
> +** ...
> +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrmi\t4
> +** ...
> +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrm\t[axt][0-9]+
> +** ...
> +** ret
> +*/
> +void
> +test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
> + double *in1, double *in2, double *in3, double *out)
> +{
> + for (int i = 0; i < vl; ++i)
> + out[i] = in2[i] * out[i] - in1[i];
> +
> + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl);
> +}
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec
2023-08-31 13:09 ` Kito Cheng
@ 2023-08-31 13:29 ` Li, Pan2
0 siblings, 0 replies; 3+ messages in thread
From: Li, Pan2 @ 2023-08-31 13:29 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, Wang, Yanzhang
Committed, thanks Kito.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Thursday, August 31, 2023 9:09 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec
LGTM
On Thu, Aug 24, 2023 at 3:13 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> There will be a case like below for intrinsic and autovec combination.
>
> vfadd RTZ <- intrinisc static rounding
> vfmsub <- autovec/autovec-opt
>
> The autovec generated vfmsub should take DYN mode, and the
> frm must be restored before the vfmsub insn. This patch
> would like to fix this issue by:
>
> * Add the frm operand to the autovec/autovec-opt pattern.
> * Set the frm_mode attr to DYN.
>
> Thus, the frm flow when combine autovec and intrinsic should be.
>
> +------------
> | frrm a5
> | ...
> | fsrmi 4
> | vfadd <- intrinsic static rounding.
> | ...
> | fsrm a5
> | vfmsub <- autovec/autovec-opt
> | ...
> +------------
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Add FRM_REGNUM to vfmsac/vfmsub
> * config/riscv/autovec.md: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c: New test.
> ---
> gcc/config/riscv/autovec-opt.md | 36 ++++----
> gcc/config/riscv/autovec.md | 30 ++++---
> .../rvv/base/float-point-frm-autovec-2.c | 88 +++++++++++++++++++
> 3 files changed, 127 insertions(+), 27 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
>
> diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
> index 4b07e80ad95..732a51edacd 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -583,13 +583,15 @@ (define_insn_and_split "*single_widen_fnma<mode>"
> ;; vect__13.182_33 = .FMS (vect__11.180_35, vect__8.176_40, vect__4.172_45);
> (define_insn_and_split "*double_widen_fms<mode>"
> [(set (match_operand:VWEXTF 0 "register_operand")
> - (fma:VWEXTF
> - (float_extend:VWEXTF
> - (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
> - (float_extend:VWEXTF
> - (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
> - (neg:VWEXTF
> - (match_operand:VWEXTF 1 "register_operand"))))]
> + (unspec:VWEXTF
> + [(fma:VWEXTF
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand"))
> + (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> @@ -600,17 +602,20 @@ (define_insn_and_split "*double_widen_fms<mode>"
> DONE;
> }
> [(set_attr "type" "vfwmuladd")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> ;; This helps to match ext + fms.
> (define_insn_and_split "*single_widen_fms<mode>"
> [(set (match_operand:VWEXTF 0 "register_operand")
> - (fma:VWEXTF
> - (float_extend:VWEXTF
> - (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
> - (match_operand:VWEXTF 3 "register_operand")
> - (neg:VWEXTF
> - (match_operand:VWEXTF 1 "register_operand"))))]
> + (unspec:VWEXTF
> + [(fma:VWEXTF
> + (float_extend:VWEXTF
> + (match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
> + (match_operand:VWEXTF 3 "register_operand")
> + (neg:VWEXTF
> + (match_operand:VWEXTF 1 "register_operand")))
> + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))]
> "TARGET_VECTOR && can_create_pseudo_p ()"
> "#"
> "&& 1"
> @@ -627,7 +632,8 @@ (define_insn_and_split "*single_widen_fms<mode>"
> DONE;
> }
> [(set_attr "type" "vfwmuladd")
> - (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> + (set_attr "mode" "<V_DOUBLE_TRUNC>")
> + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> ;; -------------------------------------------------------------------------
> ;; ---- [FP] VFWNMACC
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 4894986d2a5..d9f1a10eb66 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1218,24 +1218,29 @@ (define_insn_and_split "*fnma<VF:mode><P:mode>"
> (define_expand "fms<mode>4"
> [(parallel
> [(set (match_operand:VF 0 "register_operand")
> - (fma:VF
> - (match_operand:VF 1 "register_operand")
> - (match_operand:VF 2 "register_operand")
> - (neg:VF
> - (match_operand:VF 3 "register_operand"))))
> + (unspec:VF
> + [(fma:VF
> + (match_operand:VF 1 "register_operand")
> + (match_operand:VF 2 "register_operand")
> + (neg:VF
> + (match_operand:VF 3 "register_operand")))
> + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
> (clobber (match_dup 4))])]
> "TARGET_VECTOR"
> {
> operands[4] = gen_reg_rtx (Pmode);
> - })
> + }
> + [(set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> (define_insn_and_split "*fms<VF:mode><P:mode>"
> [(set (match_operand:VF 0 "register_operand" "=vr, vr, ?&vr")
> - (fma:VF
> - (match_operand:VF 1 "register_operand" " %0, vr, vr")
> - (match_operand:VF 2 "register_operand" " vr, vr, vr")
> - (neg:VF
> - (match_operand:VF 3 "register_operand" " vr, 0, vr"))))
> + (unspec:VF
> + [(fma:VF
> + (match_operand:VF 1 "register_operand" " %0, vr, vr")
> + (match_operand:VF 2 "register_operand" " vr, vr, vr")
> + (neg:VF
> + (match_operand:VF 3 "register_operand" " vr, 0, vr")))
> + (reg:SI FRM_REGNUM)] UNSPEC_VFFMA))
> (clobber (match_operand:P 4 "register_operand" "=r,r,r"))]
> "TARGET_VECTOR"
> "#"
> @@ -1249,7 +1254,8 @@ (define_insn_and_split "*fms<VF:mode><P:mode>"
> DONE;
> }
> [(set_attr "type" "vfmuladd")
> - (set_attr "mode" "<VF:MODE>")])
> + (set_attr "mode" "<VF:MODE>")
> + (set (attr "frm_mode") (symbol_ref "riscv_vector::FRM_DYN"))])
>
> ;; -------------------------------------------------------------------------
> ;; ---- [FP] VFMSAC and VFMSUB
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
> new file mode 100644
> index 00000000000..77d0f5ef773
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-autovec-2.c
> @@ -0,0 +1,88 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv --param=riscv-autovec-preference=fixed-vlmax -ffast-math -mabi=lp64 -O3 -Wno-psabi" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "riscv_vector.h"
> +
> +/*
> +**test_1:
> +** ...
> +** frrm\t[axt][0-9]+
> +** ...
> +** fsrmi\t1
> +** ...
> +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrm\t[axt][0-9]+
> +** ...
> +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** ret
> +*/
> +void
> +test_1 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
> + double *in1, double *in2, double *out)
> +{
> + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl);
> +
> + for (int i = 0; i < vl; ++i)
> + out[i] = in1[i] * in2[i] - out[i];
> +}
> +
> +/*
> +**test_2:
> +** ...
> +** frrm\t[axt][0-9]+
> +** ...
> +** fsrmi\t1
> +** ...
> +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrm\t[axt][0-9]+
> +** ...
> +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrmi\t4
> +** ...
> +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrm\t[axt][0-9]+
> +** ...
> +** ret
> +*/
> +void
> +test_2 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
> + double *in1, double *in2, double *out)
> +{
> + op2 = __riscv_vfadd_vv_f32m1_rm (op1, op2, 1, vl);
> +
> + for (int i = 0; i < vl; ++i)
> + out[i] = out[i] * in1[i] - in2[i];
> +
> + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl);
> +}
> +
> +/*
> +**test_3:
> +** ...
> +** frrm\t[axt][0-9]+
> +** ...
> +** vfmsub\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrmi\t4
> +** ...
> +** vfadd\.vv\tv[0-9]+,v[0-9]+,v[0-9]+
> +** ...
> +** fsrm\t[axt][0-9]+
> +** ...
> +** ret
> +*/
> +void
> +test_3 (vfloat32m1_t op1, vfloat32m1_t op2, vfloat32m1_t *op_out, size_t vl,
> + double *in1, double *in2, double *in3, double *out)
> +{
> + for (int i = 0; i < vl; ++i)
> + out[i] = in2[i] * out[i] - in1[i];
> +
> + *op_out = __riscv_vfadd_vv_f32m1_rm (op1, op2, 4, vl);
> +}
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-08-24 7:11 [PATCH v1] RISC-V: Support rounding mode for VFMSAC/VFMSUB autovec pan2.li
2023-08-31 13:09 ` Kito Cheng
2023-08-31 13:29 ` Li, Pan2
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