* [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API
@ 2023-04-26 12:05 yanzhang.wang
[not found] ` <C0EDB34B44515F0E+7C4404C2-68B6-40DA-B9F4-D633858D487C@rivai.ai>
2023-04-26 13:06 ` [PATCH v2] " yanzhang.wang
0 siblings, 2 replies; 5+ messages in thread
From: yanzhang.wang @ 2023-04-26 12:05 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Yanzhang Wang <yanzhang.wang@intel.com>
PR 109617
gcc/ChangeLog:
* config/riscv/vector-iterators.md:
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/vector-iterators.md | 3 ++-
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 14 ++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index a8e856161d3..033659930d1 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -189,6 +189,7 @@
(VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
+ (VNx4DI "TARGET_VECTOR_ELEN_64")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
(VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -220,7 +221,7 @@
(define_mode_iterator VLMULEXT32 [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
- (VNx1HI "TARGET_MIN_VLEN < 128")
+ (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
])
(define_mode_iterator VLMULEXT64 [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
new file mode 100644
index 00000000000..501d98c5897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include <riscv_vector.h>
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
+ return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
+ return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
+}
+
+/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */
--
2.39.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API
[not found] ` <C0EDB34B44515F0E+7C4404C2-68B6-40DA-B9F4-D633858D487C@rivai.ai>
@ 2023-04-26 12:22 ` Li, Pan2
0 siblings, 0 replies; 5+ messages in thread
From: Li, Pan2 @ 2023-04-26 12:22 UTC (permalink / raw)
To: juzhe.zhong, Wang, Yanzhang; +Cc: gcc-patches, kito.cheng, Wang, Yanzhang
[-- Attachment #1: Type: text/plain, Size: 1328 bytes --]
Great! Thanks yanzhang.
Could you please help to add some text about the changes below? Or kito may meet some error by git hook when commit the PATCH.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: <- add text for change.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
Pan
From: juzhe.zhong <juzhe.zhong@rivai.ai>
Sent: Wednesday, April 26, 2023 8:15 PM
To: Wang, Yanzhang <yanzhang.wang@intel.com>
Cc: gcc-patches@gcc.gnu.org; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API
LGTM. Thanks for fixing my silly mistake.
---- Replied Message ----
From
yanzhang.wang@intel.com<yanzhang.wang@intel.com><mailto:yanzhang.wang@intel.com>
Date
04/26/2023 20:05
To
gcc-patches@gcc.gnu.org<gcc-patches@gcc.gnu.org><mailto:gcc-patches@gcc.gnu.org>
Cc
juzhe.zhong@rivai.ai<juzhe.zhong@rivai.ai><mailto:juzhe.zhong@rivai.ai>,
kito.cheng@sifive.com<kito.cheng@sifive.com><mailto:kito.cheng@sifive.com>,
pan2.li@intel.com<pan2.li@intel.com><mailto:pan2.li@intel.com>,
yanzhang.wang@intel.com<yanzhang.wang@intel.com><mailto:yanzhang.wang@intel.com>
Subject
[PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API
2023-04-26 12:05 [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API yanzhang.wang
[not found] ` <C0EDB34B44515F0E+7C4404C2-68B6-40DA-B9F4-D633858D487C@rivai.ai>
@ 2023-04-26 13:06 ` yanzhang.wang
2023-04-28 10:36 ` Li, Pan2
1 sibling, 1 reply; 5+ messages in thread
From: yanzhang.wang @ 2023-04-26 13:06 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, yanzhang.wang
From: Yanzhang Wang <yanzhang.wang@intel.com>
PR 109617
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/vector-iterators.md | 3 ++-
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 14 ++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index a8e856161d3..033659930d1 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -189,6 +189,7 @@
(VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
+ (VNx4DI "TARGET_VECTOR_ELEN_64")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
(VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -220,7 +221,7 @@
(define_mode_iterator VLMULEXT32 [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
- (VNx1HI "TARGET_MIN_VLEN < 128")
+ (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
])
(define_mode_iterator VLMULEXT64 [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
new file mode 100644
index 00000000000..501d98c5897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include <riscv_vector.h>
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
+ return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
+ return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
+}
+
+/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */
--
2.39.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API
2023-04-26 13:06 ` [PATCH v2] " yanzhang.wang
@ 2023-04-28 10:36 ` Li, Pan2
2023-05-02 15:35 ` Kito Cheng
0 siblings, 1 reply; 5+ messages in thread
From: Li, Pan2 @ 2023-04-28 10:36 UTC (permalink / raw)
To: Wang, Yanzhang, gcc-patches; +Cc: juzhe.zhong, kito.cheng
Kindly ping for this ICE fix.
Pan
-----Original Message-----
From: Wang, Yanzhang <yanzhang.wang@intel.com>
Sent: Wednesday, April 26, 2023 9:06 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API
From: Yanzhang Wang <yanzhang.wang@intel.com>
PR 109617
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/vector-iterators.md | 3 ++-
.../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 14 ++++++++++++++
2 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index a8e856161d3..033659930d1 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -189,6 +189,7 @@
(VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
(VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
(VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
+ (VNx4DI "TARGET_VECTOR_ELEN_64")
(VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
(VNx2SF "TARGET_VECTOR_ELEN_FP_32")
(VNx4SF "TARGET_VECTOR_ELEN_FP_32")
@@ -220,7 +221,7 @@
(define_mode_iterator VLMULEXT32 [
(VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
- (VNx1HI "TARGET_MIN_VLEN < 128")
+ (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
])
(define_mode_iterator VLMULEXT64 [
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
new file mode 100644
index 00000000000..501d98c5897
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
+-fno-schedule-insns2" } */
+
+#include <riscv_vector.h>
+
+vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
+ return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
+}
+
+vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
+ return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
+}
+
+/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */
--
2.39.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API
2023-04-28 10:36 ` Li, Pan2
@ 2023-05-02 15:35 ` Kito Cheng
0 siblings, 0 replies; 5+ messages in thread
From: Kito Cheng @ 2023-05-02 15:35 UTC (permalink / raw)
To: Li, Pan2; +Cc: Wang, Yanzhang, gcc-patches, juzhe.zhong, kito.cheng
committed, thanks for the patch :)
On Fri, Apr 28, 2023 at 6:37 PM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Kindly ping for this ICE fix.
>
> Pan
>
> -----Original Message-----
> From: Wang, Yanzhang <yanzhang.wang@intel.com>
> Sent: Wednesday, April 26, 2023 9:06 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>
> Subject: [PATCH v2] RISC-V: ICE for vlmul_ext_v intrinsic API
>
> From: Yanzhang Wang <yanzhang.wang@intel.com>
>
> PR 109617
>
> gcc/ChangeLog:
>
> * config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
>
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> Co-authored-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/vector-iterators.md | 3 ++-
> .../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 14 ++++++++++++++
> 2 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
>
> diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
> index a8e856161d3..033659930d1 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -189,6 +189,7 @@
> (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128")
> (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128")
> (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64")
> + (VNx4DI "TARGET_VECTOR_ELEN_64")
> (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128")
> (VNx2SF "TARGET_VECTOR_ELEN_FP_32")
> (VNx4SF "TARGET_VECTOR_ELEN_FP_32")
> @@ -220,7 +221,7 @@
>
> (define_mode_iterator VLMULEXT32 [
> (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128")
> - (VNx1HI "TARGET_MIN_VLEN < 128")
> + (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128")
> ])
>
> (define_mode_iterator VLMULEXT64 [
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
> new file mode 100644
> index 00000000000..501d98c5897
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns
> +-fno-schedule-insns2" } */
> +
> +#include <riscv_vector.h>
> +
> +vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) {
> + return __riscv_vlmul_ext_v_i16mf4_i16m8(op1);
> +}
> +
> +vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) {
> + return __riscv_vlmul_ext_v_i64m2_i64m8(op1);
> +}
> +
> +/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */
> --
> 2.39.2
>
^ permalink raw reply [flat|nested] 5+ messages in thread
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2023-04-26 12:05 [PATCH] RISC-V: ICE for vlmul_ext_v intrinsic API yanzhang.wang
[not found] ` <C0EDB34B44515F0E+7C4404C2-68B6-40DA-B9F4-D633858D487C@rivai.ai>
2023-04-26 12:22 ` Li, Pan2
2023-04-26 13:06 ` [PATCH v2] " yanzhang.wang
2023-04-28 10:36 ` Li, Pan2
2023-05-02 15:35 ` Kito Cheng
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