* [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
@ 2024-04-25 1:25 pan2.li
2024-04-25 1:25 ` juzhe.zhong
0 siblings, 1 reply; 4+ messages in thread
From: pan2.li @ 2024-04-25 1:25 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, rdapp.gcc, Pan Li
From: Pan Li <pan2.li@intel.com>
We missed the existing early clobber for the dest operand of vwsll
pattern when resolve the conflict of revert register overlap. Thus
add it back to the pattern. Unfortunately, we have no test to cover
this part and will improve this after GCC-15 open.
The below tests are passed for this patch:
* The rv64gcv fully regression test with isl build.
gcc/ChangeLog:
* config/riscv/vector-crypto.md: Add early clobber to the
dest operand of vwsll.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/vector-crypto.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
index 8a4888a7653..e474ddf5da7 100755
--- a/gcc/config/riscv/vector-crypto.md
+++ b/gcc/config/riscv/vector-crypto.md
@@ -303,7 +303,7 @@ (define_insn "@pred_vwsll<mode>"
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
(define_insn "@pred_vwsll<mode>_scalar"
- [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr")
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
2024-04-25 1:25 [PATCH v1] RISC-V: Add early clobber to the dest of vwsll pan2.li
@ 2024-04-25 1:25 ` juzhe.zhong
2024-04-25 6:23 ` Kito Cheng
0 siblings, 1 reply; 4+ messages in thread
From: juzhe.zhong @ 2024-04-25 1:25 UTC (permalink / raw)
To: pan2.li, gcc-patches; +Cc: kito.cheng, Robin Dapp, pan2.li
[-- Attachment #1: Type: text/plain, Size: 1511 bytes --]
lgtm
juzhe.zhong@rivai.ai
From: pan2.li
Date: 2024-04-25 09:25
To: gcc-patches
CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
From: Pan Li <pan2.li@intel.com>
We missed the existing early clobber for the dest operand of vwsll
pattern when resolve the conflict of revert register overlap. Thus
add it back to the pattern. Unfortunately, we have no test to cover
this part and will improve this after GCC-15 open.
The below tests are passed for this patch:
* The rv64gcv fully regression test with isl build.
gcc/ChangeLog:
* config/riscv/vector-crypto.md: Add early clobber to the
dest operand of vwsll.
Signed-off-by: Pan Li <pan2.li@intel.com>
---
gcc/config/riscv/vector-crypto.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
index 8a4888a7653..e474ddf5da7 100755
--- a/gcc/config/riscv/vector-crypto.md
+++ b/gcc/config/riscv/vector-crypto.md
@@ -303,7 +303,7 @@ (define_insn "@pred_vwsll<mode>"
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
(define_insn "@pred_vwsll<mode>_scalar"
- [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr")
(if_then_else:VWEXTI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
2024-04-25 1:25 ` juzhe.zhong
@ 2024-04-25 6:23 ` Kito Cheng
2024-04-25 6:50 ` Li, Pan2
0 siblings, 1 reply; 4+ messages in thread
From: Kito Cheng @ 2024-04-25 6:23 UTC (permalink / raw)
To: juzhe.zhong; +Cc: pan2.li, gcc-patches, Robin Dapp
LGTM, thanks :)
On Thu, Apr 25, 2024 at 9:26 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> lgtm
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: pan2.li
> Date: 2024-04-25 09:25
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
> Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
> From: Pan Li <pan2.li@intel.com>
>
> We missed the existing early clobber for the dest operand of vwsll
> pattern when resolve the conflict of revert register overlap. Thus
> add it back to the pattern. Unfortunately, we have no test to cover
> this part and will improve this after GCC-15 open.
>
> The below tests are passed for this patch:
> * The rv64gcv fully regression test with isl build.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-crypto.md: Add early clobber to the
> dest operand of vwsll.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/vector-crypto.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
> index 8a4888a7653..e474ddf5da7 100755
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -303,7 +303,7 @@ (define_insn "@pred_vwsll<mode>"
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> (define_insn "@pred_vwsll<mode>_scalar"
> - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
> + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr")
> (if_then_else:VWEXTI
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
2024-04-25 6:23 ` Kito Cheng
@ 2024-04-25 6:50 ` Li, Pan2
0 siblings, 0 replies; 4+ messages in thread
From: Li, Pan2 @ 2024-04-25 6:50 UTC (permalink / raw)
To: Kito Cheng, juzhe.zhong; +Cc: gcc-patches, Robin Dapp
Committed, thanks Kito and Juzhe.
Pan
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Thursday, April 25, 2024 2:24 PM
To: juzhe.zhong@rivai.ai
Cc: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>; Robin Dapp <rdapp.gcc@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
LGTM, thanks :)
On Thu, Apr 25, 2024 at 9:26 AM juzhe.zhong@rivai.ai
<juzhe.zhong@rivai.ai> wrote:
>
> lgtm
>
> ________________________________
> juzhe.zhong@rivai.ai
>
>
> From: pan2.li
> Date: 2024-04-25 09:25
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
> Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
> From: Pan Li <pan2.li@intel.com>
>
> We missed the existing early clobber for the dest operand of vwsll
> pattern when resolve the conflict of revert register overlap. Thus
> add it back to the pattern. Unfortunately, we have no test to cover
> this part and will improve this after GCC-15 open.
>
> The below tests are passed for this patch:
> * The rv64gcv fully regression test with isl build.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-crypto.md: Add early clobber to the
> dest operand of vwsll.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> ---
> gcc/config/riscv/vector-crypto.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/vector-crypto.md b/gcc/config/riscv/vector-crypto.md
> index 8a4888a7653..e474ddf5da7 100755
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -303,7 +303,7 @@ (define_insn "@pred_vwsll<mode>"
> (set_attr "mode" "<V_DOUBLE_TRUNC>")])
> (define_insn "@pred_vwsll<mode>_scalar"
> - [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
> + [(set (match_operand:VWEXTI 0 "register_operand" "=&vr, &vr")
> (if_then_else:VWEXTI
> (unspec:<VM>
> [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-04-25 6:50 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-25 1:25 [PATCH v1] RISC-V: Add early clobber to the dest of vwsll pan2.li
2024-04-25 1:25 ` juzhe.zhong
2024-04-25 6:23 ` Kito Cheng
2024-04-25 6:50 ` Li, Pan2
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).