* [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
@ 2023-03-08 7:33 pan2.li
2023-03-08 11:31 ` Li, Pan2
0 siblings, 1 reply; 5+ messages in thread
From: pan2.li @ 2023-03-08 7:33 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, rguenther, pan2.li
From: yes <pan2.li@intel.com>
Fix the bug of the rvv bool mode size by the adjustment.
Besides the mode precision (aka bit size [1, 2, 4, 8, 16, 32, 64])
of the vbool*_t, the mode size (aka byte size) will be adjusted to
[1, 1, 1, 1, 2, 4, 8] according to the rvv spec 1.0 isa. The
adjustment will provide correct information for the underlying
redundant instruction elimiation.
Given the below sample code:
{
vbool1_t v1 = *(vbool1_t*)in;
vbool64_t v2 = *(vbool64_t*)in;
*(vbool1_t*)(out + 100) = v1;
*(vbool64_t*)(out + 200) = v2;
}
Before the size adjustment:
csrr t0,vlenb
slli t1,t0,1
csrr a3,vlenb
sub sp,sp,t1
slli a4,a3,1
add a4,a4,sp
addi a2,a1,100
vsetvli a5,zero,e8,m8,ta,ma
sub a3,a4,a3
vlm.v v24,0(a0)
vsm.v v24,0(a2)
vsm.v v24,0(a3)
addi a1,a1,200
csrr t0,vlenb
vsetvli a4,zero,e8,mf8,ta,ma
slli t1,t0,1
vlm.v v24,0(a3)
vsm.v v24,0(a1)
add sp,sp,t1
jr ra
After the size adjustment:
addi a3,a1,100
vsetvli a4,zero,e8,m8,ta,ma
addi a1,a1,200
vlm.v v24,0(a0)
vsm.v v24,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v24,0(a0)
vsm.v v24,0(a1)
ret
Additionally, the size adjust cannot cover all possible combinations
of the vbool*_t code pattern like above. We will take a look into it
in another patches.
PR 108185
PR 108654
gcc/ChangeLog:
* config/riscv/riscv-modes.def (ADJUST_BYTESIZE):
* config/riscv/riscv.cc (riscv_v_adjust_bytesize):
* config/riscv/riscv.h (riscv_v_adjust_bytesize):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr108185-1.c:
* gcc.target/riscv/rvv/base/pr108185-2.c:
* gcc.target/riscv/rvv/base/pr108185-3.c:
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
---
gcc/config/riscv/riscv-modes.def | 14 ++++++------
gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++
gcc/config/riscv/riscv.h | 1 +
.../gcc.target/riscv/rvv/base/pr108185-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-2.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-3.c | 2 +-
6 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index 110bddce851..4cf7cf8b1c6 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -64,13 +64,13 @@ ADJUST_ALIGNMENT (VNx16BI, 1);
ADJUST_ALIGNMENT (VNx32BI, 1);
ADJUST_ALIGNMENT (VNx64BI, 1);
-ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
-ADJUST_BYTESIZE (VNx2BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
-ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
-ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
-ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
-ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
-ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8));
+ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1));
+ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1));
+ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1));
+ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1));
+ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2));
+ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4));
+ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8));
ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1));
ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2));
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e7b7d87cebc..428fbb28fae 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1003,6 +1003,28 @@ riscv_v_adjust_nunits (machine_mode mode, int scale)
return scale;
}
+/* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct
+ BYTE size for corresponding machine_mode. */
+
+poly_int64
+riscv_v_adjust_bytesize (machine_mode mode, int scale)
+{
+ if (riscv_v_ext_vector_mode_p (mode))
+ {
+ poly_uint16 mode_size = GET_MODE_SIZE (mode);
+
+ if (maybe_eq (mode_size, (uint16_t)-1))
+ mode_size = riscv_vector_chunks * scale;
+
+ if (known_gt (mode_size, BYTES_PER_RISCV_VECTOR))
+ mode_size = BYTES_PER_RISCV_VECTOR;
+
+ return mode_size;
+ }
+
+ return scale;
+}
+
/* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct
PRECISION size for corresponding machine_mode. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 15b9317a8ce..66fb07d6652 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1026,6 +1026,7 @@ extern unsigned riscv_bytes_per_vector_chunk;
extern poly_uint16 riscv_vector_chunks;
extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int);
extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
+extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
/* The number of bits and bytes in a RVV vector. */
#define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8))
#define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
index e70960c5b6d..c3d0b10271a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -65,4 +65,4 @@ test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 18 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
index dcc7a644a88..bd13ba916da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
@@ -65,4 +65,4 @@ test_vbool2_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 17 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
index 3af0513e006..99928f7b1cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
@@ -65,4 +65,4 @@ test_vbool4_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 16 } } */
+/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
2023-03-08 7:33 [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment pan2.li
@ 2023-03-08 11:31 ` Li, Pan2
2023-03-13 1:40 ` Li, Pan2
0 siblings, 1 reply; 5+ messages in thread
From: Li, Pan2 @ 2023-03-08 11:31 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng
Completed the regression test and the RISC-V backend test without any surprise.
Pan
-----Original Message-----
From: Li, Pan2 <pan2.li@intel.com>
Sent: Wednesday, March 8, 2023 3:34 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; rguenther@suse.de; Li, Pan2 <pan2.li@intel.com>
Subject: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
From: yes <pan2.li@intel.com>
Fix the bug of the rvv bool mode size by the adjustment.
Besides the mode precision (aka bit size [1, 2, 4, 8, 16, 32, 64]) of the vbool*_t, the mode size (aka byte size) will be adjusted to [1, 1, 1, 1, 2, 4, 8] according to the rvv spec 1.0 isa. The adjustment will provide correct information for the underlying redundant instruction elimiation.
Given the below sample code:
{
vbool1_t v1 = *(vbool1_t*)in;
vbool64_t v2 = *(vbool64_t*)in;
*(vbool1_t*)(out + 100) = v1;
*(vbool64_t*)(out + 200) = v2;
}
Before the size adjustment:
csrr t0,vlenb
slli t1,t0,1
csrr a3,vlenb
sub sp,sp,t1
slli a4,a3,1
add a4,a4,sp
addi a2,a1,100
vsetvli a5,zero,e8,m8,ta,ma
sub a3,a4,a3
vlm.v v24,0(a0)
vsm.v v24,0(a2)
vsm.v v24,0(a3)
addi a1,a1,200
csrr t0,vlenb
vsetvli a4,zero,e8,mf8,ta,ma
slli t1,t0,1
vlm.v v24,0(a3)
vsm.v v24,0(a1)
add sp,sp,t1
jr ra
After the size adjustment:
addi a3,a1,100
vsetvli a4,zero,e8,m8,ta,ma
addi a1,a1,200
vlm.v v24,0(a0)
vsm.v v24,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v24,0(a0)
vsm.v v24,0(a1)
ret
Additionally, the size adjust cannot cover all possible combinations of the vbool*_t code pattern like above. We will take a look into it in another patches.
PR 108185
PR 108654
gcc/ChangeLog:
* config/riscv/riscv-modes.def (ADJUST_BYTESIZE):
* config/riscv/riscv.cc (riscv_v_adjust_bytesize):
* config/riscv/riscv.h (riscv_v_adjust_bytesize):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr108185-1.c:
* gcc.target/riscv/rvv/base/pr108185-2.c:
* gcc.target/riscv/rvv/base/pr108185-3.c:
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
---
gcc/config/riscv/riscv-modes.def | 14 ++++++------
gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++
gcc/config/riscv/riscv.h | 1 +
.../gcc.target/riscv/rvv/base/pr108185-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-2.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-3.c | 2 +-
6 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index 110bddce851..4cf7cf8b1c6 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -64,13 +64,13 @@ ADJUST_ALIGNMENT (VNx16BI, 1); ADJUST_ALIGNMENT (VNx32BI, 1); ADJUST_ALIGNMENT (VNx64BI, 1);
-ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx2BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8));
+ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1));
+ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1));
+ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1));
+ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1));
+ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2));
+ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4));
+ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8));
ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1)); ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2)); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e7b7d87cebc..428fbb28fae 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1003,6 +1003,28 @@ riscv_v_adjust_nunits (machine_mode mode, int scale)
return scale;
}
+/* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct
+ BYTE size for corresponding machine_mode. */
+
+poly_int64
+riscv_v_adjust_bytesize (machine_mode mode, int scale) {
+ if (riscv_v_ext_vector_mode_p (mode))
+ {
+ poly_uint16 mode_size = GET_MODE_SIZE (mode);
+
+ if (maybe_eq (mode_size, (uint16_t)-1))
+ mode_size = riscv_vector_chunks * scale;
+
+ if (known_gt (mode_size, BYTES_PER_RISCV_VECTOR))
+ mode_size = BYTES_PER_RISCV_VECTOR;
+
+ return mode_size;
+ }
+
+ return scale;
+}
+
/* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct
PRECISION size for corresponding machine_mode. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 15b9317a8ce..66fb07d6652 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1026,6 +1026,7 @@ extern unsigned riscv_bytes_per_vector_chunk; extern poly_uint16 riscv_vector_chunks; extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
+extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
/* The number of bits and bytes in a RVV vector. */ #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
index e70960c5b6d..c3d0b10271a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -65,4 +65,4 @@ test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 18 } } */
+/* { dg-final { scan-assembler-times
+{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
index dcc7a644a88..bd13ba916da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
@@ -65,4 +65,4 @@ test_vbool2_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 17 } } */
+/* { dg-final { scan-assembler-times
+{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
index 3af0513e006..99928f7b1cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
@@ -65,4 +65,4 @@ test_vbool4_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 16 } } */
+/* { dg-final { scan-assembler-times
+{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
2023-03-08 11:31 ` Li, Pan2
@ 2023-03-13 1:40 ` Li, Pan2
2023-03-23 8:40 ` Kito Cheng
0 siblings, 1 reply; 5+ messages in thread
From: Li, Pan2 @ 2023-03-13 1:40 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng
Kindly reminder for this PR. Thank you all in advance.
Pan
-----Original Message-----
From: Li, Pan2
Sent: Wednesday, March 8, 2023 7:31 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com
Subject: RE: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
Completed the regression test and the RISC-V backend test without any surprise.
Pan
-----Original Message-----
From: Li, Pan2 <pan2.li@intel.com>
Sent: Wednesday, March 8, 2023 3:34 PM
To: gcc-patches@gcc.gnu.org
Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; rguenther@suse.de; Li, Pan2 <pan2.li@intel.com>
Subject: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
From: yes <pan2.li@intel.com>
Fix the bug of the rvv bool mode size by the adjustment.
Besides the mode precision (aka bit size [1, 2, 4, 8, 16, 32, 64]) of the vbool*_t, the mode size (aka byte size) will be adjusted to [1, 1, 1, 1, 2, 4, 8] according to the rvv spec 1.0 isa. The adjustment will provide correct information for the underlying redundant instruction elimiation.
Given the below sample code:
{
vbool1_t v1 = *(vbool1_t*)in;
vbool64_t v2 = *(vbool64_t*)in;
*(vbool1_t*)(out + 100) = v1;
*(vbool64_t*)(out + 200) = v2;
}
Before the size adjustment:
csrr t0,vlenb
slli t1,t0,1
csrr a3,vlenb
sub sp,sp,t1
slli a4,a3,1
add a4,a4,sp
addi a2,a1,100
vsetvli a5,zero,e8,m8,ta,ma
sub a3,a4,a3
vlm.v v24,0(a0)
vsm.v v24,0(a2)
vsm.v v24,0(a3)
addi a1,a1,200
csrr t0,vlenb
vsetvli a4,zero,e8,mf8,ta,ma
slli t1,t0,1
vlm.v v24,0(a3)
vsm.v v24,0(a1)
add sp,sp,t1
jr ra
After the size adjustment:
addi a3,a1,100
vsetvli a4,zero,e8,m8,ta,ma
addi a1,a1,200
vlm.v v24,0(a0)
vsm.v v24,0(a3)
vsetvli a5,zero,e8,mf8,ta,ma
vlm.v v24,0(a0)
vsm.v v24,0(a1)
ret
Additionally, the size adjust cannot cover all possible combinations of the vbool*_t code pattern like above. We will take a look into it in another patches.
PR 108185
PR 108654
gcc/ChangeLog:
* config/riscv/riscv-modes.def (ADJUST_BYTESIZE):
* config/riscv/riscv.cc (riscv_v_adjust_bytesize):
* config/riscv/riscv.h (riscv_v_adjust_bytesize):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr108185-1.c:
* gcc.target/riscv/rvv/base/pr108185-2.c:
* gcc.target/riscv/rvv/base/pr108185-3.c:
Signed-off-by: Pan Li <pan2.li@intel.com>
Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
---
gcc/config/riscv/riscv-modes.def | 14 ++++++------
gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++
gcc/config/riscv/riscv.h | 1 +
.../gcc.target/riscv/rvv/base/pr108185-1.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-2.c | 2 +-
.../gcc.target/riscv/rvv/base/pr108185-3.c | 2 +-
6 files changed, 33 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
index 110bddce851..4cf7cf8b1c6 100644
--- a/gcc/config/riscv/riscv-modes.def
+++ b/gcc/config/riscv/riscv-modes.def
@@ -64,13 +64,13 @@ ADJUST_ALIGNMENT (VNx16BI, 1); ADJUST_ALIGNMENT (VNx32BI, 1); ADJUST_ALIGNMENT (VNx64BI, 1);
-ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx2BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8));
+ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1));
+ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1));
+ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1));
+ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1));
+ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2));
+ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4));
+ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8));
ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1)); ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2)); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e7b7d87cebc..428fbb28fae 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1003,6 +1003,28 @@ riscv_v_adjust_nunits (machine_mode mode, int scale)
return scale;
}
+/* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct
+ BYTE size for corresponding machine_mode. */
+
+poly_int64
+riscv_v_adjust_bytesize (machine_mode mode, int scale) {
+ if (riscv_v_ext_vector_mode_p (mode))
+ {
+ poly_uint16 mode_size = GET_MODE_SIZE (mode);
+
+ if (maybe_eq (mode_size, (uint16_t)-1))
+ mode_size = riscv_vector_chunks * scale;
+
+ if (known_gt (mode_size, BYTES_PER_RISCV_VECTOR))
+ mode_size = BYTES_PER_RISCV_VECTOR;
+
+ return mode_size;
+ }
+
+ return scale;
+}
+
/* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct
PRECISION size for corresponding machine_mode. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 15b9317a8ce..66fb07d6652 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -1026,6 +1026,7 @@ extern unsigned riscv_bytes_per_vector_chunk; extern poly_uint16 riscv_vector_chunks; extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
+extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
/* The number of bits and bytes in a RVV vector. */ #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
index e70960c5b6d..c3d0b10271a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -65,4 +65,4 @@ test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 18 } } */
+/* { dg-final { scan-assembler-times
+{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
index dcc7a644a88..bd13ba916da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
@@ -65,4 +65,4 @@ test_vbool2_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 17 } } */
+/* { dg-final { scan-assembler-times
+{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
index 3af0513e006..99928f7b1cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
@@ -65,4 +65,4 @@ test_vbool4_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
-/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 16 } } */
+/* { dg-final { scan-assembler-times
+{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
--
2.34.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
2023-03-13 1:40 ` Li, Pan2
@ 2023-03-23 8:40 ` Kito Cheng
2023-03-23 9:38 ` Li, Pan2
0 siblings, 1 reply; 5+ messages in thread
From: Kito Cheng @ 2023-03-23 8:40 UTC (permalink / raw)
To: Li, Pan2; +Cc: gcc-patches, juzhe.zhong, kito.cheng
committed, thanks for the reminder :)
On Mon, Mar 13, 2023 at 9:40 AM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Kindly reminder for this PR. Thank you all in advance.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Wednesday, March 8, 2023 7:31 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com
> Subject: RE: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
>
> Completed the regression test and the RISC-V backend test without any surprise.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2 <pan2.li@intel.com>
> Sent: Wednesday, March 8, 2023 3:34 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; rguenther@suse.de; Li, Pan2 <pan2.li@intel.com>
> Subject: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
>
> From: yes <pan2.li@intel.com>
>
> Fix the bug of the rvv bool mode size by the adjustment.
> Besides the mode precision (aka bit size [1, 2, 4, 8, 16, 32, 64]) of the vbool*_t, the mode size (aka byte size) will be adjusted to [1, 1, 1, 1, 2, 4, 8] according to the rvv spec 1.0 isa. The adjustment will provide correct information for the underlying redundant instruction elimiation.
>
> Given the below sample code:
> {
> vbool1_t v1 = *(vbool1_t*)in;
> vbool64_t v2 = *(vbool64_t*)in;
>
> *(vbool1_t*)(out + 100) = v1;
> *(vbool64_t*)(out + 200) = v2;
> }
>
> Before the size adjustment:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m8,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf8,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After the size adjustment:
> addi a3,a1,100
> vsetvli a4,zero,e8,m8,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf8,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
>
> Additionally, the size adjust cannot cover all possible combinations of the vbool*_t code pattern like above. We will take a look into it in another patches.
>
> PR 108185
> PR 108654
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-modes.def (ADJUST_BYTESIZE):
> * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
> * config/riscv/riscv.h (riscv_v_adjust_bytesize):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-1.c:
> * gcc.target/riscv/rvv/base/pr108185-2.c:
> * gcc.target/riscv/rvv/base/pr108185-3.c:
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> ---
> gcc/config/riscv/riscv-modes.def | 14 ++++++------
> gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++
> gcc/config/riscv/riscv.h | 1 +
> .../gcc.target/riscv/rvv/base/pr108185-1.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-2.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-3.c | 2 +-
> 6 files changed, 33 insertions(+), 10 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def
> index 110bddce851..4cf7cf8b1c6 100644
> --- a/gcc/config/riscv/riscv-modes.def
> +++ b/gcc/config/riscv/riscv-modes.def
> @@ -64,13 +64,13 @@ ADJUST_ALIGNMENT (VNx16BI, 1); ADJUST_ALIGNMENT (VNx32BI, 1); ADJUST_ALIGNMENT (VNx64BI, 1);
>
> -ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx2BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx16BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8));
> +ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1));
> +ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1));
> +ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1));
> +ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1));
> +ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2));
> +ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4));
> +ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8));
>
> ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1)); ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2)); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e7b7d87cebc..428fbb28fae 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1003,6 +1003,28 @@ riscv_v_adjust_nunits (machine_mode mode, int scale)
> return scale;
> }
>
> +/* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct
> + BYTE size for corresponding machine_mode. */
> +
> +poly_int64
> +riscv_v_adjust_bytesize (machine_mode mode, int scale) {
> + if (riscv_v_ext_vector_mode_p (mode))
> + {
> + poly_uint16 mode_size = GET_MODE_SIZE (mode);
> +
> + if (maybe_eq (mode_size, (uint16_t)-1))
> + mode_size = riscv_vector_chunks * scale;
> +
> + if (known_gt (mode_size, BYTES_PER_RISCV_VECTOR))
> + mode_size = BYTES_PER_RISCV_VECTOR;
> +
> + return mode_size;
> + }
> +
> + return scale;
> +}
> +
> /* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct
> PRECISION size for corresponding machine_mode. */
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 15b9317a8ce..66fb07d6652 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -1026,6 +1026,7 @@ extern unsigned riscv_bytes_per_vector_chunk; extern poly_uint16 riscv_vector_chunks; extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int); extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);
> +extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
> /* The number of bits and bytes in a RVV vector. */ #define BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk * 8)) #define BYTES_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk)) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
> index e70960c5b6d..c3d0b10271a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
> @@ -65,4 +65,4 @@ test_vbool1_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 18 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
> index dcc7a644a88..bd13ba916da 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
> @@ -65,4 +65,4 @@ test_vbool2_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 17 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
> index 3af0513e006..99928f7b1cc 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
> @@ -65,4 +65,4 @@ test_vbool4_then_vbool64(int8_t * restrict in, int8_t * restrict out) {
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 16 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
2023-03-23 8:40 ` Kito Cheng
@ 2023-03-23 9:38 ` Li, Pan2
0 siblings, 0 replies; 5+ messages in thread
From: Li, Pan2 @ 2023-03-23 9:38 UTC (permalink / raw)
To: Kito Cheng; +Cc: gcc-patches, juzhe.zhong, kito.cheng
Great! Thank you ;)
-----Original Message-----
From: Kito Cheng <kito.cheng@gmail.com>
Sent: Thursday, March 23, 2023 4:41 PM
To: Li, Pan2 <pan2.li@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; kito.cheng@sifive.com
Subject: Re: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
committed, thanks for the reminder :)
On Mon, Mar 13, 2023 at 9:40 AM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
>
> Kindly reminder for this PR. Thank you all in advance.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Wednesday, March 8, 2023 7:31 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com
> Subject: RE: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
>
> Completed the regression test and the RISC-V backend test without any surprise.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2 <pan2.li@intel.com>
> Sent: Wednesday, March 8, 2023 3:34 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zhong@rivai.ai; kito.cheng@sifive.com; rguenther@suse.de;
> Li, Pan2 <pan2.li@intel.com>
> Subject: [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment
>
> From: yes <pan2.li@intel.com>
>
> Fix the bug of the rvv bool mode size by the adjustment.
> Besides the mode precision (aka bit size [1, 2, 4, 8, 16, 32, 64]) of the vbool*_t, the mode size (aka byte size) will be adjusted to [1, 1, 1, 1, 2, 4, 8] according to the rvv spec 1.0 isa. The adjustment will provide correct information for the underlying redundant instruction elimiation.
>
> Given the below sample code:
> {
> vbool1_t v1 = *(vbool1_t*)in;
> vbool64_t v2 = *(vbool64_t*)in;
>
> *(vbool1_t*)(out + 100) = v1;
> *(vbool64_t*)(out + 200) = v2;
> }
>
> Before the size adjustment:
> csrr t0,vlenb
> slli t1,t0,1
> csrr a3,vlenb
> sub sp,sp,t1
> slli a4,a3,1
> add a4,a4,sp
> addi a2,a1,100
> vsetvli a5,zero,e8,m8,ta,ma
> sub a3,a4,a3
> vlm.v v24,0(a0)
> vsm.v v24,0(a2)
> vsm.v v24,0(a3)
> addi a1,a1,200
> csrr t0,vlenb
> vsetvli a4,zero,e8,mf8,ta,ma
> slli t1,t0,1
> vlm.v v24,0(a3)
> vsm.v v24,0(a1)
> add sp,sp,t1
> jr ra
>
> After the size adjustment:
> addi a3,a1,100
> vsetvli a4,zero,e8,m8,ta,ma
> addi a1,a1,200
> vlm.v v24,0(a0)
> vsm.v v24,0(a3)
> vsetvli a5,zero,e8,mf8,ta,ma
> vlm.v v24,0(a0)
> vsm.v v24,0(a1)
> ret
>
> Additionally, the size adjust cannot cover all possible combinations of the vbool*_t code pattern like above. We will take a look into it in another patches.
>
> PR 108185
> PR 108654
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-modes.def (ADJUST_BYTESIZE):
> * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
> * config/riscv/riscv.h (riscv_v_adjust_bytesize):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr108185-1.c:
> * gcc.target/riscv/rvv/base/pr108185-2.c:
> * gcc.target/riscv/rvv/base/pr108185-3.c:
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
> Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> ---
> gcc/config/riscv/riscv-modes.def | 14 ++++++------
> gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++
> gcc/config/riscv/riscv.h | 1 +
> .../gcc.target/riscv/rvv/base/pr108185-1.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-2.c | 2 +-
> .../gcc.target/riscv/rvv/base/pr108185-3.c | 2 +-
> 6 files changed, 33 insertions(+), 10 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-modes.def
> b/gcc/config/riscv/riscv-modes.def
> index 110bddce851..4cf7cf8b1c6 100644
> --- a/gcc/config/riscv/riscv-modes.def
> +++ b/gcc/config/riscv/riscv-modes.def
> @@ -64,13 +64,13 @@ ADJUST_ALIGNMENT (VNx16BI, 1); ADJUST_ALIGNMENT
> (VNx32BI, 1); ADJUST_ALIGNMENT (VNx64BI, 1);
>
> -ADJUST_BYTESIZE (VNx1BI, riscv_vector_chunks *
> riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx2BI,
> riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE
> (VNx4BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
> -ADJUST_BYTESIZE (VNx8BI, riscv_vector_chunks *
> riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE (VNx16BI,
> riscv_vector_chunks * riscv_bytes_per_vector_chunk); -ADJUST_BYTESIZE
> (VNx32BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk);
> -ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_nunits (VNx64BImode, 8));
> +ADJUST_BYTESIZE (VNx1BI, riscv_v_adjust_bytesize (VNx1BImode, 1));
> +ADJUST_BYTESIZE (VNx2BI, riscv_v_adjust_bytesize (VNx2BImode, 1));
> +ADJUST_BYTESIZE (VNx4BI, riscv_v_adjust_bytesize (VNx4BImode, 1));
> +ADJUST_BYTESIZE (VNx8BI, riscv_v_adjust_bytesize (VNx8BImode, 1));
> +ADJUST_BYTESIZE (VNx16BI, riscv_v_adjust_bytesize (VNx16BImode, 2));
> +ADJUST_BYTESIZE (VNx32BI, riscv_v_adjust_bytesize (VNx32BImode, 4));
> +ADJUST_BYTESIZE (VNx64BI, riscv_v_adjust_bytesize (VNx64BImode, 8));
>
> ADJUST_PRECISION (VNx1BI, riscv_v_adjust_precision (VNx1BImode, 1));
> ADJUST_PRECISION (VNx2BI, riscv_v_adjust_precision (VNx2BImode, 2));
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index e7b7d87cebc..428fbb28fae 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1003,6 +1003,28 @@ riscv_v_adjust_nunits (machine_mode mode, int scale)
> return scale;
> }
>
> +/* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct
> + BYTE size for corresponding machine_mode. */
> +
> +poly_int64
> +riscv_v_adjust_bytesize (machine_mode mode, int scale) {
> + if (riscv_v_ext_vector_mode_p (mode))
> + {
> + poly_uint16 mode_size = GET_MODE_SIZE (mode);
> +
> + if (maybe_eq (mode_size, (uint16_t)-1))
> + mode_size = riscv_vector_chunks * scale;
> +
> + if (known_gt (mode_size, BYTES_PER_RISCV_VECTOR))
> + mode_size = BYTES_PER_RISCV_VECTOR;
> +
> + return mode_size;
> + }
> +
> + return scale;
> +}
> +
> /* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct
> PRECISION size for corresponding machine_mode. */
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index
> 15b9317a8ce..66fb07d6652 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -1026,6 +1026,7 @@ extern unsigned riscv_bytes_per_vector_chunk;
> extern poly_uint16 riscv_vector_chunks; extern poly_int64
> riscv_v_adjust_nunits (enum machine_mode, int); extern poly_int64
> riscv_v_adjust_precision (enum machine_mode, int);
> +extern poly_int64 riscv_v_adjust_bytesize (enum machine_mode, int);
> /* The number of bits and bytes in a RVV vector. */ #define
> BITS_PER_RISCV_VECTOR (poly_uint16 (riscv_vector_chunks *
> riscv_bytes_per_vector_chunk * 8)) #define BYTES_PER_RISCV_VECTOR
> (poly_uint16 (riscv_vector_chunks * riscv_bytes_per_vector_chunk))
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
> index e70960c5b6d..c3d0b10271a 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
> @@ -65,4 +65,4 @@ test_vbool1_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 18 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
> index dcc7a644a88..bd13ba916da 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
> @@ -65,4 +65,4 @@ test_vbool2_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 17 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
> index 3af0513e006..99928f7b1cc 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
> @@ -65,4 +65,4 @@ test_vbool4_then_vbool64(int8_t * restrict in,
> int8_t * restrict out) {
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vsetvli\s+[a-x][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 1 } } */
> /* { dg-final { scan-assembler-times
> {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> -/* { dg-final { scan-assembler-times
> {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 16 } } */
> +/* { dg-final { scan-assembler-times
> +{vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 12 } } */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-03-23 9:38 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-08 7:33 [PATCH] RISC-V: Bugfix for rvv bool mode size adjustment pan2.li
2023-03-08 11:31 ` Li, Pan2
2023-03-13 1:40 ` Li, Pan2
2023-03-23 8:40 ` Kito Cheng
2023-03-23 9:38 ` Li, Pan2
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