[PATCH] aarch64: Specify that FEAT_MOPS sequences clobber CC

[PATCH] aarch64: Specify that FEAT_MOPS sequences clobber CC

[Kyrylo Tkachov]

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Hi all,

According to the architecture pseudocode the FEAT_MOPS sequences overwrite the NZCV flags
as part of their operation, so GCC needs to model that in the relevant RTL patterns.
For the testcase:
void g();
void foo (int a, size_t N, char *__restrict__ in,
         char *__restrict__ out)
{
  if (a != 3)
    __builtin_memcpy (out, in, N);
  if (a > 3)
    g ();
}

we will currently generate:
foo:
        cmp     w0, 3
        bne     .L6
.L1:
        ret
.L6:
        cpyfp   [x3]!, [x2]!, x1!
        cpyfm   [x3]!, [x2]!, x1!
        cpyfe   [x3]!, [x2]!, x1!
        ble     .L1 // Flags reused after CPYF* sequence
        b       g

This is wrong as the result of cmp needs to be recalculated after the MOPS sequence.
With this patch we'll insert a "cmp w0, 3" before the ble, like what clang does.

Bootstrapped and tested on aarch64-none-linux-gnu.
Pushing to trunk and to the GCC 12 branch after some baking time.

Thanks,
Kyrill

gcc/ChangeLog:

	* config/aarch64/aarch64.md (aarch64_cpymemdi): Specify clobber of CC reg.
	(*aarch64_cpymemdi): Likewise.
	(aarch64_movmemdi): Likewise.
	(aarch64_setmemdi): Likewise.
	(*aarch64_setmemdi): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/mops_5.c: New test.
	* gcc.target/aarch64/mops_6.c: Likewise.
	* gcc.target/aarch64/mops_7.c: Likewise.

[-- Attachment #2: mops-cc.patch --]
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diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 76b6898ca048c559ff7f7fba78119161b3d382f6..8a18405b04ea0df8ad74c24719cd315b265c501c 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1592,6 +1592,7 @@ (define_expand "aarch64_cpymemdi"
      [(set (match_operand 2) (const_int 0))
       (clobber (match_dup 3))
       (clobber (match_dup 4))
+      (clobber (reg:CC CC_REGNUM))
       (set (match_operand 0)
 	   (unspec:BLK [(match_operand 1) (match_dup 2)] UNSPEC_CPYMEM))])]
   "TARGET_MOPS"
@@ -1605,6 +1606,7 @@ (define_insn "*aarch64_cpymemdi"
   [(set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
    (clobber (match_operand:DI 0 "register_operand" "+&r"))
    (clobber (match_operand:DI 1 "register_operand" "+&r"))
+   (clobber (reg:CC CC_REGNUM))
    (set (mem:BLK (match_dup 0))
         (unspec:BLK [(mem:BLK (match_dup 1)) (match_dup 2)] UNSPEC_CPYMEM))]
   "TARGET_MOPS"
@@ -1635,6 +1637,7 @@ (define_insn "aarch64_movmemdi"
    (set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
    (clobber (match_operand:DI 0 "register_operand" "+&r"))
    (clobber (match_operand:DI 1 "register_operand" "+&r"))
+   (clobber (reg:CC CC_REGNUM))
    (set (mem:BLK (match_dup 0))
         (unspec:BLK [(mem:BLK (match_dup 1)) (match_dup 2)] UNSPEC_MOVMEM))])]
  "TARGET_MOPS"
@@ -1680,6 +1683,7 @@ (define_expand "aarch64_setmemdi"
   [(parallel
      [(set (match_operand 2) (const_int 0))
       (clobber (match_dup 3))
+      (clobber (reg:CC CC_REGNUM))
       (set (match_operand 0)
 	   (unspec:BLK [(match_operand 1)
 			(match_dup 2)] UNSPEC_SETMEM))])]
@@ -1692,6 +1696,7 @@ (define_expand "aarch64_setmemdi"
 (define_insn "*aarch64_setmemdi"
   [(set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
    (clobber (match_operand:DI 0 "register_operand" "+&r"))
+   (clobber (reg:CC CC_REGNUM))
    (set (mem:BLK (match_dup 0))
         (unspec:BLK [(match_operand:QI 1 "aarch64_reg_or_zero" "rZ")
 		     (match_dup 2)] UNSPEC_SETMEM))]
diff --git a/gcc/testsuite/gcc.target/aarch64/mops_5.c b/gcc/testsuite/gcc.target/aarch64/mops_5.c
new file mode 100644
index 0000000000000000000000000000000000000000..8a2626786eb510ed880850fc6ab8992482a955de
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mops_5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.6-a+mops" } */
+
+#include <stddef.h>
+
+void g();
+void foo (int a, size_t N, char *__restrict__ in,
+         char *__restrict__ out)
+{
+  if (a != 3)
+    __builtin_memcpy (out, in, N);
+  if (a > 3)
+    g ();
+}
+
+/* { dg-final { scan-assembler-times {cmp\tw0, *} 2 } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/mops_6.c b/gcc/testsuite/gcc.target/aarch64/mops_6.c
new file mode 100644
index 0000000000000000000000000000000000000000..c6c9a548351e4e8e12960138c55630b125994ed7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mops_6.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.6-a+mops" } */
+
+#include <stddef.h>
+
+void g();
+void foo (int a, size_t N, char *__restrict__ in,
+         char *__restrict__ out)
+{
+  if (a != 3)
+    __builtin_memmove (out, in, N);
+  if (a > 3)
+    g ();
+}
+
+/* { dg-final { scan-assembler-times {cmp\tw0, *} 2 } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/mops_7.c b/gcc/testsuite/gcc.target/aarch64/mops_7.c
new file mode 100644
index 0000000000000000000000000000000000000000..79720ca164c400061da1fc2d0ef7a969b603190c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mops_7.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.6-a+mops" } */
+
+#include <stddef.h>
+
+void g();
+void foo (int a, size_t N, char *__restrict__ out)
+{
+  if (a != 3)
+    __builtin_memset (out, 0, N);
+  if (a > 3)
+    g ();
+}
+
+/* { dg-final { scan-assembler-times {cmp\tw0, *} 2 } } */
+

RE: [PATCH] aarch64: Specify that FEAT_MOPS sequences clobber CC

[Kyrylo Tkachov]

> -----Original Message-----
> From: Kyrylo Tkachov
> Sent: Wednesday, November 30, 2022 5:40 PM
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH] aarch64: Specify that FEAT_MOPS sequences clobber CC
> 
> Hi all,
> 
> According to the architecture pseudocode the FEAT_MOPS sequences
> overwrite the NZCV flags
> as part of their operation, so GCC needs to model that in the relevant RTL
> patterns.
> For the testcase:
> void g();
> void foo (int a, size_t N, char *__restrict__ in,
>          char *__restrict__ out)
> {
>   if (a != 3)
>     __builtin_memcpy (out, in, N);
>   if (a > 3)
>     g ();
> }
> 
> we will currently generate:
> foo:
>         cmp     w0, 3
>         bne     .L6
> .L1:
>         ret
> .L6:
>         cpyfp   [x3]!, [x2]!, x1!
>         cpyfm   [x3]!, [x2]!, x1!
>         cpyfe   [x3]!, [x2]!, x1!
>         ble     .L1 // Flags reused after CPYF* sequence
>         b       g
> 
> This is wrong as the result of cmp needs to be recalculated after the MOPS
> sequence.
> With this patch we'll insert a "cmp w0, 3" before the ble, like what clang
> does.
> 
> Bootstrapped and tested on aarch64-none-linux-gnu.
> Pushing to trunk and to the GCC 12 branch after some baking time.

Pushed to releases/gcc-12 now.

Thanks,
Kyrill

> 
> Thanks,
> Kyrill
> 
> gcc/ChangeLog:
> 
> 	* config/aarch64/aarch64.md (aarch64_cpymemdi): Specify clobber
> of CC reg.
> 	(*aarch64_cpymemdi): Likewise.
> 	(aarch64_movmemdi): Likewise.
> 	(aarch64_setmemdi): Likewise.
> 	(*aarch64_setmemdi): Likewise.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/aarch64/mops_5.c: New test.
> 	* gcc.target/aarch64/mops_6.c: Likewise.
> 	* gcc.target/aarch64/mops_7.c: Likewise.