* [PATCH] Replace UNSPEC with RTL code for extendditi2.
@ 2022-04-01 16:59 Michael Meissner
2022-04-20 16:04 ` Ping: " Michael Meissner
0 siblings, 1 reply; 4+ messages in thread
From: Michael Meissner @ 2022-04-01 16:59 UTC (permalink / raw)
To: gcc-patches, Michael Meissner, Segher Boessenkool,
David Edelsohn, Peter Bergner, Will Schmidt
eplace UNSPEC with RTL code for extendditi2.
When I submitted my patch on March 12th for extendditi2, Segher wished I
had removed the use of the UNSPEC for the vextsd2q instruction. This
patch rewrites extendditi2_vector to use VEC_SELECT rather than UNSPEC.
I have built a power10 little endian toolchain, power9 little endian toolchain,
and a power8 big endian toolchain. There were no regressions with this
change. Is it ok to commit to the master branch? I don't see the need to back
port the change, but I can certainly do so if desired.
2022-03-31 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete.
(extendditi2_vector): Rewrite to use VEC_SELECT as a
define_expand.
(extendditi2_vector2): New insn.
---
gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a1a1ce95195..c091e5e2f47 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -358,7 +358,6 @@ (define_c_enum "unspec"
UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX
UNSPEC_XXGENPCV
UNSPEC_MTVSBM
- UNSPEC_EXTENDDITI2
UNSPEC_VCNTMB
UNSPEC_VEXPAND
UNSPEC_VEXTRACT
@@ -5083,10 +5082,25 @@ (define_insn_and_split "extendditi2"
(set_attr "type" "shift,load,vecmove,vecperm,load")])
;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg
-(define_insn "extendditi2_vector"
+(define_expand "extendditi2_vector"
+ [(use (match_operand:TI 0 "gpc_reg_operand"))
+ (use (match_operand:TI 1 "gpc_reg_operand"))]
+ "TARGET_POWER10"
+{
+ rtx dest = operands[0];
+ rtx src_v2di = gen_lowpart (V2DImode, operands[1]);
+ rtx element = GEN_INT (VECTOR_ELEMENT_SCALAR_64BIT);
+
+ emit_insn (gen_extendditi2_vector2 (dest, src_v2di, element));
+ DONE;
+})
+
+(define_insn "extendditi2_vector2"
[(set (match_operand:TI 0 "gpc_reg_operand" "=v")
- (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")]
- UNSPEC_EXTENDDITI2))]
+ (sign_extend:TI
+ (vec_select:DI
+ (match_operand:V2DI 1 "gpc_reg_operand" "v")
+ (parallel [(match_operand 2 "vsx_scalar_64bit" "wD")]))))]
"TARGET_POWER10"
"vextsd2q %0,%1"
[(set_attr "type" "vecexts")])
--
2.35.1
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meissner@linux.ibm.com
^ permalink raw reply [flat|nested] 4+ messages in thread
* Ping: [PATCH] Replace UNSPEC with RTL code for extendditi2.
2022-04-01 16:59 [PATCH] Replace UNSPEC with RTL code for extendditi2 Michael Meissner
@ 2022-04-20 16:04 ` Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2022-04-20 16:04 UTC (permalink / raw)
To: Michael Meissner, gcc-patches, Segher Boessenkool,
David Edelsohn, Peter Bergner, Will Schmidt
Ping patch. While this could be held for GCC 13, it would be nice to know
whether to keep this patch (which was asked for in one of the previous patches)
or discard it.
| Date: Fri, 1 Apr 2022 12:59:28 -0400
| From: Michael Meissner <meissner@linux.ibm.com>
| Subject: [PATCH] Replace UNSPEC with RTL code for extendditi2.
| Message-ID: <YkcvcEhL6LXwYQlG@toto.the-meissners.org>
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meissner@linux.ibm.com
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] Replace UNSPEC with RTL code for extendditi2.
2022-05-13 14:52 Michael Meissner
@ 2022-05-13 17:29 ` will schmidt
0 siblings, 0 replies; 4+ messages in thread
From: will schmidt @ 2022-05-13 17:29 UTC (permalink / raw)
To: Michael Meissner, gcc-patches, Segher Boessenkool, Kewen.Lin,
David Edelsohn, Peter Bergner
On Fri, 2022-05-13 at 10:52 -0400, Michael Meissner wrote:
> Replace UNSPEC with RTL code for extendditi2.
>
Hi,
> When I submitted my patch on March 12th for extendditi2, Segher
> wished I
> had removed the use of the UNSPEC for the vextsd2q instruction. This
> patch rewrites extendditi2_vector to use VEC_SELECT rather than
> UNSPEC.
I'd suggest a paragraph break between the two sentences.
>
> 2022-05-13 Michael Meissner <meissner@linux.ibm.com>
>
> gcc/
> * config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete.
> (extendditi2_vector): Rewrite to use VEC_SELECT as a
> define_expand.
> (extendditi2_vector2): New insn.
Ok, so per my interpretation of the patch below, it converts the
define_insn extendditi2_vector into a define_expand, and creates a new
extendditi2_vector2 instruction.
Content below seems reasonable, I've not reviewed it extensively.
Thanks
-Will
> ---
> gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++----
> 1 file changed, 18 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index a1a1ce95195..c091e5e2f47 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -358,7 +358,6 @@ (define_c_enum "unspec"
> UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX
> UNSPEC_XXGENPCV
> UNSPEC_MTVSBM
> - UNSPEC_EXTENDDITI2
> UNSPEC_VCNTMB
> UNSPEC_VEXPAND
> UNSPEC_VEXTRACT
> @@ -5083,10 +5082,25 @@ (define_insn_and_split "extendditi2"
> (set_attr "type" "shift,load,vecmove,vecperm,load")])
>
> ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in
> TI reg
> -(define_insn "extendditi2_vector"
> +(define_expand "extendditi2_vector"
> + [(use (match_operand:TI 0 "gpc_reg_operand"))
> + (use (match_operand:TI 1 "gpc_reg_operand"))]
> + "TARGET_POWER10"
> +{
> + rtx dest = operands[0];
> + rtx src_v2di = gen_lowpart (V2DImode, operands[1]);
> + rtx element = GEN_INT (VECTOR_ELEMENT_SCALAR_64BIT);
> +
> + emit_insn (gen_extendditi2_vector2 (dest, src_v2di, element));
> + DONE;
> +})
> +
> +(define_insn "extendditi2_vector2"
> [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
> - (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")]
> - UNSPEC_EXTENDDITI2))]
> + (sign_extend:TI
> + (vec_select:DI
> + (match_operand:V2DI 1 "gpc_reg_operand" "v")
> + (parallel [(match_operand 2 "vsx_scalar_64bit" "wD")]))))]
> "TARGET_POWER10"
> "vextsd2q %0,%1"
> [(set_attr "type" "vecexts")])
> --
> 2.35.3
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] Replace UNSPEC with RTL code for extendditi2.
@ 2022-05-13 14:52 Michael Meissner
2022-05-13 17:29 ` will schmidt
0 siblings, 1 reply; 4+ messages in thread
From: Michael Meissner @ 2022-05-13 14:52 UTC (permalink / raw)
To: gcc-patches, Michael Meissner, Segher Boessenkool, Kewen.Lin,
David Edelsohn, Peter Bergner, Will Schmidt
Replace UNSPEC with RTL code for extendditi2.
When I submitted my patch on March 12th for extendditi2, Segher wished I
had removed the use of the UNSPEC for the vextsd2q instruction. This
patch rewrites extendditi2_vector to use VEC_SELECT rather than UNSPEC.
2022-05-13 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete.
(extendditi2_vector): Rewrite to use VEC_SELECT as a
define_expand.
(extendditi2_vector2): New insn.
---
gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a1a1ce95195..c091e5e2f47 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -358,7 +358,6 @@ (define_c_enum "unspec"
UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX
UNSPEC_XXGENPCV
UNSPEC_MTVSBM
- UNSPEC_EXTENDDITI2
UNSPEC_VCNTMB
UNSPEC_VEXPAND
UNSPEC_VEXTRACT
@@ -5083,10 +5082,25 @@ (define_insn_and_split "extendditi2"
(set_attr "type" "shift,load,vecmove,vecperm,load")])
;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg
-(define_insn "extendditi2_vector"
+(define_expand "extendditi2_vector"
+ [(use (match_operand:TI 0 "gpc_reg_operand"))
+ (use (match_operand:TI 1 "gpc_reg_operand"))]
+ "TARGET_POWER10"
+{
+ rtx dest = operands[0];
+ rtx src_v2di = gen_lowpart (V2DImode, operands[1]);
+ rtx element = GEN_INT (VECTOR_ELEMENT_SCALAR_64BIT);
+
+ emit_insn (gen_extendditi2_vector2 (dest, src_v2di, element));
+ DONE;
+})
+
+(define_insn "extendditi2_vector2"
[(set (match_operand:TI 0 "gpc_reg_operand" "=v")
- (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")]
- UNSPEC_EXTENDDITI2))]
+ (sign_extend:TI
+ (vec_select:DI
+ (match_operand:V2DI 1 "gpc_reg_operand" "v")
+ (parallel [(match_operand 2 "vsx_scalar_64bit" "wD")]))))]
"TARGET_POWER10"
"vextsd2q %0,%1"
[(set_attr "type" "vecexts")])
--
2.35.3
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meissner@linux.ibm.com
^ permalink raw reply [flat|nested] 4+ messages in thread
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2022-04-01 16:59 [PATCH] Replace UNSPEC with RTL code for extendditi2 Michael Meissner
2022-04-20 16:04 ` Ping: " Michael Meissner
2022-05-13 14:52 Michael Meissner
2022-05-13 17:29 ` will schmidt
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