Re: [PATCH] RISC-V: Prohibit combination of 'E' and 'H'

[Jeff Law <jeffreyalaw@gmail.com>]

On 10/20/23 23:32, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
> 
> According to the ratified privileged specification (version 20211203),
> it says:
> 
>> The hypervisor extension depends on an "I" base integer ISA with 32 x
>> registers (RV32I or RV64I), not RV32E, which has only 16 x registers.
> 
> Also in the latest draft, it also prohibits RV64E with the 'H' extension.
> This commit prohibits the combination of 'E' and 'H' extensions.
> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
> 	Prohibit 'E' and 'H' combinations.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/arch-26.c: New test.
In a similar vein, GCC doesn't really care about the privileged 
extensions.  So this won't really affect code generation.  So I'll ACK, 
but going forward let's start doing the regression test.  If you need 
help setting that up, I'm sure someone here can make suggestions. 
Personally I prefer a qemu+binfmt setup as it doesn't require setting up 
a board file and explicitly calling the simulator, ie, it looks a lot 
like native testing.

jeff