Re: [PATCH v6] RISC-V: Add support for experimental zfa extension.

[Jeff Law <jeffreyalaw@gmail.com>]

On 3/10/23 05:40, Jin Ma via Gcc-patches wrote:
> This patch adds the 'Zfa' extension for riscv, which is based on:
>   https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7
> latest 'Zfa' change on the master branch of the RISC-V ISA Manual as
> of this writing.
> 
> The Wiki Page (details):
>   https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa
> 
> The binutils-gdb for 'Zfa' extension:
>   https://sourceware.org/pipermail/binutils/2022-September/122938.html
> 
> Implementation of zfa extension on LLVM:
>    https://reviews.llvm.org/rGc0947dc44109252fcc0f68a542fc6ef250d4d3a9
> 
> There are three points that need to be discussed here.
> 1. According to riscv-spec, "The FCVTMO D.W.D instruction was added principally to
>    accelerate the processing of JavaScript Numbers.", so it seems that no implementation
>    is required in the compiler.
> 2. The FROUND and FROUNDN instructions in this patch use related functions in the math
>    library, such as round, floor, ceil, etc. Since there is no interface for half-precision in
>    the math library, the instructions FROUN D.H and FROUNDN X.H have not been implemented for
>    the time being. Is it necessary to add a built-in interface belonging to riscv such as
>   __builtin_roundhf or __builtin_roundf16 to generate half floating point instructions?
> 3. As far as I know, FMINM and FMAXM instructions correspond to C23 library function fminimum
>    and fmaximum. Therefore, I have not dealt with such instructions for the time being, but have
>    simply implemented the pattern of fminm<hf\sf\df>3 and fmaxm<hf\sf\df>3. Is it necessary to
>    add a built-in interface belonging to riscv such as__builtin_fminm to generate half
>    floating-point instructions?
> 
> gcc/ChangeLog:
> 
> 	* common/config/riscv/riscv-common.cc: Add zfa extension.
> 	* config/riscv/constraints.md (Zf): Constrain the floating point number that the FLI instruction can load.
> 	* config/riscv/iterators.md (round_pattern): New.
> 	* config/riscv/predicates.md: Predicate the floating point number that the FLI instruction can load.
> 	* config/riscv/riscv-opts.h (MASK_ZFA): New.
> 	(TARGET_ZFA): New.
> 	* config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): Get the index of the
>            floating-point number that the FLI instruction can load.
> 	* config/riscv/riscv.cc (find_index_in_array): New.
> 	(riscv_float_const_rtx_index_for_fli): New.
> 	(riscv_cannot_force_const_mem): Likewise.
> 	(riscv_const_insns): Likewise.
> 	(riscv_legitimize_const_move): Likewise.
> 	(riscv_split_64bit_move_p): Exclude floating point numbers that can be loaded by FLI instructions.
> 	(riscv_output_move): Likewise.
> 	(riscv_memmodel_needs_release_fence): Likewise.
> 	(riscv_print_operand): Likewise.
> 	(riscv_secondary_memory_needed): Likewise.
> 	* config/riscv/riscv.h (GP_REG_RTX_P): New.
> 	* config/riscv/riscv.md (fminm<mode>3): New.
> 	(fmaxm<mode>3): New.
> 	(<round_pattern><ANYF:mode>2): New.
> 	(rint<ANYF:mode>2): New.
> 	(f<quiet_pattern>_quiet<ANYF:mode><X:mode>4_zfa): New.
> 
> gcc/testsuite/ChangeLog:
> 
> 	* gcc.target/riscv/zfa-fleq-fltq-rv32.c: New test.
> 	* gcc.target/riscv/zfa-fleq-fltq.c: New test.
> 	* gcc.target/riscv/zfa-fli-rv32.c: New test.
> 	* gcc.target/riscv/zfa-fli-zfh-rv32.c: New test.
> 	* gcc.target/riscv/zfa-fli-zfh.c: New test.
> 	* gcc.target/riscv/zfa-fli.c: New test.
> 	* gcc.target/riscv/zfa-fmovh-fmovp-rv32.c: New test.
> 	* gcc.target/riscv/zfa-fround-rv32.c: New test.
> 	* gcc.target/riscv/zfa-fround.c: New test.
This needs to wait for gcc-14 IMHO.

jeff