From: Palmer Dabbelt <palmer@rivosinc.com>
To: juzhe.zhong@rivai.ai
Cc: gcc-patches@gcc.gnu.org, jeffreyalaw@gmail.com
Subject: Re: [PATCH] RISC-V: Add v_uimm_operand
Date: Thu, 11 May 2023 15:31:38 -0700 (PDT) [thread overview]
Message-ID: <mhng-8b0b2af0-7f30-4579-87ce-9566e502910b@palmer-ri-x1c9a> (raw)
In-Reply-To: <969B3287F7711EA4+202305120600483436491@rivai.ai>
On Thu, 11 May 2023 15:00:48 PDT (-0700), juzhe.zhong@rivai.ai wrote:
>>> ;; V has 32-bit unsigned immediates. This happens to be the same constraint asIt should be 5-bit unsigned immediates>> ; the csr_operand, but it's not CSR related.
>>> (define_predicate "v_uimm_operand"
>>> (match_operand 0 "csr_operand"))
> To make name consistent, it should be "vector_xxxx", so I suggest it to be "vector_scalar_shift_operand".
Makes sense, I sent a v2.
next prev parent reply other threads:[~2023-05-11 22:31 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-11 22:00 钟居哲
2023-05-11 22:31 ` Palmer Dabbelt [this message]
2023-05-11 22:32 ` 钟居哲
-- strict thread matches above, loose matches on Subject: below --
2023-05-11 18:25 Palmer Dabbelt
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