From: 钟居哲 <juzhe.zhong@rivai.ai>
To: palmer <palmer@rivosinc.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>,
"Jeff Law" <jeffreyalaw@gmail.com>
Subject: Re: Re: [PATCH] RISC-V: Add v_uimm_operand
Date: Fri, 12 May 2023 06:32:06 +0800 [thread overview]
Message-ID: <40F66C2027C7977E+202305120632061082702@rivai.ai> (raw)
In-Reply-To: <mhng-8b0b2af0-7f30-4579-87ce-9566e502910b@palmer-ri-x1c9a>
[-- Attachment #1: Type: text/plain, Size: 644 bytes --]
LGTM
juzhe.zhong@rivai.ai
From: Palmer Dabbelt
Date: 2023-05-12 06:31
To: juzhe.zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add v_uimm_operand
On Thu, 11 May 2023 15:00:48 PDT (-0700), juzhe.zhong@rivai.ai wrote:
>>> ;; V has 32-bit unsigned immediates. This happens to be the same constraint asIt should be 5-bit unsigned immediates>> ; the csr_operand, but it's not CSR related.
>>> (define_predicate "v_uimm_operand"
>>> (match_operand 0 "csr_operand"))
> To make name consistent, it should be "vector_xxxx", so I suggest it to be "vector_scalar_shift_operand".
Makes sense, I sent a v2.
prev parent reply other threads:[~2023-05-11 22:32 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-11 22:00 钟居哲
2023-05-11 22:31 ` Palmer Dabbelt
2023-05-11 22:32 ` 钟居哲 [this message]
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