From: 钟居哲 <juzhe.zhong@rivai.ai>
To: gcc-patches <gcc-patches@gcc.gnu.org>
Cc: palmer <palmer@rivosinc.com>, "Jeff Law" <jeffreyalaw@gmail.com>
Subject: [PATCH] RISC-V: Add v_uimm_operand
Date: Fri, 12 May 2023 06:00:48 +0800 [thread overview]
Message-ID: <969B3287F7711EA4+202305120600483436491@rivai.ai> (raw)
[-- Attachment #1: Type: text/plain, Size: 391 bytes --]
>> ;; V has 32-bit unsigned immediates. This happens to be the same constraint asIt should be 5-bit unsigned immediates>> ; the csr_operand, but it's not CSR related.
>> (define_predicate "v_uimm_operand"
>> (match_operand 0 "csr_operand"))
To make name consistent, it should be "vector_xxxx", so I suggest it to be "vector_scalar_shift_operand".
Thanks.
juzhe.zhong@rivai.ai
next reply other threads:[~2023-05-11 22:00 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-11 22:00 钟居哲 [this message]
2023-05-11 22:31 ` Palmer Dabbelt
2023-05-11 22:32 ` 钟居哲
-- strict thread matches above, loose matches on Subject: below --
2023-05-11 18:25 Palmer Dabbelt
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