* [PATCH] rtl: AArch64: New RTL for ABD
@ 2023-05-09 16:14 Oluwatamilore Adebayo
2023-05-16 12:30 ` Richard Sandiford
0 siblings, 1 reply; 8+ messages in thread
From: Oluwatamilore Adebayo @ 2023-05-09 16:14 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.guenther, Richard Sandiford
[-- Attachment #1: Type: text/plain, Size: 16134 bytes --]
From afa416dab831795f7e1114da2fb9e94ea3b8c519 Mon Sep 17 00:00:00 2001
From: oluade01 <oluwatamilore.adebayo@arm.com>
Date: Fri, 14 Apr 2023 15:10:07 +0100
Subject: [PATCH 2/4] AArch64: New RTL for ABD
This patch adds new RTL and tests for sabd and uabd
PR tree-optimization/109156
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (sabd, uabd):
Change the mode to 3.
* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>):
Rename to <su>abd<mode>3.
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Rename
to <su>abd<mode>3.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/abd.h: New file.
* gcc.target/aarch64/abd_2.c: New test.
* gcc.target/aarch64/abd_3.c: New test.
* gcc.target/aarch64/abd_4.c: New test.
* gcc.target/aarch64/abd_run_1.c: New test.
* gcc.target/aarch64/sve/sve/abd_1.c: New test.
* gcc.target/aarch64/sve/sve/abd_2.c: New test.
---
gcc/config/aarch64/aarch64-simd-builtins.def | 6 +-
gcc/config/aarch64/aarch64-simd.md | 4 +-
gcc/config/aarch64/aarch64-sve.md | 4 +-
gcc/testsuite/gcc.target/aarch64/abd.h | 62 +++++++++++++
gcc/testsuite/gcc.target/aarch64/abd_2.c | 34 +++++++
gcc/testsuite/gcc.target/aarch64/abd_3.c | 34 +++++++
gcc/testsuite/gcc.target/aarch64/abd_4.c | 33 +++++++
gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 93 ++++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 34 +++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 33 +++++++
10 files changed, 330 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd.h
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_4.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_run_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 1beaa08c1e7c94bc13a64865ddb677345534699c..3efbf0a1874f6242e69665b8316d9a7d62a9c8cf 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -194,9 +194,9 @@
BUILTIN_VDQV_L (UNOP, saddlv, 0, NONE)
BUILTIN_VDQV_L (UNOPU, uaddlv, 0, NONE)
- /* Implemented by aarch64_<su>abd<mode>. */
- BUILTIN_VDQ_BHSI (BINOP, sabd, 0, NONE)
- BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, NONE)
+ /* Implemented by <su>abd<mode>3. */
+ BUILTIN_VDQ_BHSI (BINOP, sabd, 3, NONE)
+ BUILTIN_VDQ_BHSI (BINOPU, uabd, 3, NONE)
/* Implemented by aarch64_<su>aba<mode>. */
BUILTIN_VDQ_BHSI (TERNOP, saba, 0, NONE)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index cb2223d29c2d97d6d396b4eca166463369819ca6..f52c148a80589a48befb71135e90aa02a2b253e7 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -915,7 +915,7 @@ (define_insn "aarch64_abs<mode>"
;; So (ABS:QI (minus:QI 64 -128)) == (ABS:QI (192 or -64 signed)) == 64.
;; Whereas SABD would return 192 (-64 signed) on the above example.
;; Use MINUS ([us]max (op1, op2), [us]min (op1, op2)) instead.
-(define_insn "aarch64_<su>abd<mode>"
+(define_insn "<su>abd<mode>3"
[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
(minus:VDQ_BHSI
(USMAX:VDQ_BHSI
@@ -1080,7 +1080,7 @@ (define_expand "<su>sadv16qi"
{
rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode));
rtx abd = gen_reg_rtx (V16QImode);
- emit_insn (gen_aarch64_<su>abdv16qi (abd, operands[1], operands[2]));
+ emit_insn (gen_<su>abdv16qi3 (abd, operands[1], operands[2]));
emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3]));
DONE;
}
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 4b4c02c90fec6ce1ff15a8b2a5df348224a307b7..5966a33a3cc471f8c2e875b9e3a6a8a8ddc6af17 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -4001,7 +4001,7 @@ (define_insn_and_rewrite "*aarch64_adr_shift_uxtw"
;; -------------------------------------------------------------------------
;; Unpredicated integer absolute difference.
-(define_expand "<su>abd<mode>_3"
+(define_expand "<su>abd<mode>3"
[(use (match_operand:SVE_I 0 "register_operand"))
(USMAX:SVE_I
(match_operand:SVE_I 1 "register_operand")
@@ -6973,7 +6973,7 @@ (define_expand "<su>sad<vsi2qi>"
{
rtx ones = force_reg (<VSI2QI>mode, CONST1_RTX (<VSI2QI>mode));
rtx diff = gen_reg_rtx (<VSI2QI>mode);
- emit_insn (gen_<su>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
+ emit_insn (gen_<su>abd<vsi2qi>3 (diff, operands[1], operands[2]));
emit_insn (gen_udot_prod<vsi2qi> (operands[0], diff, ones, operands[3]));
DONE;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/abd.h b/gcc/testsuite/gcc.target/aarch64/abd.h
new file mode 100644
index 0000000000000000000000000000000000000000..bc38e8508056cf2623cddd6053bf1cec3fa4ece4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd.h
@@ -0,0 +1,62 @@
+#ifdef ABD_IDIOM
+
+#define TEST1(S, TYPE) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST2(S, TYPE1, TYPE2) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE2 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE3 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#endif
+
+#ifdef ABD_ABS
+
+#define TEST1(S, TYPE) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST2(S, TYPE1, TYPE2) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..45bcfabe05a395f6775f78f28c73eb536ba5654e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..e7079cdd4a3e37c9e22f89cff301451be1441bc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..da9598193aec72fa40a02d25d88e7c31a39153f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_IDIOM
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 8 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7bb0a801415ffeab235bd636032112228255e836
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 16
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+#define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 }
+#define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 }
+#define B { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25 }
+#define GOLD { 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75 }
+
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+
+s8 sc_out[] = EMPTY;
+u8 uc_out[] = EMPTY;
+s16 ss_out[] = EMPTY;
+u16 us_out[] = EMPTY;
+s32 si_out[] = EMPTY;
+u32 ui_out[] = EMPTY;
+
+s8 sc_A[] = sA;
+s8 sc_B[] = B;
+u8 uc_A[] = uA;
+u8 uc_B[] = B;
+
+s16 ss_A[] = sA;
+s16 ss_B[] = B;
+u16 us_A[] = uA;
+u16 us_B[] = B;
+
+s32 si_A[] = sA;
+s32 si_B[] = B;
+u32 ui_A[] = uA;
+u32 ui_B[] = B;
+
+s8 sc_gold[] = GOLD;
+u8 uc_gold[] = GOLD;
+s16 ss_gold[] = GOLD;
+u16 us_gold[] = GOLD;
+s32 si_gold[] = GOLD;
+u32 ui_gold[] = GOLD;
+
+extern void abort (void);
+
+#define CLEAR(arr) \
+for (int i = 0; i < N; i++) \
+ arr[i] = 0;
+
+#define COMPARE(A, B) \
+for (int i = 0; i < N; i++) \
+ if (A[i] != B[i]) \
+ abort();
+
+int main ()
+{
+ fn_signed_char (sc_A, sc_B, sc_out);
+ COMPARE (sc_out, sc_gold);
+
+ fn_unsigned_char (uc_A, uc_B, uc_out);
+ COMPARE (uc_out, uc_gold);
+
+ fn_signed_short (ss_A, ss_B, ss_out);
+ COMPARE (ss_out, ss_gold)
+
+ fn_unsigned_short (us_A, us_B, us_out);
+ COMPARE (us_out, us_gold)
+
+ fn_signed_int (si_A, si_B, si_out);
+ COMPARE (si_out, si_gold);
+
+ fn_unsigned_int (ui_A, ui_B, ui_out);
+ COMPARE (ui_out, ui_gold);
+
+ return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..6ba111a623a344877a9d2eabda29a629a0dc8258
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..6d4b3fec76279656ebf827c386481337451f82fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_IDIOM
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 8 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 2 } } */
--
2.25.1
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0002-AArch64-New-RTL-for-ABD.patch --]
[-- Type: text/x-patch; name="0002-AArch64-New-RTL-for-ABD.patch", Size: 15660 bytes --]
From afa416dab831795f7e1114da2fb9e94ea3b8c519 Mon Sep 17 00:00:00 2001
From: oluade01 <oluwatamilore.adebayo@arm.com>
Date: Fri, 14 Apr 2023 15:10:07 +0100
Subject: [PATCH 2/4] AArch64: New RTL for ABD
This patch adds new RTL and tests for sabd and uabd
PR tree-optimization/109156
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (sabd, uabd):
Change the mode to 3.
* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>):
Rename to <su>abd<mode>3.
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Rename
to <su>abd<mode>3.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/abd.h: New file.
* gcc.target/aarch64/abd_2.c: New test.
* gcc.target/aarch64/abd_3.c: New test.
* gcc.target/aarch64/abd_4.c: New test.
* gcc.target/aarch64/abd_run_1.c: New test.
* gcc.target/aarch64/sve/sve/abd_1.c: New test.
* gcc.target/aarch64/sve/sve/abd_2.c: New test.
---
gcc/config/aarch64/aarch64-simd-builtins.def | 6 +-
gcc/config/aarch64/aarch64-simd.md | 4 +-
gcc/config/aarch64/aarch64-sve.md | 4 +-
gcc/testsuite/gcc.target/aarch64/abd.h | 62 +++++++++++++
gcc/testsuite/gcc.target/aarch64/abd_2.c | 34 +++++++
gcc/testsuite/gcc.target/aarch64/abd_3.c | 34 +++++++
gcc/testsuite/gcc.target/aarch64/abd_4.c | 33 +++++++
gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 93 ++++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 34 +++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 33 +++++++
10 files changed, 330 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd.h
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_4.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_run_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 1beaa08c1e7c94bc13a64865ddb677345534699c..3efbf0a1874f6242e69665b8316d9a7d62a9c8cf 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -194,9 +194,9 @@
BUILTIN_VDQV_L (UNOP, saddlv, 0, NONE)
BUILTIN_VDQV_L (UNOPU, uaddlv, 0, NONE)
- /* Implemented by aarch64_<su>abd<mode>. */
- BUILTIN_VDQ_BHSI (BINOP, sabd, 0, NONE)
- BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, NONE)
+ /* Implemented by <su>abd<mode>3. */
+ BUILTIN_VDQ_BHSI (BINOP, sabd, 3, NONE)
+ BUILTIN_VDQ_BHSI (BINOPU, uabd, 3, NONE)
/* Implemented by aarch64_<su>aba<mode>. */
BUILTIN_VDQ_BHSI (TERNOP, saba, 0, NONE)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index cb2223d29c2d97d6d396b4eca166463369819ca6..f52c148a80589a48befb71135e90aa02a2b253e7 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -915,7 +915,7 @@ (define_insn "aarch64_abs<mode>"
;; So (ABS:QI (minus:QI 64 -128)) == (ABS:QI (192 or -64 signed)) == 64.
;; Whereas SABD would return 192 (-64 signed) on the above example.
;; Use MINUS ([us]max (op1, op2), [us]min (op1, op2)) instead.
-(define_insn "aarch64_<su>abd<mode>"
+(define_insn "<su>abd<mode>3"
[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
(minus:VDQ_BHSI
(USMAX:VDQ_BHSI
@@ -1080,7 +1080,7 @@ (define_expand "<su>sadv16qi"
{
rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode));
rtx abd = gen_reg_rtx (V16QImode);
- emit_insn (gen_aarch64_<su>abdv16qi (abd, operands[1], operands[2]));
+ emit_insn (gen_<su>abdv16qi3 (abd, operands[1], operands[2]));
emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3]));
DONE;
}
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 4b4c02c90fec6ce1ff15a8b2a5df348224a307b7..5966a33a3cc471f8c2e875b9e3a6a8a8ddc6af17 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -4001,7 +4001,7 @@ (define_insn_and_rewrite "*aarch64_adr_shift_uxtw"
;; -------------------------------------------------------------------------
;; Unpredicated integer absolute difference.
-(define_expand "<su>abd<mode>_3"
+(define_expand "<su>abd<mode>3"
[(use (match_operand:SVE_I 0 "register_operand"))
(USMAX:SVE_I
(match_operand:SVE_I 1 "register_operand")
@@ -6973,7 +6973,7 @@ (define_expand "<su>sad<vsi2qi>"
{
rtx ones = force_reg (<VSI2QI>mode, CONST1_RTX (<VSI2QI>mode));
rtx diff = gen_reg_rtx (<VSI2QI>mode);
- emit_insn (gen_<su>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
+ emit_insn (gen_<su>abd<vsi2qi>3 (diff, operands[1], operands[2]));
emit_insn (gen_udot_prod<vsi2qi> (operands[0], diff, ones, operands[3]));
DONE;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/abd.h b/gcc/testsuite/gcc.target/aarch64/abd.h
new file mode 100644
index 0000000000000000000000000000000000000000..bc38e8508056cf2623cddd6053bf1cec3fa4ece4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd.h
@@ -0,0 +1,62 @@
+#ifdef ABD_IDIOM
+
+#define TEST1(S, TYPE) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST2(S, TYPE1, TYPE2) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE2 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE3 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#endif
+
+#ifdef ABD_ABS
+
+#define TEST1(S, TYPE) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST2(S, TYPE1, TYPE2) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..45bcfabe05a395f6775f78f28c73eb536ba5654e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..e7079cdd4a3e37c9e22f89cff301451be1441bc2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..da9598193aec72fa40a02d25d88e7c31a39153f7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_IDIOM
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 8 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7bb0a801415ffeab235bd636032112228255e836
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 16
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+#define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 }
+#define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 }
+#define B { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25 }
+#define GOLD { 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75 }
+
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+
+s8 sc_out[] = EMPTY;
+u8 uc_out[] = EMPTY;
+s16 ss_out[] = EMPTY;
+u16 us_out[] = EMPTY;
+s32 si_out[] = EMPTY;
+u32 ui_out[] = EMPTY;
+
+s8 sc_A[] = sA;
+s8 sc_B[] = B;
+u8 uc_A[] = uA;
+u8 uc_B[] = B;
+
+s16 ss_A[] = sA;
+s16 ss_B[] = B;
+u16 us_A[] = uA;
+u16 us_B[] = B;
+
+s32 si_A[] = sA;
+s32 si_B[] = B;
+u32 ui_A[] = uA;
+u32 ui_B[] = B;
+
+s8 sc_gold[] = GOLD;
+u8 uc_gold[] = GOLD;
+s16 ss_gold[] = GOLD;
+u16 us_gold[] = GOLD;
+s32 si_gold[] = GOLD;
+u32 ui_gold[] = GOLD;
+
+extern void abort (void);
+
+#define CLEAR(arr) \
+for (int i = 0; i < N; i++) \
+ arr[i] = 0;
+
+#define COMPARE(A, B) \
+for (int i = 0; i < N; i++) \
+ if (A[i] != B[i]) \
+ abort();
+
+int main ()
+{
+ fn_signed_char (sc_A, sc_B, sc_out);
+ COMPARE (sc_out, sc_gold);
+
+ fn_unsigned_char (uc_A, uc_B, uc_out);
+ COMPARE (uc_out, uc_gold);
+
+ fn_signed_short (ss_A, ss_B, ss_out);
+ COMPARE (ss_out, ss_gold)
+
+ fn_unsigned_short (us_A, us_B, us_out);
+ COMPARE (us_out, us_gold)
+
+ fn_signed_int (si_A, si_B, si_out);
+ COMPARE (si_out, si_gold);
+
+ fn_unsigned_int (ui_A, ui_B, ui_out);
+ COMPARE (ui_out, ui_gold);
+
+ return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..6ba111a623a344877a9d2eabda29a629a0dc8258
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..6d4b3fec76279656ebf827c386481337451f82fa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
@@ -0,0 +1,33 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_IDIOM
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 8 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 2 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] rtl: AArch64: New RTL for ABD
2023-05-09 16:14 [PATCH] rtl: AArch64: New RTL for ABD Oluwatamilore Adebayo
@ 2023-05-16 12:30 ` Richard Sandiford
2023-06-06 15:11 ` Oluwatamilore Adebayo
0 siblings, 1 reply; 8+ messages in thread
From: Richard Sandiford @ 2023-05-16 12:30 UTC (permalink / raw)
To: Oluwatamilore Adebayo; +Cc: gcc-patches, richard.guenther
Sorry for the slow reply.
Oluwatamilore Adebayo <Oluwatamilore.Adebayo@arm.com> writes:
> From afa416dab831795f7e1114da2fb9e94ea3b8c519 Mon Sep 17 00:00:00 2001
> From: oluade01 <oluwatamilore.adebayo@arm.com>
> Date: Fri, 14 Apr 2023 15:10:07 +0100
> Subject: [PATCH 2/4] AArch64: New RTL for ABD
>
> This patch adds new RTL and tests for sabd and uabd
>
> PR tree-optimization/109156
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-simd-builtins.def (sabd, uabd):
> Change the mode to 3.
> * config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>):
> Rename to <su>abd<mode>3.
> * config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Rename
> to <su>abd<mode>3.
Thanks. These changes look good, once the vectoriser part is sorted,
but I have some comments about the tests:
> diff --git a/gcc/testsuite/gcc.target/aarch64/abd.h b/gcc/testsuite/gcc.target/aarch64/abd.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..bc38e8508056cf2623cddd6053bf1cec3fa4ece4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/abd.h
> @@ -0,0 +1,62 @@
> +#ifdef ABD_IDIOM
> +
> +#define TEST1(S, TYPE) \
> +void fn_##S##_##TYPE (S TYPE * restrict a, \
> + S TYPE * restrict b, \
> + S TYPE * restrict out) { \
> + for (int i = 0; i < N; i++) { \
> + signed TYPE diff = b[i] - a[i]; \
> + out[i] = diff > 0 ? diff : -diff; \
> +} }
> +
> +#define TEST2(S, TYPE1, TYPE2) \
> +void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
> + (S TYPE1 * restrict a, \
> + S TYPE1 * restrict b, \
> + S TYPE2 * restrict out) { \
> + for (int i = 0; i < N; i++) { \
> + signed TYPE2 diff = b[i] - a[i]; \
> + out[i] = diff > 0 ? diff : -diff; \
> +} }
> +
> +#define TEST3(S, TYPE1, TYPE2, TYPE3) \
> +void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
> + (S TYPE1 * restrict a, \
> + S TYPE2 * restrict b, \
> + S TYPE3 * restrict out) { \
> + for (int i = 0; i < N; i++) { \
> + signed TYPE3 diff = b[i] - a[i]; \
> + out[i] = diff > 0 ? diff : -diff; \
> +} }
> +
> +#endif
> +
> +#ifdef ABD_ABS
> +
> +#define TEST1(S, TYPE) \
> +void fn_##S##_##TYPE (S TYPE * restrict a, \
> + S TYPE * restrict b, \
> + S TYPE * restrict out) { \
> + for (int i = 0; i < N; i++) \
> + out[i] = __builtin_abs(a[i] - b[i]); \
> +}
> +
> +#define TEST2(S, TYPE1, TYPE2) \
> +void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
> + (S TYPE1 * restrict a, \
> + S TYPE1 * restrict b, \
> + S TYPE2 * restrict out) { \
> + for (int i = 0; i < N; i++) \
> + out[i] = __builtin_abs(a[i] - b[i]); \
> +}
> +
> +#define TEST3(S, TYPE1, TYPE2, TYPE3) \
> +void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
> + (S TYPE1 * restrict a, \
> + S TYPE2 * restrict b, \
> + S TYPE3 * restrict out) { \
> + for (int i = 0; i < N; i++) \
> + out[i] = __builtin_abs(a[i] - b[i]); \
> +}
> +
> +#endif
It would be good to mark all of these functions with __attribute__((noipa)),
since I think interprocedural optimisations might otherwise defeat the
runtime test in abd_run_1.c (in the sense that we might end up folding
things at compile time and not testing the vector versions of the functions).
> diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..45bcfabe05a395f6775f78f28c73eb536ba5654e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c
> @@ -0,0 +1,34 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3" } */
> +
> +#pragma GCC target "+nosve"
> +#define N 1024
> +
> +#define ABD_ABS
> +#include "abd.h"
> +
> +TEST1(signed, int)
> +TEST1(signed, short)
> +TEST1(signed, char)
> +
> +TEST2(signed, char, int)
> +TEST2(signed, char, short)
> +
> +TEST3(signed, char, int, short)
> +TEST3(signed, char, short, int)
> +
> +TEST1(unsigned, int)
> +TEST1(unsigned, short)
> +TEST1(unsigned, char)
> +
> +TEST2(unsigned, char, int)
> +TEST2(unsigned, char, short)
> +
> +TEST3(unsigned, char, int, short)
> +TEST3(unsigned, char, short, int)
> +
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
> +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
> +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
There are 14 tests, and it looks like 6 of them are expected to produce
ABD instructions while 8 aren't. It isn't really clear which tests are
which though.
I think it'd help to split the file into two:
- one containing only the tests that should produce ABD, so that the
scan-assembler counts sum up to the number of tests
- one containing only the tests that cannot use ABD, with:
{ dg-final { scan-assembler-not {\tsabd\t} } }
{ dg-final { scan-assembler-not {\tuabd\t} } }
to enforce that
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..6ba111a623a344877a9d2eabda29a629a0dc8258
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
> @@ -0,0 +1,34 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3" } */
> +
> +#pragma GCC target "arch=armv8-a"
> +#define N 1024
> +
> +#define ABD_ABS
> +#include "../abd.h"
> +
> +TEST1(signed, int)
> +TEST1(signed, short)
> +TEST1(signed, char)
> +
> +TEST2(signed, char, int)
> +TEST2(signed, char, short)
> +
> +TEST3(signed, char, int, short)
> +TEST3(signed, char, short, int)
> +
> +TEST1(unsigned, int)
> +TEST1(unsigned, short)
> +TEST1(unsigned, char)
> +
> +TEST2(unsigned, char, int)
> +TEST2(unsigned, char, short)
> +
> +TEST3(unsigned, char, int, short)
> +TEST3(unsigned, char, short, int)
> +
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
> +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
> +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..6d4b3fec76279656ebf827c386481337451f82fa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
> @@ -0,0 +1,33 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O3" } */
> +
> +#pragma GCC target "arch=armv8-a"
> +#define N 1024
> +
> +#define ABD_IDIOM
> +#include "../abd.h"
> +
> +TEST1(signed, int)
> +TEST1(signed, short)
> +TEST1(signed, char)
> +
> +TEST2(signed, char, int)
> +TEST2(signed, char, short)
> +
> +TEST3(signed, char, int, short)
> +TEST3(signed, char, short, int)
> +
> +TEST1(unsigned, int)
> +TEST1(unsigned, short)
> +TEST1(unsigned, char)
> +
> +TEST2(unsigned, char, int)
> +TEST2(unsigned, char, short)
> +
> +TEST3(unsigned, char, int, short)
> +TEST3(unsigned, char, short, int)
> +
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 8 } } */
> +/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
> +/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 2 } } */
For these SVE tests, it'd be better to drop the:
#pragma GCC target "arch=armv8-a"
lines and instead allow SVE to be used as normal. We should then be
able to match the SVE instructions in the dg-final lines.
Thanks,
Richard
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] rtl: AArch64: New RTL for ABD
2023-05-16 12:30 ` Richard Sandiford
@ 2023-06-06 15:11 ` Oluwatamilore Adebayo
2023-06-06 15:17 ` [PATCH 2/2] " Oluwatamilore Adebayo
2023-06-06 17:03 ` [PATCH] rtl: " Richard Sandiford
0 siblings, 2 replies; 8+ messages in thread
From: Oluwatamilore Adebayo @ 2023-06-06 15:11 UTC (permalink / raw)
To: richard.sandiford; +Cc: Oluwatamilore.Adebayo, gcc-patches, richard.guenther
> It would be good to mark all of these functions with __attribute__((noipa)),
> since I think interprocedural optimisations might otherwise defeat the
> runtime test in abd_run_1.c (in the sense that we might end up folding
> things at compile time and not testing the vector versions of the functions).
Done.
> There are 14 tests, and it looks like 6 of them are expected to produce
> ABD instructions while 8 aren't. It isn't really clear which tests are
> which though.
>
> I think it'd help to split the file into two:
>
> - one containing only the tests that should produce ABD, so that the
> scan-assembler counts sum up to the number of tests
>
> - one containing only the tests that cannot use ABD, with:
>
> { dg-final { scan-assembler-not {\tsabd\t} } }
> { dg-final { scan-assembler-not {\tuabd\t} } }
>
> to enforce that
After adjustments made to the vectoriser part, all tests now use an abd
instruction.
> For these SVE tests, it'd be better to drop the:
>
> #pragma GCC target "arch=armv8-a"
>
> lines and instead allow SVE to be used as normal. We should then be
> able to match the SVE instructions in the dg-final lines.
Done, and changed the assembler scans to reflect this.
Patch is in the next response.
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 2/2] AArch64: New RTL for ABD
2023-06-06 15:11 ` Oluwatamilore Adebayo
@ 2023-06-06 15:17 ` Oluwatamilore Adebayo
2023-06-06 17:03 ` [PATCH] rtl: " Richard Sandiford
1 sibling, 0 replies; 8+ messages in thread
From: Oluwatamilore Adebayo @ 2023-06-06 15:17 UTC (permalink / raw)
To: oluwatamilore.adebayo; +Cc: gcc-patches, richard.guenther, richard.sandiford
From: oluade01 <oluwatamilore.adebayo@arm.com>
This patch adds new RTL and tests for sabd and uabd
PR tree-optimization/109156
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (sabd, uabd):
Change the mode to 3.
* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>):
Rename to <su>abd<mode>3.
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Rename
to <su>abd<mode>3.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/abd.h: New file.
* gcc.target/aarch64/abd_2.c: New test.
* gcc.target/aarch64/abd_3.c: New test.
* gcc.target/aarch64/abd_4.c: New test.
* gcc.target/aarch64/abd_none_2.c: New test.
* gcc.target/aarch64/abd_none_3.c: New test.
* gcc.target/aarch64/abd_none_4.c: New test.
* gcc.target/aarch64/abd_run_1.c: New test.
* gcc.target/aarch64/sve/abd_1.c: New test.
* gcc.target/aarch64/sve/abd_none_1.c: New test.
* gcc.target/aarch64/sve/abd_2.c: New test.
* gcc.target/aarch64/sve/abd_none_2.c: New test.
---
gcc/config/aarch64/aarch64-simd-builtins.def | 6 +-
gcc/config/aarch64/aarch64-simd.md | 4 +-
gcc/config/aarch64/aarch64-sve.md | 4 +-
gcc/testsuite/gcc.target/aarch64/abd.h | 68 ++++++++++++++
gcc/testsuite/gcc.target/aarch64/abd_2.c | 36 ++++++++
gcc/testsuite/gcc.target/aarch64/abd_3.c | 36 ++++++++
gcc/testsuite/gcc.target/aarch64/abd_4.c | 36 ++++++++
gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 93 ++++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 35 ++++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 35 ++++++++
10 files changed, 346 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd.h
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_4.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_run_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 1beaa08c1e7c94bc13a64865ddb677345534699c..3efbf0a1874f6242e69665b8316d9a7d62a9c8cf 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -194,9 +194,9 @@
BUILTIN_VDQV_L (UNOP, saddlv, 0, NONE)
BUILTIN_VDQV_L (UNOPU, uaddlv, 0, NONE)
- /* Implemented by aarch64_<su>abd<mode>. */
- BUILTIN_VDQ_BHSI (BINOP, sabd, 0, NONE)
- BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, NONE)
+ /* Implemented by <su>abd<mode>3. */
+ BUILTIN_VDQ_BHSI (BINOP, sabd, 3, NONE)
+ BUILTIN_VDQ_BHSI (BINOPU, uabd, 3, NONE)
/* Implemented by aarch64_<su>aba<mode>. */
BUILTIN_VDQ_BHSI (TERNOP, saba, 0, NONE)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index a567f016b354c0f0542e58e7b51c0be739882d65..da35a928bac91db61f4e9884d9c8b162c3a3c937 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -896,7 +896,7 @@ (define_insn "aarch64_abs<mode><vczle><vczbe>"
;; So (ABS:QI (minus:QI 64 -128)) == (ABS:QI (192 or -64 signed)) == 64.
;; Whereas SABD would return 192 (-64 signed) on the above example.
;; Use MINUS ([us]max (op1, op2), [us]min (op1, op2)) instead.
-(define_insn "aarch64_<su>abd<mode><vczle><vczbe>"
+(define_insn "<su>abd<mode>3"
[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
(minus:VDQ_BHSI
(USMAX:VDQ_BHSI
@@ -1087,7 +1087,7 @@ (define_expand "<su>sadv16qi"
{
rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode));
rtx abd = gen_reg_rtx (V16QImode);
- emit_insn (gen_aarch64_<su>abdv16qi (abd, operands[1], operands[2]));
+ emit_insn (gen_<su>abdv16qi3 (abd, operands[1], operands[2]));
emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3]));
DONE;
}
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 2898b85376b831c2728b806e0f2079086345f1fe..2de651a1989c6b36272dd78a8744c700ebc75c1a 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -4001,7 +4001,7 @@ (define_insn_and_rewrite "*aarch64_adr_shift_uxtw"
;; -------------------------------------------------------------------------
;; Unpredicated integer absolute difference.
-(define_expand "<su>abd<mode>_3"
+(define_expand "<su>abd<mode>3"
[(use (match_operand:SVE_I 0 "register_operand"))
(USMAX:SVE_I
(match_operand:SVE_I 1 "register_operand")
@@ -6973,7 +6973,7 @@ (define_expand "<su>sad<vsi2qi>"
{
rtx ones = force_reg (<VSI2QI>mode, CONST1_RTX (<VSI2QI>mode));
rtx diff = gen_reg_rtx (<VSI2QI>mode);
- emit_insn (gen_<su>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
+ emit_insn (gen_<su>abd<vsi2qi>3 (diff, operands[1], operands[2]));
emit_insn (gen_udot_prod<vsi2qi> (operands[0], diff, ones, operands[3]));
DONE;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/abd.h b/gcc/testsuite/gcc.target/aarch64/abd.h
new file mode 100644
index 0000000000000000000000000000000000000000..b95fd908d91d9e576e4d76638844e22deb50a006
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd.h
@@ -0,0 +1,68 @@
+#ifdef ABD_IDIOM
+
+#define TEST1(S, TYPE) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST2(S, TYPE1, TYPE2) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE2 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE3 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#endif
+
+#ifdef ABD_ABS
+
+#define TEST1(S, TYPE) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST2(S, TYPE1, TYPE2) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..a350a9a3c0e6e82b0be4d19a83cef36c5e3f9225
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 10 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..76021fbf8f91f2c656f9dc5eefa17f5c2c393356
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 10 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..c8baf1bfa042edf8ab6e4f90a8b8ad2388e8051c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_IDIOM
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, short, int)
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 9 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 4 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7bb0a801415ffeab235bd636032112228255e836
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 16
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+#define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 }
+#define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 }
+#define B { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25 }
+#define GOLD { 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75 }
+
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+
+s8 sc_out[] = EMPTY;
+u8 uc_out[] = EMPTY;
+s16 ss_out[] = EMPTY;
+u16 us_out[] = EMPTY;
+s32 si_out[] = EMPTY;
+u32 ui_out[] = EMPTY;
+
+s8 sc_A[] = sA;
+s8 sc_B[] = B;
+u8 uc_A[] = uA;
+u8 uc_B[] = B;
+
+s16 ss_A[] = sA;
+s16 ss_B[] = B;
+u16 us_A[] = uA;
+u16 us_B[] = B;
+
+s32 si_A[] = sA;
+s32 si_B[] = B;
+u32 ui_A[] = uA;
+u32 ui_B[] = B;
+
+s8 sc_gold[] = GOLD;
+u8 uc_gold[] = GOLD;
+s16 ss_gold[] = GOLD;
+u16 us_gold[] = GOLD;
+s32 si_gold[] = GOLD;
+u32 ui_gold[] = GOLD;
+
+extern void abort (void);
+
+#define CLEAR(arr) \
+for (int i = 0; i < N; i++) \
+ arr[i] = 0;
+
+#define COMPARE(A, B) \
+for (int i = 0; i < N; i++) \
+ if (A[i] != B[i]) \
+ abort();
+
+int main ()
+{
+ fn_signed_char (sc_A, sc_B, sc_out);
+ COMPARE (sc_out, sc_gold);
+
+ fn_unsigned_char (uc_A, uc_B, uc_out);
+ COMPARE (uc_out, uc_gold);
+
+ fn_signed_short (ss_A, ss_B, ss_out);
+ COMPARE (ss_out, ss_gold)
+
+ fn_unsigned_short (us_A, us_B, us_out);
+ COMPARE (us_out, us_gold)
+
+ fn_signed_int (si_A, si_B, si_out);
+ COMPARE (si_out, si_gold);
+
+ fn_unsigned_int (ui_A, ui_B, ui_out);
+ COMPARE (ui_out, ui_gold);
+
+ return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..59bd9fdacfba66d405da1a1c42e0b5bfab9cff05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_ABS
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 4 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..adc33c2e9ef32f6dca323ae073eb64d321a6ca4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_IDIOM
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 6 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 4 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] rtl: AArch64: New RTL for ABD
2023-06-06 15:11 ` Oluwatamilore Adebayo
2023-06-06 15:17 ` [PATCH 2/2] " Oluwatamilore Adebayo
@ 2023-06-06 17:03 ` Richard Sandiford
2023-06-08 10:37 ` Oluwatamilore Adebayo
1 sibling, 1 reply; 8+ messages in thread
From: Richard Sandiford @ 2023-06-06 17:03 UTC (permalink / raw)
To: Oluwatamilore Adebayo; +Cc: gcc-patches, richard.guenther
Oluwatamilore Adebayo <oluwatamilore.adebayo@arm.com> writes:
>> It would be good to mark all of these functions with __attribute__((noipa)),
>> since I think interprocedural optimisations might otherwise defeat the
>> runtime test in abd_run_1.c (in the sense that we might end up folding
>> things at compile time and not testing the vector versions of the functions).
>
> Done.
>
>> There are 14 tests, and it looks like 6 of them are expected to produce
>> ABD instructions while 8 aren't. It isn't really clear which tests are
>> which though.
>>
>> I think it'd help to split the file into two:
>>
>> - one containing only the tests that should produce ABD, so that the
>> scan-assembler counts sum up to the number of tests
>>
>> - one containing only the tests that cannot use ABD, with:
>>
>> { dg-final { scan-assembler-not {\tsabd\t} } }
>> { dg-final { scan-assembler-not {\tuabd\t} } }
>>
>> to enforce that
>
> After adjustments made to the vectoriser part, all tests now use an abd
> instruction.
Ah, that's a problem. Sorry, I didn't review 1/2 closely enough.
For:
> + /* Failed to find a widen operation so we check for a regular MINUS_EXPR. */
> + if (diff
> + && gimple_assign_rhs_code (diff) == MINUS_EXPR
> + && (TYPE_UNSIGNED (abs_type) || TYPE_OVERFLOW_UNDEFINED (abs_type)))
> + {
> + *half_type = NULL_TREE;
> + return true;
> + }
the condition should instead be:
if (diff
&& gimple_assign_rhs_code (diff) == MINUS_EXPR
&& TYPE_OVERFLOW_UNDEFINED (TREE_TYPE (abs_oprnd)))
{
*half_type = NULL_TREE;
return true;
}
That is, we rely on overflow being undefined, so we need to check
TYPE_OVERFLOW_UNDEFINED on the type of the subtraction (rather than
abs_type, which is the type of ABS input, and at this point can be
different from TREE_TYPE (abs_oprnd)).
Then fn_unsigned_int and fn_unsigned_char_int_short correctly
avoid using SABD. The output for the other tests looks right.
It would be good to add a:
/* { dg-final { scan-assembler-not {\tabs\t} } } */
to be the positive tests, to make it more obvious that all separate
ABS instructions are elided.
Thanks,
Richard
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] rtl: AArch64: New RTL for ABD
2023-06-06 17:03 ` [PATCH] rtl: " Richard Sandiford
@ 2023-06-08 10:37 ` Oluwatamilore Adebayo
2023-06-08 10:38 ` [PATCH 2/2] " Oluwatamilore Adebayo
0 siblings, 1 reply; 8+ messages in thread
From: Oluwatamilore Adebayo @ 2023-06-08 10:37 UTC (permalink / raw)
To: richard.sandiford; +Cc: gcc-patches, oluwatamilore.adebayo, richard.guenther
> It would be good to add a:
>
> /* { dg-final { scan-assembler-not {\tabs\t} } } */
>
> to be the positive tests, to make it more obvious that all separate
> ABS instructions are elided.
Done.
Patch is in the next response.
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 2/2] AArch64: New RTL for ABD
2023-06-08 10:37 ` Oluwatamilore Adebayo
@ 2023-06-08 10:38 ` Oluwatamilore Adebayo
2023-06-13 8:27 ` Oluwatamilore Adebayo
0 siblings, 1 reply; 8+ messages in thread
From: Oluwatamilore Adebayo @ 2023-06-08 10:38 UTC (permalink / raw)
To: oluwatamilore.adebayo; +Cc: gcc-patches, richard.guenther, richard.sandiford
From: oluade01 <oluwatamilore.adebayo@arm.com>
This patch adds new RTL and tests for sabd and uabd
PR tree-optimization/109156
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (sabd, uabd):
Change the mode to 3.
* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>):
Rename to <su>abd<mode>3.
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Rename
to <su>abd<mode>3.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/abd.h: New file.
* gcc.target/aarch64/abd_2.c: New test.
* gcc.target/aarch64/abd_3.c: New test.
* gcc.target/aarch64/abd_4.c: New test.
* gcc.target/aarch64/abd_none_2.c: New test.
* gcc.target/aarch64/abd_none_3.c: New test.
* gcc.target/aarch64/abd_none_4.c: New test.
* gcc.target/aarch64/abd_run_1.c: New test.
* gcc.target/aarch64/sve/abd_1.c: New test.
* gcc.target/aarch64/sve/abd_none_1.c: New test.
* gcc.target/aarch64/sve/abd_2.c: New test.
* gcc.target/aarch64/sve/abd_none_2.c: New test.
---
gcc/config/aarch64/aarch64-simd-builtins.def | 6 +-
gcc/config/aarch64/aarch64-simd.md | 4 +-
gcc/config/aarch64/aarch64-sve.md | 4 +-
gcc/testsuite/gcc.target/aarch64/abd.h | 68 ++++++++++++++
gcc/testsuite/gcc.target/aarch64/abd_2.c | 35 +++++++
gcc/testsuite/gcc.target/aarch64/abd_3.c | 36 +++++++
gcc/testsuite/gcc.target/aarch64/abd_4.c | 30 ++++++
gcc/testsuite/gcc.target/aarch64/abd_none_2.c | 14 +++
gcc/testsuite/gcc.target/aarch64/abd_none_3.c | 14 +++
gcc/testsuite/gcc.target/aarch64/abd_none_4.c | 19 ++++
gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 93 +++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 35 +++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 32 +++++++
.../gcc.target/aarch64/sve/abd_none_1.c | 13 +++
.../gcc.target/aarch64/sve/abd_none_2.c | 18 ++++
15 files changed, 414 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd.h
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_4.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_none_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_none_3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_none_4.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_run_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 1beaa08c1e7c94bc13a64865ddb677345534699c..3efbf0a1874f6242e69665b8316d9a7d62a9c8cf 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -194,9 +194,9 @@
BUILTIN_VDQV_L (UNOP, saddlv, 0, NONE)
BUILTIN_VDQV_L (UNOPU, uaddlv, 0, NONE)
- /* Implemented by aarch64_<su>abd<mode>. */
- BUILTIN_VDQ_BHSI (BINOP, sabd, 0, NONE)
- BUILTIN_VDQ_BHSI (BINOPU, uabd, 0, NONE)
+ /* Implemented by <su>abd<mode>3. */
+ BUILTIN_VDQ_BHSI (BINOP, sabd, 3, NONE)
+ BUILTIN_VDQ_BHSI (BINOPU, uabd, 3, NONE)
/* Implemented by aarch64_<su>aba<mode>. */
BUILTIN_VDQ_BHSI (TERNOP, saba, 0, NONE)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index a567f016b354c0f0542e58e7b51c0be739882d65..da35a928bac91db61f4e9884d9c8b162c3a3c937 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -896,7 +896,7 @@ (define_insn "aarch64_abs<mode><vczle><vczbe>"
;; So (ABS:QI (minus:QI 64 -128)) == (ABS:QI (192 or -64 signed)) == 64.
;; Whereas SABD would return 192 (-64 signed) on the above example.
;; Use MINUS ([us]max (op1, op2), [us]min (op1, op2)) instead.
-(define_insn "aarch64_<su>abd<mode><vczle><vczbe>"
+(define_insn "<su>abd<mode>3"
[(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
(minus:VDQ_BHSI
(USMAX:VDQ_BHSI
@@ -1087,7 +1087,7 @@ (define_expand "<su>sadv16qi"
{
rtx ones = force_reg (V16QImode, CONST1_RTX (V16QImode));
rtx abd = gen_reg_rtx (V16QImode);
- emit_insn (gen_aarch64_<su>abdv16qi (abd, operands[1], operands[2]));
+ emit_insn (gen_<su>abdv16qi3 (abd, operands[1], operands[2]));
emit_insn (gen_udot_prodv16qi (operands[0], abd, ones, operands[3]));
DONE;
}
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 2898b85376b831c2728b806e0f2079086345f1fe..2de651a1989c6b36272dd78a8744c700ebc75c1a 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -4001,7 +4001,7 @@ (define_insn_and_rewrite "*aarch64_adr_shift_uxtw"
;; -------------------------------------------------------------------------
;; Unpredicated integer absolute difference.
-(define_expand "<su>abd<mode>_3"
+(define_expand "<su>abd<mode>3"
[(use (match_operand:SVE_I 0 "register_operand"))
(USMAX:SVE_I
(match_operand:SVE_I 1 "register_operand")
@@ -6973,7 +6973,7 @@ (define_expand "<su>sad<vsi2qi>"
{
rtx ones = force_reg (<VSI2QI>mode, CONST1_RTX (<VSI2QI>mode));
rtx diff = gen_reg_rtx (<VSI2QI>mode);
- emit_insn (gen_<su>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
+ emit_insn (gen_<su>abd<vsi2qi>3 (diff, operands[1], operands[2]));
emit_insn (gen_udot_prod<vsi2qi> (operands[0], diff, ones, operands[3]));
DONE;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/abd.h b/gcc/testsuite/gcc.target/aarch64/abd.h
new file mode 100644
index 0000000000000000000000000000000000000000..b95fd908d91d9e576e4d76638844e22deb50a006
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd.h
@@ -0,0 +1,68 @@
+#ifdef ABD_IDIOM
+
+#define TEST1(S, TYPE) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST2(S, TYPE1, TYPE2) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE2 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE3 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#endif
+
+#ifdef ABD_ABS
+
+#define TEST1(S, TYPE) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST2(S, TYPE1, TYPE2) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..c0d41fb7ef99baf95b0f6a2e68a88f6748482af3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..4873c64f34885b3993010beafa01087569336dec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..4670ec8fe92f3cd4b1bb0a15125fc66231b2be0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_IDIOM
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, short, int)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..658e7426965ead945d0cad68ef721f176fb41665
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(unsigned, int)
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..14cfdcbde6998b527989326ff8848d071a4774e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(unsigned, int)
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..667acf2c3c8156fcf5ff9a56b40fdf2cf2aa5502
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_IDIOM
+#include "abd.h"
+
+TEST3(signed, char, int, short)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7bb0a801415ffeab235bd636032112228255e836
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 16
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+#define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 }
+#define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 }
+#define B { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25 }
+#define GOLD { 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75 }
+
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+
+s8 sc_out[] = EMPTY;
+u8 uc_out[] = EMPTY;
+s16 ss_out[] = EMPTY;
+u16 us_out[] = EMPTY;
+s32 si_out[] = EMPTY;
+u32 ui_out[] = EMPTY;
+
+s8 sc_A[] = sA;
+s8 sc_B[] = B;
+u8 uc_A[] = uA;
+u8 uc_B[] = B;
+
+s16 ss_A[] = sA;
+s16 ss_B[] = B;
+u16 us_A[] = uA;
+u16 us_B[] = B;
+
+s32 si_A[] = sA;
+s32 si_B[] = B;
+u32 ui_A[] = uA;
+u32 ui_B[] = B;
+
+s8 sc_gold[] = GOLD;
+u8 uc_gold[] = GOLD;
+s16 ss_gold[] = GOLD;
+u16 us_gold[] = GOLD;
+s32 si_gold[] = GOLD;
+u32 ui_gold[] = GOLD;
+
+extern void abort (void);
+
+#define CLEAR(arr) \
+for (int i = 0; i < N; i++) \
+ arr[i] = 0;
+
+#define COMPARE(A, B) \
+for (int i = 0; i < N; i++) \
+ if (A[i] != B[i]) \
+ abort();
+
+int main ()
+{
+ fn_signed_char (sc_A, sc_B, sc_out);
+ COMPARE (sc_out, sc_gold);
+
+ fn_unsigned_char (uc_A, uc_B, uc_out);
+ COMPARE (uc_out, uc_gold);
+
+ fn_signed_short (ss_A, ss_B, ss_out);
+ COMPARE (ss_out, ss_gold)
+
+ fn_unsigned_short (us_A, us_B, us_out);
+ COMPARE (us_out, us_gold)
+
+ fn_signed_int (si_A, si_B, si_out);
+ COMPARE (si_out, si_gold);
+
+ fn_unsigned_int (ui_A, ui_B, ui_out);
+ COMPARE (ui_out, ui_gold);
+
+ return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..e49006f90b22040f890c279ec19c490a655abd63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_ABS
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..bb17c8d6855eeee0a109b991c6610cfe7af12fd9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_IDIOM
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+TEST2(signed, short, int)
+
+TEST3(signed, char, short, int)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, int, short)
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..a4c2053c50e235e6ea6ad8bfb124889556be1657
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_ABS
+#include "../abd.h"
+
+TEST1(unsigned, int)
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..b540c38844936a17dc658acd909f3416f8887071
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_IDIOM
+#include "../abd.h"
+
+TEST3(signed, char, int, short)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 2/2] AArch64: New RTL for ABD
2023-06-08 10:38 ` [PATCH 2/2] " Oluwatamilore Adebayo
@ 2023-06-13 8:27 ` Oluwatamilore Adebayo
0 siblings, 0 replies; 8+ messages in thread
From: Oluwatamilore Adebayo @ 2023-06-13 8:27 UTC (permalink / raw)
To: oluwatamilore.adebayo; +Cc: gcc-patches, richard.guenther, richard.sandiford
From: oluade01 <oluwatamilore.adebayo@arm.com>
This patch adds new RTL and tests for sabd and uabd
PR tree-optimization/109156
gcc/ChangeLog:
* config/aarch64/aarch64-simd-builtins.def (sabd, uabd):
Change the mode to 3.
* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>):
Rename to <su>abd<mode>3.
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Rename
to <su>abd<mode>3.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/abd.h: New file.
* gcc.target/aarch64/abd_2.c: New test.
* gcc.target/aarch64/abd_3.c: New test.
* gcc.target/aarch64/abd_4.c: New test.
* gcc.target/aarch64/abd_none_2.c: New test.
* gcc.target/aarch64/abd_none_3.c: New test.
* gcc.target/aarch64/abd_none_4.c: New test.
* gcc.target/aarch64/abd_run_1.c: New test.
* gcc.target/aarch64/sve/abd_1.c: New test.
* gcc.target/aarch64/sve/abd_none_1.c: New test.
* gcc.target/aarch64/sve/abd_2.c: New test.
* gcc.target/aarch64/sve/abd_none_2.c: New test.
---
gcc/config/aarch64/aarch64-simd.md | 12 +++
gcc/config/aarch64/aarch64-sve.md | 4 +-
gcc/testsuite/gcc.target/aarch64/abd.h | 68 ++++++++++++++
gcc/testsuite/gcc.target/aarch64/abd_2.c | 35 +++++++
gcc/testsuite/gcc.target/aarch64/abd_3.c | 36 +++++++
gcc/testsuite/gcc.target/aarch64/abd_4.c | 30 ++++++
gcc/testsuite/gcc.target/aarch64/abd_none_2.c | 14 +++
gcc/testsuite/gcc.target/aarch64/abd_none_3.c | 14 +++
gcc/testsuite/gcc.target/aarch64/abd_none_4.c | 22 +++++
gcc/testsuite/gcc.target/aarch64/abd_run_1.c | 93 +++++++++++++++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_1.c | 35 +++++++
gcc/testsuite/gcc.target/aarch64/sve/abd_2.c | 29 ++++++
.../gcc.target/aarch64/sve/abd_none_1.c | 13 +++
.../gcc.target/aarch64/sve/abd_none_2.c | 21 +++++
14 files changed, 424 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd.h
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_4.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_none_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_none_3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_none_4.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/abd_run_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index a567f016b354c0f0542e58e7b51c0be739882d65..bf90202ba2ad3f62f2020486d21256f083effb07 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -910,6 +910,18 @@ (define_insn "aarch64_<su>abd<mode><vczle><vczbe>"
[(set_attr "type" "neon_abd<q>")]
)
+(define_expand "<su>abd<mode>3"
+ [(match_operand:VDQ_BHSI 0 "register_operand")
+ (USMAX:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand")
+ (match_operand:VDQ_BHSI 2 "register_operand"))]
+ "TARGET_SIMD"
+ {
+ emit_insn (gen_aarch64_<su>abd<mode> (operands[0], operands[1], operands[2]));
+ DONE;
+ }
+)
+
(define_insn "aarch64_<su>abdl<mode>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(zero_extend:<VWIDE>
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 2898b85376b831c2728b806e0f2079086345f1fe..2de651a1989c6b36272dd78a8744c700ebc75c1a 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -4001,7 +4001,7 @@ (define_insn_and_rewrite "*aarch64_adr_shift_uxtw"
;; -------------------------------------------------------------------------
;; Unpredicated integer absolute difference.
-(define_expand "<su>abd<mode>_3"
+(define_expand "<su>abd<mode>3"
[(use (match_operand:SVE_I 0 "register_operand"))
(USMAX:SVE_I
(match_operand:SVE_I 1 "register_operand")
@@ -6973,7 +6973,7 @@ (define_expand "<su>sad<vsi2qi>"
{
rtx ones = force_reg (<VSI2QI>mode, CONST1_RTX (<VSI2QI>mode));
rtx diff = gen_reg_rtx (<VSI2QI>mode);
- emit_insn (gen_<su>abd<vsi2qi>_3 (diff, operands[1], operands[2]));
+ emit_insn (gen_<su>abd<vsi2qi>3 (diff, operands[1], operands[2]));
emit_insn (gen_udot_prod<vsi2qi> (operands[0], diff, ones, operands[3]));
DONE;
}
diff --git a/gcc/testsuite/gcc.target/aarch64/abd.h b/gcc/testsuite/gcc.target/aarch64/abd.h
new file mode 100644
index 0000000000000000000000000000000000000000..b95fd908d91d9e576e4d76638844e22deb50a006
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd.h
@@ -0,0 +1,68 @@
+#ifdef ABD_IDIOM
+
+#define TEST1(S, TYPE) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST2(S, TYPE1, TYPE2) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE2 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) { \
+ signed TYPE3 diff = b[i] - a[i]; \
+ out[i] = diff > 0 ? diff : -diff; \
+} }
+
+#endif
+
+#ifdef ABD_ABS
+
+#define TEST1(S, TYPE) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE (S TYPE * restrict a, \
+ S TYPE * restrict b, \
+ S TYPE * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST2(S, TYPE1, TYPE2) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE1##_##TYPE2 \
+ (S TYPE1 * restrict a, \
+ S TYPE1 * restrict b, \
+ S TYPE2 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#define TEST3(S, TYPE1, TYPE2, TYPE3) \
+__attribute__((noipa)) \
+void fn_##S##_##TYPE1##_##TYPE2##_##TYPE3 \
+ (S TYPE1 * restrict a, \
+ S TYPE2 * restrict b, \
+ S TYPE3 * restrict out) { \
+ for (int i = 0; i < N; i++) \
+ out[i] = __builtin_abs(a[i] - b[i]); \
+}
+
+#endif
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_2.c b/gcc/testsuite/gcc.target/aarch64/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..c0d41fb7ef99baf95b0f6a2e68a88f6748482af3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_2.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_3.c b/gcc/testsuite/gcc.target/aarch64/abd_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..4873c64f34885b3993010beafa01087569336dec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_3.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 5 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 4 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 3 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_4.c b/gcc/testsuite/gcc.target/aarch64/abd_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..98aa730d6aad700e3a9a712e14adc08c9fb546c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_4.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_IDIOM
+#include "abd.h"
+
+TEST1(signed, int)
+
+TEST2(signed, char, short)
+TEST2(signed, char, int)
+TEST2(signed, short, int)
+
+TEST3(signed, char, short, int)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s, v\[0-9\]+\.4s" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */
+/* { dg-final { scan-assembler-times "sabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h, v\[0-9\]+\.8h" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..658e7426965ead945d0cad68ef721f176fb41665
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_none_2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(unsigned, int)
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_3.c b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c
new file mode 100644
index 0000000000000000000000000000000000000000..14cfdcbde6998b527989326ff8848d071a4774e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_none_3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-Ofast" } */
+
+#pragma GCC target "arch=armv8-a"
+#define N 1024
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(unsigned, int)
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_none_4.c b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c
new file mode 100644
index 0000000000000000000000000000000000000000..d612216b98bf5484783489cc48b4417ad1914b1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_none_4.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 1024
+
+#define ABD_IDIOM
+#include "abd.h"
+
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST3(signed, char, int, short)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/abd_run_1.c b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..7bb0a801415ffeab235bd636032112228255e836
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abd_run_1.c
@@ -0,0 +1,93 @@
+/* { dg-do run } */
+/* { dg-options "-O3" } */
+
+#pragma GCC target "+nosve"
+#define N 16
+
+#define ABD_ABS
+#include "abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+#define EMPTY { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
+#define sA { -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50 }
+#define uA { 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100 }
+#define B { 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25, 25 }
+#define GOLD { 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75, 75 }
+
+typedef signed char s8;
+typedef unsigned char u8;
+typedef signed short s16;
+typedef unsigned short u16;
+typedef signed int s32;
+typedef unsigned int u32;
+
+s8 sc_out[] = EMPTY;
+u8 uc_out[] = EMPTY;
+s16 ss_out[] = EMPTY;
+u16 us_out[] = EMPTY;
+s32 si_out[] = EMPTY;
+u32 ui_out[] = EMPTY;
+
+s8 sc_A[] = sA;
+s8 sc_B[] = B;
+u8 uc_A[] = uA;
+u8 uc_B[] = B;
+
+s16 ss_A[] = sA;
+s16 ss_B[] = B;
+u16 us_A[] = uA;
+u16 us_B[] = B;
+
+s32 si_A[] = sA;
+s32 si_B[] = B;
+u32 ui_A[] = uA;
+u32 ui_B[] = B;
+
+s8 sc_gold[] = GOLD;
+u8 uc_gold[] = GOLD;
+s16 ss_gold[] = GOLD;
+u16 us_gold[] = GOLD;
+s32 si_gold[] = GOLD;
+u32 ui_gold[] = GOLD;
+
+extern void abort (void);
+
+#define CLEAR(arr) \
+for (int i = 0; i < N; i++) \
+ arr[i] = 0;
+
+#define COMPARE(A, B) \
+for (int i = 0; i < N; i++) \
+ if (A[i] != B[i]) \
+ abort();
+
+int main ()
+{
+ fn_signed_char (sc_A, sc_B, sc_out);
+ COMPARE (sc_out, sc_gold);
+
+ fn_unsigned_char (uc_A, uc_B, uc_out);
+ COMPARE (uc_out, uc_gold);
+
+ fn_signed_short (ss_A, ss_B, ss_out);
+ COMPARE (ss_out, ss_gold)
+
+ fn_unsigned_short (us_A, us_B, us_out);
+ COMPARE (us_out, us_gold)
+
+ fn_signed_int (si_A, si_B, si_out);
+ COMPARE (si_out, si_gold);
+
+ fn_unsigned_int (ui_A, ui_B, ui_out);
+ COMPARE (ui_out, ui_gold);
+
+ return 0;
+}
+
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..e49006f90b22040f890c279ec19c490a655abd63
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_ABS
+#include "../abd.h"
+
+TEST1(signed, int)
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+TEST2(signed, short, int)
+
+TEST3(signed, char, int, short)
+TEST3(signed, char, short, int)
+
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST2(unsigned, char, short)
+TEST2(unsigned, char, int)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 3 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 3 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..ea64fa837b1025933ab6c339b86f0db06ffbe0e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_2.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_IDIOM
+#include "../abd.h"
+
+TEST1(signed, int)
+
+TEST2(signed, char, int)
+TEST2(signed, char, short)
+TEST2(signed, short, int)
+
+TEST3(signed, char, short, int)
+
+TEST2(unsigned, char, int)
+TEST2(unsigned, char, short)
+TEST2(unsigned, short, int)
+
+TEST3(unsigned, char, short, int)
+
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.s, p\[0-9\]/m, z\[0-9\]+\.s, z\[0-9\]+\.s" 1 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */
+/* { dg-final { scan-assembler-times "sabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.h, p\[0-9\]/m, z\[0-9\]+\.h, z\[0-9\]+\.h" 2 } } */
+/* { dg-final { scan-assembler-times "uabd\\tz\[0-9\]+\.b, p\[0-9\]/m, z\[0-9\]+\.b, z\[0-9\]+\.b" 2 } } */
+
+/* { dg-final { scan-assembler-not {\tabs\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..a4c2053c50e235e6ea6ad8bfb124889556be1657
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_ABS
+#include "../abd.h"
+
+TEST1(unsigned, int)
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c
new file mode 100644
index 0000000000000000000000000000000000000000..4862db93a81e890637ee8e02dcc9de9e0e613e91
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/abd_none_2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+#define N 1024
+
+#define ABD_IDIOM
+#include "../abd.h"
+
+TEST1(signed, short)
+TEST1(signed, char)
+
+TEST3(signed, char, int, short)
+
+TEST1(unsigned, int)
+TEST1(unsigned, short)
+TEST1(unsigned, char)
+
+TEST3(unsigned, char, int, short)
+
+/* { dg-final { scan-assembler-not {\tsabd\t} } } */
+/* { dg-final { scan-assembler-not {\tuabd\t} } } */
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-06-13 8:27 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-09 16:14 [PATCH] rtl: AArch64: New RTL for ABD Oluwatamilore Adebayo
2023-05-16 12:30 ` Richard Sandiford
2023-06-06 15:11 ` Oluwatamilore Adebayo
2023-06-06 15:17 ` [PATCH 2/2] " Oluwatamilore Adebayo
2023-06-06 17:03 ` [PATCH] rtl: " Richard Sandiford
2023-06-08 10:37 ` Oluwatamilore Adebayo
2023-06-08 10:38 ` [PATCH 2/2] " Oluwatamilore Adebayo
2023-06-13 8:27 ` Oluwatamilore Adebayo
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