* [PATCH V2] RTL_SSA: Relax PHI_MODE in phi_setup
@ 2023-07-17 14:42 juzhe.zhong
2023-07-17 14:44 ` Richard Sandiford
0 siblings, 1 reply; 2+ messages in thread
From: juzhe.zhong @ 2023-07-17 14:42 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.sandiford, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Hi, Richard.
RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc)
There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc)
When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS (inserted after RA) ICE:
rvv.c:13:1: internal compiler error: in partial_subreg_p, at rtl.h:3186
13 | }
| ^
0xf7a5b1 partial_subreg_p(machine_mode, machine_mode)
../../../riscv-gcc/gcc/rtl.h:3186
0x1407616 wider_subreg_mode(machine_mode, machine_mode)
../../../riscv-gcc/gcc/rtl.h:3252
0x2a2c6ff rtl_ssa::combine_modes(machine_mode, machine_mode)
../../../riscv-gcc/gcc/rtl-ssa/internals.inl:677
0x2a2b9a4 rtl_ssa::function_info::simplify_phi_setup(rtl_ssa::phi_info*, rtl_ssa::set_info**, bitmap_head*)
../../../riscv-gcc/gcc/rtl-ssa/functions.cc:146
0x2a2c142 rtl_ssa::function_info::simplify_phis()
../../../riscv-gcc/gcc/rtl-ssa/functions.cc:258
0x2a2b3f0 rtl_ssa::function_info::function_info(function*)
../../../riscv-gcc/gcc/rtl-ssa/functions.cc:51
0x1cebab9 pass_vsetvl::init()
../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4578
0x1cec150 pass_vsetvl::execute(function*)
../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716
The reason is that we have V32QImode (size = [32,0]) which is the mode set as regno_reg_rtx[97]
When the PHI input def comes from ENTRY BLOCK (index =0), the def->mode () = V32QImode.
But the phi_mode = VNx2QI for example (I use VLA modes intrinsic write the codes).
Then combine_modes report ICE.
gcc/ChangeLog:
* rtl-ssa/internals.inl: Fix when mode1 and mode2 are not ordred.
---
gcc/rtl-ssa/internals.inl | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/rtl-ssa/internals.inl b/gcc/rtl-ssa/internals.inl
index 0a61811289d..e49297c12b3 100644
--- a/gcc/rtl-ssa/internals.inl
+++ b/gcc/rtl-ssa/internals.inl
@@ -673,6 +673,9 @@ combine_modes (machine_mode mode1, machine_mode mode2)
if (mode2 == E_BLKmode)
return mode1;
+ if (!ordered_p (GET_MODE_SIZE (mode1), GET_MODE_SIZE (mode2)))
+ return BLKmode;
+
return wider_subreg_mode (mode1, mode2);
}
--
2.36.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH V2] RTL_SSA: Relax PHI_MODE in phi_setup
2023-07-17 14:42 [PATCH V2] RTL_SSA: Relax PHI_MODE in phi_setup juzhe.zhong
@ 2023-07-17 14:44 ` Richard Sandiford
0 siblings, 0 replies; 2+ messages in thread
From: Richard Sandiford @ 2023-07-17 14:44 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches
juzhe.zhong@rivai.ai writes:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> Hi, Richard.
>
> RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc)
> There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc)
>
> When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS (inserted after RA) ICE:
> rvv.c:13:1: internal compiler error: in partial_subreg_p, at rtl.h:3186
> 13 | }
> | ^
> 0xf7a5b1 partial_subreg_p(machine_mode, machine_mode)
> ../../../riscv-gcc/gcc/rtl.h:3186
> 0x1407616 wider_subreg_mode(machine_mode, machine_mode)
> ../../../riscv-gcc/gcc/rtl.h:3252
> 0x2a2c6ff rtl_ssa::combine_modes(machine_mode, machine_mode)
> ../../../riscv-gcc/gcc/rtl-ssa/internals.inl:677
> 0x2a2b9a4 rtl_ssa::function_info::simplify_phi_setup(rtl_ssa::phi_info*, rtl_ssa::set_info**, bitmap_head*)
> ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:146
> 0x2a2c142 rtl_ssa::function_info::simplify_phis()
> ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:258
> 0x2a2b3f0 rtl_ssa::function_info::function_info(function*)
> ../../../riscv-gcc/gcc/rtl-ssa/functions.cc:51
> 0x1cebab9 pass_vsetvl::init()
> ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4578
> 0x1cec150 pass_vsetvl::execute(function*)
> ../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716
>
> The reason is that we have V32QImode (size = [32,0]) which is the mode set as regno_reg_rtx[97]
> When the PHI input def comes from ENTRY BLOCK (index =0), the def->mode () = V32QImode.
> But the phi_mode = VNx2QI for example (I use VLA modes intrinsic write the codes).
> Then combine_modes report ICE.
>
> gcc/ChangeLog:
>
> * rtl-ssa/internals.inl: Fix when mode1 and mode2 are not ordred.
OK if it passes testing.
Thanks,
Richard
> ---
> gcc/rtl-ssa/internals.inl | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/gcc/rtl-ssa/internals.inl b/gcc/rtl-ssa/internals.inl
> index 0a61811289d..e49297c12b3 100644
> --- a/gcc/rtl-ssa/internals.inl
> +++ b/gcc/rtl-ssa/internals.inl
> @@ -673,6 +673,9 @@ combine_modes (machine_mode mode1, machine_mode mode2)
> if (mode2 == E_BLKmode)
> return mode1;
>
> + if (!ordered_p (GET_MODE_SIZE (mode1), GET_MODE_SIZE (mode2)))
> + return BLKmode;
> +
> return wider_subreg_mode (mode1, mode2);
> }
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-07-17 14:42 [PATCH V2] RTL_SSA: Relax PHI_MODE in phi_setup juzhe.zhong
2023-07-17 14:44 ` Richard Sandiford
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