* [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of
@ 2024-03-01 6:27 demin.han
2024-03-01 6:27 ` [PATCH 1/5] RISC-V: Remove float vector eqne pattern demin.han
` (5 more replies)
0 siblings, 6 replies; 32+ messages in thread
From: demin.han @ 2024-03-01 6:27 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, jeffreyalaw
We expect:
flw
...
vmfxx.vf
For simplicity of supporting vx and vf, two refactors completed first.
1. remove eqne pattern; any special case or reason for eqne when first added?
2. refactor duplicate code.
demin.han (5):
RISC-V: Remove float vector eqne pattern
RISC-V: Refactor expand_vec_cmp
RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
RISC-V: Remove integer vector eqne pattern
RISC-V: Support vmsxx.vx for autovec comparison of vec and imm
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/predicates.md | 4 +-
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv-string.cc | 4 +-
gcc/config/riscv/riscv-v.cc | 94 ++---
.../riscv/riscv-vector-builtins-bases.cc | 7 -
gcc/config/riscv/riscv.cc | 2 +-
gcc/config/riscv/vector.md | 365 +-----------------
.../riscv/rvv/autovec/cmp/vcond-1.c | 48 ++-
9 files changed, 105 insertions(+), 423 deletions(-)
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-03-01 6:27 [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of demin.han
@ 2024-03-01 6:27 ` demin.han
2024-03-01 7:23 ` 钟居哲
2024-06-08 20:50 ` Jeff Law
2024-03-01 6:27 ` [PATCH 2/5] RISC-V: Refactor expand_vec_cmp demin.han
` (4 subsequent siblings)
5 siblings, 2 replies; 32+ messages in thread
From: demin.han @ 2024-03-01 6:27 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, jeffreyalaw
We can unify eqne and other comparison operations.
Tested on RV32 and RV64
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_scalar): Ditto
(*pred_eqne<mode>_scalar_narrow): Ditto
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
.../riscv/riscv-vector-builtins-bases.cc | 4 -
gcc/config/riscv/vector.md | 86 -------------------
2 files changed, 90 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b6f6e4ff37e..d414721ede8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1420,10 +1420,6 @@ public:
switch (e.op_info->op)
{
case OP_TYPE_vf: {
- if (CODE == EQ || CODE == NE)
- return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
- e.vector_mode ()));
- else
return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
e.vector_mode ()));
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index ab6e099852d..9210d7c28ad 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7520,92 +7520,6 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-(define_expand "@pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 6 "vector_length_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand"))
- (match_operand:V_VLSF 4 "register_operand")])
- (match_operand:<VM> 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
- {})
-
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 4 "register_operand" " f"))
- (match_operand:V_VLSF 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR"
- "vmf%B2.vf\t%0,%3,%4,v0.t"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))
- (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
- "vmf%B3.vf\t%0,%4,%5%p1"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
- (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
- "vmf%B3.vf\t%0,%4,%5%p1"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point merge
;; -------------------------------------------------------------------------------
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 2/5] RISC-V: Refactor expand_vec_cmp
2024-03-01 6:27 [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of demin.han
2024-03-01 6:27 ` [PATCH 1/5] RISC-V: Remove float vector eqne pattern demin.han
@ 2024-03-01 6:27 ` demin.han
2024-03-01 7:32 ` 钟居哲
2024-03-01 6:27 ` [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm demin.han
` (3 subsequent siblings)
5 siblings, 1 reply; 32+ messages in thread
From: demin.han @ 2024-03-01 6:27 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, jeffreyalaw
There are two expand_vec_cmp functions.
They have same structure and similar code.
We can use default arguments instead of overloading.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
* config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
(expand_vec_cmp_float): Adapt arguments
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv-v.cc | 44 +++++++++++----------------------
2 files changed, 15 insertions(+), 31 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 80efdf2b7e5..b8735593805 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -603,7 +603,7 @@ bool simm5_p (rtx);
bool neg_simm5_p (rtx);
#ifdef RTX_CODE
bool has_vi_variant_p (rtx_code, rtx);
-void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
+void expand_vec_cmp (rtx, rtx_code, rtx, rtx, rtx = nullptr, rtx = nullptr);
bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
void expand_cond_len_unop (unsigned, rtx *);
void expand_cond_len_binop (unsigned, rtx *);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0cfbd21ce6f..14e75b9a117 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2752,7 +2752,8 @@ vectorize_related_mode (machine_mode vector_mode, scalar_mode element_mode,
/* Expand an RVV comparison. */
void
-expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1)
+expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
+ rtx maskoff)
{
machine_mode mask_mode = GET_MODE (target);
machine_mode data_mode = GET_MODE (op0);
@@ -2762,8 +2763,8 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1)
{
rtx lt = gen_reg_rtx (mask_mode);
rtx gt = gen_reg_rtx (mask_mode);
- expand_vec_cmp (lt, LT, op0, op1);
- expand_vec_cmp (gt, GT, op0, op1);
+ expand_vec_cmp (lt, LT, op0, op1, mask, maskoff);
+ expand_vec_cmp (gt, GT, op0, op1, mask, maskoff);
icode = code_for_pred (IOR, mask_mode);
rtx ops[] = {target, lt, gt};
emit_vlmax_insn (icode, BINARY_MASK_OP, ops);
@@ -2771,33 +2772,16 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1)
}
rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
- rtx ops[] = {target, cmp, op0, op1};
- emit_vlmax_insn (icode, COMPARE_OP, ops);
-}
-
-void
-expand_vec_cmp (rtx target, rtx_code code, rtx mask, rtx maskoff, rtx op0,
- rtx op1)
-{
- machine_mode mask_mode = GET_MODE (target);
- machine_mode data_mode = GET_MODE (op0);
- insn_code icode = get_cmp_insn_code (code, data_mode);
-
- if (code == LTGT)
+ if (!mask && !maskoff)
{
- rtx lt = gen_reg_rtx (mask_mode);
- rtx gt = gen_reg_rtx (mask_mode);
- expand_vec_cmp (lt, LT, mask, maskoff, op0, op1);
- expand_vec_cmp (gt, GT, mask, maskoff, op0, op1);
- icode = code_for_pred (IOR, mask_mode);
- rtx ops[] = {target, lt, gt};
- emit_vlmax_insn (icode, BINARY_MASK_OP, ops);
- return;
+ rtx ops[] = {target, cmp, op0, op1};
+ emit_vlmax_insn (icode, COMPARE_OP, ops);
+ }
+ else
+ {
+ rtx ops[] = {target, mask, maskoff, cmp, op0, op1};
+ emit_vlmax_insn (icode, COMPARE_OP_MU, ops);
}
-
- rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
- rtx ops[] = {target, mask, maskoff, cmp, op0, op1};
- emit_vlmax_insn (icode, COMPARE_OP_MU, ops);
}
/* Expand an RVV floating-point comparison:
@@ -2875,7 +2859,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1,
else
{
/* vmfeq.vv v0, vb, vb, v0.t */
- expand_vec_cmp (eq0, EQ, eq0, eq0, op1, op1);
+ expand_vec_cmp (eq0, EQ, op1, op1, eq0, eq0);
}
break;
default:
@@ -2893,7 +2877,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1,
if (code == ORDERED)
emit_move_insn (target, eq0);
else
- expand_vec_cmp (eq0, code, eq0, eq0, op0, op1);
+ expand_vec_cmp (eq0, code, op0, op1, eq0, eq0);
if (can_invert_p)
{
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
2024-03-01 6:27 [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of demin.han
2024-03-01 6:27 ` [PATCH 1/5] RISC-V: Remove float vector eqne pattern demin.han
2024-03-01 6:27 ` [PATCH 2/5] RISC-V: Refactor expand_vec_cmp demin.han
@ 2024-03-01 6:27 ` demin.han
2024-03-01 7:48 ` 钟居哲
2024-03-01 6:27 ` [PATCH 4/5] RISC-V: Remove integer vector eqne pattern demin.han
` (2 subsequent siblings)
5 siblings, 1 reply; 32+ messages in thread
From: demin.han @ 2024-03-01 6:27 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, jeffreyalaw
Currently, following instructions generated in autovector:
flw
vsetvli
vfmv.v.f
...
vmfxx.vv
Two issues:
1. Additional vsetvl and vfmv instructions
2. Occupy one vector register and may results in smaller lmul
We expect:
flw
...
vmfxx.vf
Tested on RV32 and RV64
gcc/ChangeLog:
* config/riscv/autovec.md: Accept imm
* config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern
(expand_vec_cmp): Ditto
* config/riscv/riscv.cc (riscv_const_insns): Exclude float mode
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Add new tests
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/riscv-v.cc | 23 +++++++++----
gcc/config/riscv/riscv.cc | 2 +-
.../riscv/rvv/autovec/cmp/vcond-1.c | 34 +++++++++++++++++++
4 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3b32369f68c..6cfb0800c45 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -690,7 +690,7 @@ (define_expand "vec_cmp<mode><vm>"
[(set (match_operand:<VM> 0 "register_operand")
(match_operator:<VM> 1 "comparison_operator"
[(match_operand:V_VLSF 2 "register_operand")
- (match_operand:V_VLSF 3 "register_operand")]))]
+ (match_operand:V_VLSF 3 "nonmemory_operand")]))]
"TARGET_VECTOR"
{
riscv_vector::expand_vec_cmp_float (operands[0], GET_CODE (operands[1]),
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 14e75b9a117..2a188ac78e0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2610,9 +2610,15 @@ expand_vec_init (rtx target, rtx vals)
/* Get insn code for corresponding comparison. */
static insn_code
-get_cmp_insn_code (rtx_code code, machine_mode mode)
+get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p)
{
insn_code icode;
+ if (FLOAT_MODE_P (mode))
+ {
+ icode = !scalar_p ? code_for_pred_cmp (mode)
+ : code_for_pred_cmp_scalar (mode);
+ return icode;
+ }
switch (code)
{
case EQ:
@@ -2628,10 +2634,7 @@ get_cmp_insn_code (rtx_code code, machine_mode mode)
case LTU:
case GE:
case GEU:
- if (FLOAT_MODE_P (mode))
- icode = code_for_pred_cmp (mode);
- else
- icode = code_for_pred_ltge (mode);
+ icode = code_for_pred_ltge (mode);
break;
default:
gcc_unreachable ();
@@ -2757,7 +2760,6 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
{
machine_mode mask_mode = GET_MODE (target);
machine_mode data_mode = GET_MODE (op0);
- insn_code icode = get_cmp_insn_code (code, data_mode);
if (code == LTGT)
{
@@ -2765,12 +2767,19 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
rtx gt = gen_reg_rtx (mask_mode);
expand_vec_cmp (lt, LT, op0, op1, mask, maskoff);
expand_vec_cmp (gt, GT, op0, op1, mask, maskoff);
- icode = code_for_pred (IOR, mask_mode);
+ insn_code icode = code_for_pred (IOR, mask_mode);
rtx ops[] = {target, lt, gt};
emit_vlmax_insn (icode, BINARY_MASK_OP, ops);
return;
}
+ rtx elt;
+ machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (op1));
+ bool scalar_p = const_vec_duplicate_p (op1, &elt) && FLOAT_MODE_P (data_mode);
+ if (scalar_p)
+ op1 = force_reg (scalar_mode, elt);
+ insn_code icode = get_cmp_insn_code (code, data_mode, scalar_p);
+
rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
if (!mask && !maskoff)
{
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4100abc9dd1..1ffe4865c19 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1760,7 +1760,7 @@ riscv_const_insns (rtx x)
register vec_duplicate into vmv.v.x. */
scalar_mode smode = GET_MODE_INNER (GET_MODE (x));
if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)
- && !immediate_operand (elt, Pmode))
+ && !FLOAT_MODE_P (smode) && !immediate_operand (elt, Pmode))
return 0;
/* Constants from -16 to 15 can be loaded with vmv.v.i.
The Wc0, Wc1 constraints are already covered by the
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
index 99a230d1c8a..7f6738518ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
@@ -141,6 +141,34 @@
TEST_VAR_ALL (DEF_VCOND_VAR)
TEST_IMM_ALL (DEF_VCOND_IMM)
+#define TEST_COND_IMM_FLOAT(T, COND, IMM, SUFFIX) \
+ T (float, float, COND, IMM, SUFFIX##_float_float) \
+ T (double, double, COND, IMM, SUFFIX##_double_double)
+
+#define TEST_IMM_FLOAT_ALL(T) \
+ TEST_COND_IMM_FLOAT (T, >, 0.0, _gt) \
+ TEST_COND_IMM_FLOAT (T, <, 0.0, _lt) \
+ TEST_COND_IMM_FLOAT (T, >=, 0.0, _ge) \
+ TEST_COND_IMM_FLOAT (T, <=, 0.0, _le) \
+ TEST_COND_IMM_FLOAT (T, ==, 0.0, _eq) \
+ TEST_COND_IMM_FLOAT (T, !=, 0.0, _ne) \
+ \
+ TEST_COND_IMM_FLOAT (T, >, 1.0, _gt1) \
+ TEST_COND_IMM_FLOAT (T, <, 1.0, _lt1) \
+ TEST_COND_IMM_FLOAT (T, >=, 1.0, _ge1) \
+ TEST_COND_IMM_FLOAT (T, <=, 1.0, _le1) \
+ TEST_COND_IMM_FLOAT (T, ==, 1.0, _eq1) \
+ TEST_COND_IMM_FLOAT (T, !=, 1.0, _ne1) \
+ \
+ TEST_COND_IMM_FLOAT (T, >, -1.0, _gt2) \
+ TEST_COND_IMM_FLOAT (T, <, -1.0, _lt2) \
+ TEST_COND_IMM_FLOAT (T, >=, -1.0, _ge2) \
+ TEST_COND_IMM_FLOAT (T, <=, -1.0, _le2) \
+ TEST_COND_IMM_FLOAT (T, ==, -1.0, _eq2) \
+ TEST_COND_IMM_FLOAT (T, !=, -1.0, _ne2)
+
+TEST_IMM_FLOAT_ALL (DEF_VCOND_IMM)
+
/* { dg-final { scan-assembler-times {\tvmseq\.vi} 42 } } */
/* { dg-final { scan-assembler-times {\tvmsne\.vi} 42 } } */
/* { dg-final { scan-assembler-times {\tvmsgt\.vi} 30 } } */
@@ -155,3 +183,9 @@ TEST_IMM_ALL (DEF_VCOND_IMM)
/* { dg-final { scan-assembler-times {\tvmslt} 38 } } */
/* { dg-final { scan-assembler-times {\tvmsge} 38 } } */
/* { dg-final { scan-assembler-times {\tvmsle} 82 } } */
+/* { dg-final { scan-assembler-times {\tvmfgt.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmflt.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfge.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfle.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfeq.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfne.vf} 6 } } */
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 4/5] RISC-V: Remove integer vector eqne pattern
2024-03-01 6:27 [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of demin.han
` (2 preceding siblings ...)
2024-03-01 6:27 ` [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm demin.han
@ 2024-03-01 6:27 ` demin.han
2024-03-01 7:37 ` 钟居哲
2024-03-01 6:27 ` [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm demin.han
2024-03-01 6:50 ` [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of Demin Han
5 siblings, 1 reply; 32+ messages in thread
From: demin.han @ 2024-03-01 6:27 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, jeffreyalaw
We can unify eqne and other comparison operations.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/predicates.md (comparison_except_eqge_operator): Only
exclue ge
(comparison_except_ge_operator): Ditto
* config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern
(expand_strcmp): Ditto
* config/riscv/riscv-vector-builtins-bases.cc: Remvoe eqne cond
* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove eqne
patterns
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_scalar): Ditto
(*pred_eqne<mode>_scalar_narrow): Ditto
(*pred_eqne<mode>_extended_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_extended_scalar): Ditto
(*pred_eqne<mode>_extended_scalar_narrow): Ditto
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
gcc/config/riscv/predicates.md | 4 +-
gcc/config/riscv/riscv-string.cc | 4 +-
.../riscv/riscv-vector-builtins-bases.cc | 3 -
gcc/config/riscv/vector.md | 279 +-----------------
4 files changed, 15 insertions(+), 275 deletions(-)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 6c87a7bd1f4..7f144551bb2 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -548,8 +548,8 @@ (define_predicate "ltge_operator"
(define_predicate "comparison_except_ltge_operator"
(match_code "eq,ne,le,leu,gt,gtu"))
-(define_predicate "comparison_except_eqge_operator"
- (match_code "le,leu,gt,gtu,lt,ltu"))
+(define_predicate "comparison_except_ge_operator"
+ (match_code "eq,ne,le,leu,gt,gtu,lt,ltu"))
(define_predicate "ge_operator"
(match_code "ge,geu"))
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index b09b51d7526..da33bd74ac6 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -1074,7 +1074,7 @@ expand_rawmemchr (machine_mode mode, rtx dst, rtx haystack, rtx needle,
/* Compare needle with haystack and store in a mask. */
rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle), vec);
rtx vmsops[] = {mask, eq, vec, needle};
- emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+ emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
riscv_vector::COMPARE_OP, vmsops, cnt);
/* Find the first bit in the mask. */
@@ -1200,7 +1200,7 @@ expand_strcmp (rtx result, rtx src1, rtx src2, rtx nbytes,
= gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, CONST0_RTX (mode)),
vec1);
rtx vmsops1[] = {mask0, eq0, vec1, CONST0_RTX (mode)};
- emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+ emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
riscv_vector::COMPARE_OP, vmsops1, cnt);
/* Look for vec1 != vec2 (includes vec2[i] == 0). */
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d414721ede8..0cef0b91758 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -718,9 +718,6 @@ public:
if (CODE == GE || CODE == GEU)
return e.use_compare_insn (CODE, code_for_pred_ge_scalar (
e.vector_mode ()));
- else if (CODE == EQ || CODE == NE)
- return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
- e.vector_mode ()));
else
return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
e.vector_mode ()));
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 9210d7c28ad..544ca4af938 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4671,7 +4671,7 @@ (define_expand "@pred_cmp<mode>_scalar"
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 4 "register_operand")
(vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 5 "register_operand"))])
@@ -4689,7 +4689,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "comparison_except_eqge_operator"
+ (match_operator:<VM> 2 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 3 "register_operand" " vr")
(vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 4 "register_operand" " r"))])
@@ -4714,7 +4714,7 @@ (define_insn "*pred_cmp<mode>_scalar"
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
@@ -4736,7 +4736,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(match_operand 8 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")
(vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
@@ -4747,92 +4747,6 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-(define_expand "@pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 6 "vector_length_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 5 "register_operand"))
- (match_operand:V_VLSI_QHS 4 "register_operand")])
- (match_operand:<VM> 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
- {})
-
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 4 "register_operand" " r"))
- (match_operand:V_VLSI_QHS 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR"
- "vms%B2.vx\t%0,%3,%4,v0.t"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))
- (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
- (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
;; we need to deal with SEW = 64 in RV32 system.
(define_expand "@pred_cmp<mode>_scalar"
@@ -4845,7 +4759,7 @@ (define_expand "@pred_cmp<mode>_scalar"
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand")
(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 5 "reg_or_int_operand"))])
@@ -4875,39 +4789,6 @@ (define_expand "@pred_cmp<mode>_scalar"
DONE;
})
-(define_expand "@pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 6 "vector_length_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 5 "reg_or_int_operand"))
- (match_operand:V_VLSI_D 4 "register_operand")])
- (match_operand:<VM> 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
-{
- enum rtx_code code = GET_CODE (operands[3]);
- if (riscv_vector::sew64_scalar_helper (
- operands,
- /* scalar op */&operands[5],
- /* vl */operands[6],
- <MODE>mode,
- riscv_vector::has_vi_variant_p (code, operands[5]),
- [] (rtx *operands, rtx boardcast_scalar) {
- emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
- operands[2], operands[3], operands[4], boardcast_scalar,
- operands[6], operands[7], operands[8]));
- },
- (riscv_vector::avl_type) INTVAL (operands[8])))
- DONE;
-})
-
(define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
[(set (match_operand:<VM> 0 "register_operand" "=vm")
(if_then_else:<VM>
@@ -4918,7 +4799,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "comparison_except_eqge_operator"
+ (match_operator:<VM> 2 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 3 "register_operand" " vr")
(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "register_operand" " r"))])
@@ -4932,30 +4813,6 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
(set (attr "avl_type_idx") (const_int 7))])
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 4 "register_operand" " r"))
- (match_operand:V_VLSI_D 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR"
- "vms%B2.vx\t%0,%3,%4,v0.t"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
@@ -4967,7 +4824,7 @@ (define_insn "*pred_cmp<mode>_scalar"
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
@@ -4989,7 +4846,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(match_operand 8 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
@@ -5000,50 +4857,6 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
(define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
[(set (match_operand:<VM> 0 "register_operand" "=vm")
(if_then_else:<VM>
@@ -5054,7 +4867,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "comparison_except_eqge_operator"
+ (match_operator:<VM> 2 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 3 "register_operand" " vr")
(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
@@ -5080,7 +4893,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar"
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
@@ -5102,7 +4915,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
(match_operand 8 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
@@ -5114,76 +4927,6 @@ (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-(define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (sign_extend:<VEL>
- (match_operand:<VSUBEL> 4 "register_operand" " r")))
- (match_operand:V_VLSI_D 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR && !TARGET_64BIT"
- "vms%B2.vx\t%0,%3,%4,v0.t"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_extended_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (sign_extend:<VEL>
- (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r")))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-(define_insn "*pred_eqne<mode>_extended_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (sign_extend:<VEL>
- (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
;; GE, vmsge.vx/vmsgeu.vx
;;
;; unmasked va >= x
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm
2024-03-01 6:27 [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of demin.han
` (3 preceding siblings ...)
2024-03-01 6:27 ` [PATCH 4/5] RISC-V: Remove integer vector eqne pattern demin.han
@ 2024-03-01 6:27 ` demin.han
2024-03-01 7:50 ` 钟居哲
2024-03-01 6:50 ` [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of Demin Han
5 siblings, 1 reply; 32+ messages in thread
From: demin.han @ 2024-03-01 6:27 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, jeffreyalaw
Similar to previous float change, vmsxx.vx is needed.
1. Only those which can't match vi should use vx.
2. DImode is processed by sew64_scalar_helper.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern
(expand_vec_cmp): Ditto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Update expect
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
gcc/config/riscv/riscv-v.cc | 33 ++++++++-----------
.../riscv/rvv/autovec/cmp/vcond-1.c | 14 ++++++--
2 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2a188ac78e0..9b601a4a8ff 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2619,26 +2619,18 @@ get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p)
: code_for_pred_cmp_scalar (mode);
return icode;
}
- switch (code)
+ if (scalar_p)
{
- case EQ:
- case NE:
- case LE:
- case LEU:
- case GT:
- case GTU:
- case LTGT:
- icode = code_for_pred_cmp (mode);
- break;
- case LT:
- case LTU:
- case GE:
- case GEU:
- icode = code_for_pred_ltge (mode);
- break;
- default:
- gcc_unreachable ();
+ if (code == GE || code == GEU)
+ icode = code_for_pred_ge_scalar (mode);
+ else
+ icode = code_for_pred_cmp_scalar (mode);
+ return icode;
}
+ if (code == LT || code == LTU || code == GE || code == GEU)
+ icode = code_for_pred_ltge (mode);
+ else
+ icode = code_for_pred_cmp (mode);
return icode;
}
@@ -2775,7 +2767,10 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
rtx elt;
machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (op1));
- bool scalar_p = const_vec_duplicate_p (op1, &elt) && FLOAT_MODE_P (data_mode);
+ bool scalar_p
+ = const_vec_duplicate_p (op1, &elt)
+ && (FLOAT_MODE_P (data_mode)
+ || (scalar_mode != DImode && !has_vi_variant_p (code, elt)));
if (scalar_p)
op1 = force_reg (scalar_mode, elt);
insn_code icode = get_cmp_insn_code (code, data_mode, scalar_p);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
index 7f6738518ee..e04c2a0cfbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
@@ -180,9 +180,19 @@ TEST_IMM_FLOAT_ALL (DEF_VCOND_IMM)
/* { dg-final { scan-assembler-times {\tvmseq} 78 } } */
/* { dg-final { scan-assembler-times {\tvmsne} 78 } } */
/* { dg-final { scan-assembler-times {\tvmsgt} 82 } } */
-/* { dg-final { scan-assembler-times {\tvmslt} 38 } } */
-/* { dg-final { scan-assembler-times {\tvmsge} 38 } } */
+/* { dg-final { scan-assembler-times {\tvmslt} 50 } } */
+/* { dg-final { scan-assembler-times {\tvmsge} 26 } } */
/* { dg-final { scan-assembler-times {\tvmsle} 82 } } */
+/* { dg-final { scan-assembler-times {\tvmseq\.vx} 16 } } */
+/* { dg-final { scan-assembler-times {\tvmsne\.vx} 16 } } */
+/* { dg-final { scan-assembler-times {\tvmsgt\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmsgtu\.vx} 14 } } */
+/* { dg-final { scan-assembler-times {\tvmslt\.vx} 24 } } */
+/* { dg-final { scan-assembler-times {\tvmsltu\.vx} 0 } } */
+/* { dg-final { scan-assembler-times {\tvmsge\.vx} 0 } } */
+/* { dg-final { scan-assembler-times {\tvmsgeu\.vx} 0 } } */
+/* { dg-final { scan-assembler-times {\tvmsle\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmsleu\.vx} 14 } } */
/* { dg-final { scan-assembler-times {\tvmfgt.vf} 6 } } */
/* { dg-final { scan-assembler-times {\tvmflt.vf} 6 } } */
/* { dg-final { scan-assembler-times {\tvmfge.vf} 6 } } */
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of
2024-03-01 6:27 [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of demin.han
` (4 preceding siblings ...)
2024-03-01 6:27 ` [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm demin.han
@ 2024-03-01 6:50 ` Demin Han
5 siblings, 0 replies; 32+ messages in thread
From: Demin Han @ 2024-03-01 6:50 UTC (permalink / raw)
To: gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li, jeffreyalaw
Sorry for the unexpected truncation.
Hi,
vf and vx are not supported well when comparing vector and
immediate in current autovec.
For example, following insts generated for float type:
flw
vsetvli
vfmv.v.f
...
vmfxx.vv
Two issues:
1. Additional vsetvl and vfmv instructions
2. Occupy one vector register and may results in smaller lmul
We expect:
flw
...
vmfxx.vf
For simplicity of supporting vx and vf, two refactors completed first.
1. remove eqne pattern; any special case or reason for eqne when first added?
2. refactor duplicate code.
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re:[PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-03-01 6:27 ` [PATCH 1/5] RISC-V: Remove float vector eqne pattern demin.han
@ 2024-03-01 7:23 ` 钟居哲
2024-03-01 8:12 ` Demin Han
2024-06-08 20:50 ` Jeff Law
1 sibling, 1 reply; 32+ messages in thread
From: 钟居哲 @ 2024-03-01 7:23 UTC (permalink / raw)
To: demin.han, gcc-patches; +Cc: kito.cheng, Li, Pan2, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 11187 bytes --]
Hello, han. Thanks for trying to optimize the codes.
But I believe those vector-scalar patterns (eq/ne) you remove in this patch are necessary.
This is the story:
1. For commutative RTL code in GCC like plus, eq, ne, ... etc,
we known in semantic Both (eq: (reg) (vec_duplicate ... ) and (eq: (vec_duplicate ... ) (reg)) are right.
However, GCC prefer this order as I remembered - (eq: (vec_duplicate ... ) (reg)).
2. Before this patch, the order of the comparison as follows (take eq and lt as an example):
1). (eq: (vec_duplicate ... ) (reg)) --> commutative
2). (lt: (reg) (vec_duplicate ... ) --> non-commutative
These patterns order are different.
So, you see we have dedicated patterns (seems duplicate patterns) for vector-scalar eq/ne, whereas, we unify eq/ne into other comparisons for vector-vector instructions.
If we unify eq/ne into other comparisons for vector-scalar instructions (like your patch does), we will end up have:
(eq: (reg) (vec_duplicate ... ) [after this patch] instead of (eq: (vec_duplicate ... ) (reg)) [Before this patch].
So, I think this patch may not be right.
I may be wrong, Robin/Jerff/kito feel free to correct me if I am wrong.
------------------ Original ------------------
From: "demin.han"<demin.han@starfivetech.com>;
Date: Fri, Mar 1, 2024 02:27 PM
To: "gcc-patches"<gcc-patches@gcc.gnu.org>;
Cc: "juzhe.zhong"<juzhe.zhong@rivai.ai>; "kito.cheng"<kito.cheng@gmail.com>; "Li, Pan2"<pan2.li@intel.com>; "jeffreyalaw"<jeffreyalaw@gmail.com>;
Subject: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
We can unify eqne and other comparison operations.
Tested on RV32 and RV64
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_scalar): Ditto
(*pred_eqne<mode>_scalar_narrow): Ditto
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
.../riscv/riscv-vector-builtins-bases.cc | 4 -
gcc/config/riscv/vector.md | 86 -------------------
2 files changed, 90 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b6f6e4ff37e..d414721ede8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1420,10 +1420,6 @@ public:
switch (e.op_info->op)
{
case OP_TYPE_vf: {
- if (CODE == EQ || CODE == NE)
- return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
- e.vector_mode ()));
- else
return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
e.vector_mode ()));
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index ab6e099852d..9210d7c28ad 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7520,92 +7520,6 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-(define_expand "@pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 6 "vector_length_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand"))
- (match_operand:V_VLSF 4 "register_operand")])
- (match_operand:<VM> 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
- {})
-
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 4 "register_operand" " f"))
- (match_operand:V_VLSF 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR"
- "vmf%B2.vf\t%0,%3,%4,v0.t"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))
- (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
- "vmf%B3.vf\t%0,%4,%5%p1"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
- (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
- "vmf%B3.vf\t%0,%4,%5%p1"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point merge
;; -------------------------------------------------------------------------------
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re:[PATCH 2/5] RISC-V: Refactor expand_vec_cmp
2024-03-01 6:27 ` [PATCH 2/5] RISC-V: Refactor expand_vec_cmp demin.han
@ 2024-03-01 7:32 ` 钟居哲
0 siblings, 0 replies; 32+ messages in thread
From: 钟居哲 @ 2024-03-01 7:32 UTC (permalink / raw)
To: demin.han, gcc-patches; +Cc: kito.cheng, Li, Pan2, jeffreyalaw
[-- Attachment #1: Type: text/plain, Size: 5956 bytes --]
LGTM. But please commit it with adding [NFC] into the title of this patch:
RISC-V: Refactor expand_vec_cmp [NFC]
------------------ Original ------------------
From: "demin.han"<demin.han@starfivetech.com>;
Date: Fri, Mar 1, 2024 02:27 PM
To: "gcc-patches"<gcc-patches@gcc.gnu.org>;
Cc: "juzhe.zhong"<juzhe.zhong@rivai.ai>; "kito.cheng"<kito.cheng@gmail.com>; "Li, Pan2"<pan2.li@intel.com>; "jeffreyalaw"<jeffreyalaw@gmail.com>;
Subject: [PATCH 2/5] RISC-V: Refactor expand_vec_cmp
There are two expand_vec_cmp functions.
They have same structure and similar code.
We can use default arguments instead of overloading.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
* config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
(expand_vec_cmp_float): Adapt arguments
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
gcc/config/riscv/riscv-protos.h | 2 +-
gcc/config/riscv/riscv-v.cc | 44 +++++++++++----------------------
2 files changed, 15 insertions(+), 31 deletions(-)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 80efdf2b7e5..b8735593805 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -603,7 +603,7 @@ bool simm5_p (rtx);
bool neg_simm5_p (rtx);
#ifdef RTX_CODE
bool has_vi_variant_p (rtx_code, rtx);
-void expand_vec_cmp (rtx, rtx_code, rtx, rtx);
+void expand_vec_cmp (rtx, rtx_code, rtx, rtx, rtx = nullptr, rtx = nullptr);
bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
void expand_cond_len_unop (unsigned, rtx *);
void expand_cond_len_binop (unsigned, rtx *);
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0cfbd21ce6f..14e75b9a117 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2752,7 +2752,8 @@ vectorize_related_mode (machine_mode vector_mode, scalar_mode element_mode,
/* Expand an RVV comparison. */
void
-expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1)
+expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
+ rtx maskoff)
{
machine_mode mask_mode = GET_MODE (target);
machine_mode data_mode = GET_MODE (op0);
@@ -2762,8 +2763,8 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1)
{
rtx lt = gen_reg_rtx (mask_mode);
rtx gt = gen_reg_rtx (mask_mode);
- expand_vec_cmp (lt, LT, op0, op1);
- expand_vec_cmp (gt, GT, op0, op1);
+ expand_vec_cmp (lt, LT, op0, op1, mask, maskoff);
+ expand_vec_cmp (gt, GT, op0, op1, mask, maskoff);
icode = code_for_pred (IOR, mask_mode);
rtx ops[] = {target, lt, gt};
emit_vlmax_insn (icode, BINARY_MASK_OP, ops);
@@ -2771,33 +2772,16 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1)
}
rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
- rtx ops[] = {target, cmp, op0, op1};
- emit_vlmax_insn (icode, COMPARE_OP, ops);
-}
-
-void
-expand_vec_cmp (rtx target, rtx_code code, rtx mask, rtx maskoff, rtx op0,
- rtx op1)
-{
- machine_mode mask_mode = GET_MODE (target);
- machine_mode data_mode = GET_MODE (op0);
- insn_code icode = get_cmp_insn_code (code, data_mode);
-
- if (code == LTGT)
+ if (!mask && !maskoff)
{
- rtx lt = gen_reg_rtx (mask_mode);
- rtx gt = gen_reg_rtx (mask_mode);
- expand_vec_cmp (lt, LT, mask, maskoff, op0, op1);
- expand_vec_cmp (gt, GT, mask, maskoff, op0, op1);
- icode = code_for_pred (IOR, mask_mode);
- rtx ops[] = {target, lt, gt};
- emit_vlmax_insn (icode, BINARY_MASK_OP, ops);
- return;
+ rtx ops[] = {target, cmp, op0, op1};
+ emit_vlmax_insn (icode, COMPARE_OP, ops);
+ }
+ else
+ {
+ rtx ops[] = {target, mask, maskoff, cmp, op0, op1};
+ emit_vlmax_insn (icode, COMPARE_OP_MU, ops);
}
-
- rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
- rtx ops[] = {target, mask, maskoff, cmp, op0, op1};
- emit_vlmax_insn (icode, COMPARE_OP_MU, ops);
}
/* Expand an RVV floating-point comparison:
@@ -2875,7 +2859,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1,
else
{
/* vmfeq.vv v0, vb, vb, v0.t */
- expand_vec_cmp (eq0, EQ, eq0, eq0, op1, op1);
+ expand_vec_cmp (eq0, EQ, op1, op1, eq0, eq0);
}
break;
default:
@@ -2893,7 +2877,7 @@ expand_vec_cmp_float (rtx target, rtx_code code, rtx op0, rtx op1,
if (code == ORDERED)
emit_move_insn (target, eq0);
else
- expand_vec_cmp (eq0, code, eq0, eq0, op0, op1);
+ expand_vec_cmp (eq0, code, op0, op1, eq0, eq0);
if (can_invert_p)
{
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re:[PATCH 4/5] RISC-V: Remove integer vector eqne pattern
2024-03-01 6:27 ` [PATCH 4/5] RISC-V: Remove integer vector eqne pattern demin.han
@ 2024-03-01 7:37 ` 钟居哲
0 siblings, 0 replies; 32+ messages in thread
From: 钟居哲 @ 2024-03-01 7:37 UTC (permalink / raw)
To: demin.han, gcc-patches; +Cc: kito.cheng, Li, Pan2, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 38761 bytes --]
Hi, han. My review comment of this patch is same as I said in:
[PATCH 1/5] RISC-V: Remove float vector eqne pattern
------------------ Original ------------------
From: "demin.han"<demin.han@starfivetech.com>;
Date: Fri, Mar 1, 2024 02:27 PM
To: "gcc-patches"<gcc-patches@gcc.gnu.org>;
Cc: "juzhe.zhong"<juzhe.zhong@rivai.ai>; "kito.cheng"<kito.cheng@gmail.com>; "Li, Pan2"<pan2.li@intel.com>; "jeffreyalaw"<jeffreyalaw@gmail.com>;
Subject: [PATCH 4/5] RISC-V: Remove integer vector eqne pattern
We can unify eqne and other comparison operations.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/predicates.md (comparison_except_eqge_operator): Only
exclue ge
(comparison_except_ge_operator): Ditto
* config/riscv/riscv-string.cc (expand_rawmemchr): Use cmp pattern
(expand_strcmp): Ditto
* config/riscv/riscv-vector-builtins-bases.cc: Remvoe eqne cond
* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove eqne
patterns
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_scalar): Ditto
(*pred_eqne<mode>_scalar_narrow): Ditto
(*pred_eqne<mode>_extended_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_extended_scalar): Ditto
(*pred_eqne<mode>_extended_scalar_narrow): Ditto
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
gcc/config/riscv/predicates.md | 4 +-
gcc/config/riscv/riscv-string.cc | 4 +-
.../riscv/riscv-vector-builtins-bases.cc | 3 -
gcc/config/riscv/vector.md | 279 +-----------------
4 files changed, 15 insertions(+), 275 deletions(-)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 6c87a7bd1f4..7f144551bb2 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -548,8 +548,8 @@ (define_predicate "ltge_operator"
(define_predicate "comparison_except_ltge_operator"
(match_code "eq,ne,le,leu,gt,gtu"))
-(define_predicate "comparison_except_eqge_operator"
- (match_code "le,leu,gt,gtu,lt,ltu"))
+(define_predicate "comparison_except_ge_operator"
+ (match_code "eq,ne,le,leu,gt,gtu,lt,ltu"))
(define_predicate "ge_operator"
(match_code "ge,geu"))
diff --git a/gcc/config/riscv/riscv-string.cc b/gcc/config/riscv/riscv-string.cc
index b09b51d7526..da33bd74ac6 100644
--- a/gcc/config/riscv/riscv-string.cc
+++ b/gcc/config/riscv/riscv-string.cc
@@ -1074,7 +1074,7 @@ expand_rawmemchr (machine_mode mode, rtx dst, rtx haystack, rtx needle,
/* Compare needle with haystack and store in a mask. */
rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle), vec);
rtx vmsops[] = {mask, eq, vec, needle};
- emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+ emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
riscv_vector::COMPARE_OP, vmsops, cnt);
/* Find the first bit in the mask. */
@@ -1200,7 +1200,7 @@ expand_strcmp (rtx result, rtx src1, rtx src2, rtx nbytes,
= gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, CONST0_RTX (mode)),
vec1);
rtx vmsops1[] = {mask0, eq0, vec1, CONST0_RTX (mode)};
- emit_nonvlmax_insn (code_for_pred_eqne_scalar (vmode),
+ emit_nonvlmax_insn (code_for_pred_cmp_scalar (vmode),
riscv_vector::COMPARE_OP, vmsops1, cnt);
/* Look for vec1 != vec2 (includes vec2[i] == 0). */
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index d414721ede8..0cef0b91758 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -718,9 +718,6 @@ public:
if (CODE == GE || CODE == GEU)
return e.use_compare_insn (CODE, code_for_pred_ge_scalar (
e.vector_mode ()));
- else if (CODE == EQ || CODE == NE)
- return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
- e.vector_mode ()));
else
return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
e.vector_mode ()));
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 9210d7c28ad..544ca4af938 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -4671,7 +4671,7 @@ (define_expand "@pred_cmp<mode>_scalar"
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 4 "register_operand")
(vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 5 "register_operand"))])
@@ -4689,7 +4689,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "comparison_except_eqge_operator"
+ (match_operator:<VM> 2 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 3 "register_operand" " vr")
(vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 4 "register_operand" " r"))])
@@ -4714,7 +4714,7 @@ (define_insn "*pred_cmp<mode>_scalar"
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
@@ -4736,7 +4736,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(match_operand 8 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")
(vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
@@ -4747,92 +4747,6 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-(define_expand "@pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 6 "vector_length_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 5 "register_operand"))
- (match_operand:V_VLSI_QHS 4 "register_operand")])
- (match_operand:<VM> 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
- {})
-
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 4 "register_operand" " r"))
- (match_operand:V_VLSI_QHS 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR"
- "vms%B2.vx\t%0,%3,%4,v0.t"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))
- (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_QHS
- (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
- (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
;; we need to deal with SEW = 64 in RV32 system.
(define_expand "@pred_cmp<mode>_scalar"
@@ -4845,7 +4759,7 @@ (define_expand "@pred_cmp<mode>_scalar"
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand")
(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 5 "reg_or_int_operand"))])
@@ -4875,39 +4789,6 @@ (define_expand "@pred_cmp<mode>_scalar"
DONE;
})
-(define_expand "@pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 6 "vector_length_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 5 "reg_or_int_operand"))
- (match_operand:V_VLSI_D 4 "register_operand")])
- (match_operand:<VM> 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
-{
- enum rtx_code code = GET_CODE (operands[3]);
- if (riscv_vector::sew64_scalar_helper (
- operands,
- /* scalar op */&operands[5],
- /* vl */operands[6],
- <MODE>mode,
- riscv_vector::has_vi_variant_p (code, operands[5]),
- [] (rtx *operands, rtx boardcast_scalar) {
- emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
- operands[2], operands[3], operands[4], boardcast_scalar,
- operands[6], operands[7], operands[8]));
- },
- (riscv_vector::avl_type) INTVAL (operands[8])))
- DONE;
-})
-
(define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
[(set (match_operand:<VM> 0 "register_operand" "=vm")
(if_then_else:<VM>
@@ -4918,7 +4799,7 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "comparison_except_eqge_operator"
+ (match_operator:<VM> 2 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 3 "register_operand" " vr")
(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "register_operand" " r"))])
@@ -4932,30 +4813,6 @@ (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
(set (attr "avl_type_idx") (const_int 7))])
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 4 "register_operand" " r"))
- (match_operand:V_VLSI_D 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR"
- "vms%B2.vx\t%0,%3,%4,v0.t"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
;; We don't use early-clobber for LMUL <= 1 to get better codegen.
(define_insn "*pred_cmp<mode>_scalar"
[(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
@@ -4967,7 +4824,7 @@ (define_insn "*pred_cmp<mode>_scalar"
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
@@ -4989,7 +4846,7 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(match_operand 8 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
(vec_duplicate:V_VLSI_D
(match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
@@ -5000,50 +4857,6 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
(define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
[(set (match_operand:<VM> 0 "register_operand" "=vm")
(if_then_else:<VM>
@@ -5054,7 +4867,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
(match_operand 7 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "comparison_except_eqge_operator"
+ (match_operator:<VM> 2 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 3 "register_operand" " vr")
(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
@@ -5080,7 +4893,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar"
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
@@ -5102,7 +4915,7 @@ (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
(match_operand 8 "const_int_operand" " i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "comparison_except_eqge_operator"
+ (match_operator:<VM> 3 "comparison_except_ge_operator"
[(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
(vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
@@ -5114,76 +4927,6 @@ (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-(define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (sign_extend:<VEL>
- (match_operand:<VSUBEL> 4 "register_operand" " r")))
- (match_operand:V_VLSI_D 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR && !TARGET_64BIT"
- "vms%B2.vx\t%0,%3,%4,v0.t"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_extended_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (sign_extend:<VEL>
- (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r")))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-(define_insn "*pred_eqne<mode>_extended_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSI_D
- (sign_extend:<VEL>
- (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))
- (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
- "vms%B3.vx\t%0,%4,%5%p1"
- [(set_attr "type" "vicmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
;; GE, vmsge.vx/vmsgeu.vx
;;
;; unmasked va >= x
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
2024-03-01 6:27 ` [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm demin.han
@ 2024-03-01 7:48 ` 钟居哲
2024-03-01 8:26 ` Demin Han
2024-03-05 8:40 ` Demin Han
0 siblings, 2 replies; 32+ messages in thread
From: 钟居哲 @ 2024-03-01 7:48 UTC (permalink / raw)
To: demin.han, gcc-patches
Cc: kito.cheng, Li, Pan2, jeffreyalaw, Robin Dapp, richard.sandiford
[-- Attachment #1: Type: text/plain, Size: 9916 bytes --]
Hi, han. I understand you are trying to support optimize vector-splat_vector into vector-scalar in "expand" stage, that is,
vv -> vx or vv -> vf.
It's a known issue that we know for a long time.
This patch is trying to transform vv->vf when the splat vector is duplicate from a constant (by recognize it is a CONST_VECTOR in expand stage),
but can't transform vv->vf when splat vector is duplicate from a register.
For example, like a[i] = b[i] > x ? c[i] : d[i], the x is a register, this case can not be optimized with your patch.
Actually, we have a solution to do all possible transformation (including the case I mentioned above) from vv to vx or vf by late-combine PASS which
is contributed by ARM Richard Sandiford: https://patchwork.ozlabs.org/project/gcc/patch/mptr0ljn9eh.fsf@arm.com/
You can try to apply this patch and experiment it locally yourself.
And I believe it will be landed in GCC-15. So I don't think we need this patch to do the optimization.
Thanks.
------------------ Original ------------------
From: "demin.han"<demin.han@starfivetech.com>;
Date: Fri, Mar 1, 2024 02:27 PM
To: "gcc-patches"<gcc-patches@gcc.gnu.org>;
Cc: "juzhe.zhong"<juzhe.zhong@rivai.ai>; "kito.cheng"<kito.cheng@gmail.com>; "Li, Pan2"<pan2.li@intel.com>; "jeffreyalaw"<jeffreyalaw@gmail.com>;
Subject: [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
Currently, following instructions generated in autovector:
flw
vsetvli
vfmv.v.f
...
vmfxx.vv
Two issues:
1. Additional vsetvl and vfmv instructions
2. Occupy one vector register and may results in smaller lmul
We expect:
flw
...
vmfxx.vf
Tested on RV32 and RV64
gcc/ChangeLog:
* config/riscv/autovec.md: Accept imm
* config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern
(expand_vec_cmp): Ditto
* config/riscv/riscv.cc (riscv_const_insns): Exclude float mode
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Add new tests
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/riscv-v.cc | 23 +++++++++----
gcc/config/riscv/riscv.cc | 2 +-
.../riscv/rvv/autovec/cmp/vcond-1.c | 34 +++++++++++++++++++
4 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3b32369f68c..6cfb0800c45 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -690,7 +690,7 @@ (define_expand "vec_cmp<mode><vm>"
[(set (match_operand:<VM> 0 "register_operand")
(match_operator:<VM> 1 "comparison_operator"
[(match_operand:V_VLSF 2 "register_operand")
- (match_operand:V_VLSF 3 "register_operand")]))]
+ (match_operand:V_VLSF 3 "nonmemory_operand")]))]
"TARGET_VECTOR"
{
riscv_vector::expand_vec_cmp_float (operands[0], GET_CODE (operands[1]),
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 14e75b9a117..2a188ac78e0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2610,9 +2610,15 @@ expand_vec_init (rtx target, rtx vals)
/* Get insn code for corresponding comparison. */
static insn_code
-get_cmp_insn_code (rtx_code code, machine_mode mode)
+get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p)
{
insn_code icode;
+ if (FLOAT_MODE_P (mode))
+ {
+ icode = !scalar_p ? code_for_pred_cmp (mode)
+ : code_for_pred_cmp_scalar (mode);
+ return icode;
+ }
switch (code)
{
case EQ:
@@ -2628,10 +2634,7 @@ get_cmp_insn_code (rtx_code code, machine_mode mode)
case LTU:
case GE:
case GEU:
- if (FLOAT_MODE_P (mode))
- icode = code_for_pred_cmp (mode);
- else
- icode = code_for_pred_ltge (mode);
+ icode = code_for_pred_ltge (mode);
break;
default:
gcc_unreachable ();
@@ -2757,7 +2760,6 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
{
machine_mode mask_mode = GET_MODE (target);
machine_mode data_mode = GET_MODE (op0);
- insn_code icode = get_cmp_insn_code (code, data_mode);
if (code == LTGT)
{
@@ -2765,12 +2767,19 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
rtx gt = gen_reg_rtx (mask_mode);
expand_vec_cmp (lt, LT, op0, op1, mask, maskoff);
expand_vec_cmp (gt, GT, op0, op1, mask, maskoff);
- icode = code_for_pred (IOR, mask_mode);
+ insn_code icode = code_for_pred (IOR, mask_mode);
rtx ops[] = {target, lt, gt};
emit_vlmax_insn (icode, BINARY_MASK_OP, ops);
return;
}
+ rtx elt;
+ machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (op1));
+ bool scalar_p = const_vec_duplicate_p (op1, &elt) && FLOAT_MODE_P (data_mode);
+ if (scalar_p)
+ op1 = force_reg (scalar_mode, elt);
+ insn_code icode = get_cmp_insn_code (code, data_mode, scalar_p);
+
rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
if (!mask && !maskoff)
{
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4100abc9dd1..1ffe4865c19 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1760,7 +1760,7 @@ riscv_const_insns (rtx x)
register vec_duplicate into vmv.v.x. */
scalar_mode smode = GET_MODE_INNER (GET_MODE (x));
if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)
- && !immediate_operand (elt, Pmode))
+ && !FLOAT_MODE_P (smode) && !immediate_operand (elt, Pmode))
return 0;
/* Constants from -16 to 15 can be loaded with vmv.v.i.
The Wc0, Wc1 constraints are already covered by the
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
index 99a230d1c8a..7f6738518ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
@@ -141,6 +141,34 @@
TEST_VAR_ALL (DEF_VCOND_VAR)
TEST_IMM_ALL (DEF_VCOND_IMM)
+#define TEST_COND_IMM_FLOAT(T, COND, IMM, SUFFIX) \
+ T (float, float, COND, IMM, SUFFIX##_float_float) \
+ T (double, double, COND, IMM, SUFFIX##_double_double)
+
+#define TEST_IMM_FLOAT_ALL(T) \
+ TEST_COND_IMM_FLOAT (T, >, 0.0, _gt) \
+ TEST_COND_IMM_FLOAT (T, <, 0.0, _lt) \
+ TEST_COND_IMM_FLOAT (T, >=, 0.0, _ge) \
+ TEST_COND_IMM_FLOAT (T, <=, 0.0, _le) \
+ TEST_COND_IMM_FLOAT (T, ==, 0.0, _eq) \
+ TEST_COND_IMM_FLOAT (T, !=, 0.0, _ne) \
+ \
+ TEST_COND_IMM_FLOAT (T, >, 1.0, _gt1) \
+ TEST_COND_IMM_FLOAT (T, <, 1.0, _lt1) \
+ TEST_COND_IMM_FLOAT (T, >=, 1.0, _ge1) \
+ TEST_COND_IMM_FLOAT (T, <=, 1.0, _le1) \
+ TEST_COND_IMM_FLOAT (T, ==, 1.0, _eq1) \
+ TEST_COND_IMM_FLOAT (T, !=, 1.0, _ne1) \
+ \
+ TEST_COND_IMM_FLOAT (T, >, -1.0, _gt2) \
+ TEST_COND_IMM_FLOAT (T, <, -1.0, _lt2) \
+ TEST_COND_IMM_FLOAT (T, >=, -1.0, _ge2) \
+ TEST_COND_IMM_FLOAT (T, <=, -1.0, _le2) \
+ TEST_COND_IMM_FLOAT (T, ==, -1.0, _eq2) \
+ TEST_COND_IMM_FLOAT (T, !=, -1.0, _ne2)
+
+TEST_IMM_FLOAT_ALL (DEF_VCOND_IMM)
+
/* { dg-final { scan-assembler-times {\tvmseq\.vi} 42 } } */
/* { dg-final { scan-assembler-times {\tvmsne\.vi} 42 } } */
/* { dg-final { scan-assembler-times {\tvmsgt\.vi} 30 } } */
@@ -155,3 +183,9 @@ TEST_IMM_ALL (DEF_VCOND_IMM)
/* { dg-final { scan-assembler-times {\tvmslt} 38 } } */
/* { dg-final { scan-assembler-times {\tvmsge} 38 } } */
/* { dg-final { scan-assembler-times {\tvmsle} 82 } } */
+/* { dg-final { scan-assembler-times {\tvmfgt.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmflt.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfge.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfle.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfeq.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfne.vf} 6 } } */
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re:[PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm
2024-03-01 6:27 ` [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm demin.han
@ 2024-03-01 7:50 ` 钟居哲
2024-03-01 12:07 ` [PATCH " Robin Dapp
0 siblings, 1 reply; 32+ messages in thread
From: 钟居哲 @ 2024-03-01 7:50 UTC (permalink / raw)
To: demin.han, gcc-patches; +Cc: kito.cheng, Li, Pan2, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 5439 bytes --]
Hi, han. My comment for this patch is same as
[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
------------------ Original ------------------
From: "demin.han"<demin.han@starfivetech.com>;
Date: Fri, Mar 1, 2024 02:27 PM
To: "gcc-patches"<gcc-patches@gcc.gnu.org>;
Cc: "juzhe.zhong"<juzhe.zhong@rivai.ai>; "kito.cheng"<kito.cheng@gmail.com>; "Li, Pan2"<pan2.li@intel.com>; "jeffreyalaw"<jeffreyalaw@gmail.com>;
Subject: [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm
Similar to previous float change, vmsxx.vx is needed.
1. Only those which can't match vi should use vx.
2. DImode is processed by sew64_scalar_helper.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern
(expand_vec_cmp): Ditto
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Update expect
Signed-off-by: demin.han <demin.han@starfivetech.com>
---
gcc/config/riscv/riscv-v.cc | 33 ++++++++-----------
.../riscv/rvv/autovec/cmp/vcond-1.c | 14 ++++++--
2 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 2a188ac78e0..9b601a4a8ff 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2619,26 +2619,18 @@ get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p)
: code_for_pred_cmp_scalar (mode);
return icode;
}
- switch (code)
+ if (scalar_p)
{
- case EQ:
- case NE:
- case LE:
- case LEU:
- case GT:
- case GTU:
- case LTGT:
- icode = code_for_pred_cmp (mode);
- break;
- case LT:
- case LTU:
- case GE:
- case GEU:
- icode = code_for_pred_ltge (mode);
- break;
- default:
- gcc_unreachable ();
+ if (code == GE || code == GEU)
+ icode = code_for_pred_ge_scalar (mode);
+ else
+ icode = code_for_pred_cmp_scalar (mode);
+ return icode;
}
+ if (code == LT || code == LTU || code == GE || code == GEU)
+ icode = code_for_pred_ltge (mode);
+ else
+ icode = code_for_pred_cmp (mode);
return icode;
}
@@ -2775,7 +2767,10 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
rtx elt;
machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (op1));
- bool scalar_p = const_vec_duplicate_p (op1, &elt) && FLOAT_MODE_P (data_mode);
+ bool scalar_p
+ = const_vec_duplicate_p (op1, &elt)
+ && (FLOAT_MODE_P (data_mode)
+ || (scalar_mode != DImode && !has_vi_variant_p (code, elt)));
if (scalar_p)
op1 = force_reg (scalar_mode, elt);
insn_code icode = get_cmp_insn_code (code, data_mode, scalar_p);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
index 7f6738518ee..e04c2a0cfbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
@@ -180,9 +180,19 @@ TEST_IMM_FLOAT_ALL (DEF_VCOND_IMM)
/* { dg-final { scan-assembler-times {\tvmseq} 78 } } */
/* { dg-final { scan-assembler-times {\tvmsne} 78 } } */
/* { dg-final { scan-assembler-times {\tvmsgt} 82 } } */
-/* { dg-final { scan-assembler-times {\tvmslt} 38 } } */
-/* { dg-final { scan-assembler-times {\tvmsge} 38 } } */
+/* { dg-final { scan-assembler-times {\tvmslt} 50 } } */
+/* { dg-final { scan-assembler-times {\tvmsge} 26 } } */
/* { dg-final { scan-assembler-times {\tvmsle} 82 } } */
+/* { dg-final { scan-assembler-times {\tvmseq\.vx} 16 } } */
+/* { dg-final { scan-assembler-times {\tvmsne\.vx} 16 } } */
+/* { dg-final { scan-assembler-times {\tvmsgt\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmsgtu\.vx} 14 } } */
+/* { dg-final { scan-assembler-times {\tvmslt\.vx} 24 } } */
+/* { dg-final { scan-assembler-times {\tvmsltu\.vx} 0 } } */
+/* { dg-final { scan-assembler-times {\tvmsge\.vx} 0 } } */
+/* { dg-final { scan-assembler-times {\tvmsgeu\.vx} 0 } } */
+/* { dg-final { scan-assembler-times {\tvmsle\.vx} 4 } } */
+/* { dg-final { scan-assembler-times {\tvmsleu\.vx} 14 } } */
/* { dg-final { scan-assembler-times {\tvmfgt.vf} 6 } } */
/* { dg-final { scan-assembler-times {\tvmflt.vf} 6 } } */
/* { dg-final { scan-assembler-times {\tvmfge.vf} 6 } } */
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: Re:[PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-03-01 7:23 ` 钟居哲
@ 2024-03-01 8:12 ` Demin Han
2024-03-01 14:53 ` [PATCH " Robin Dapp
2024-06-08 20:51 ` Jeff Law
0 siblings, 2 replies; 32+ messages in thread
From: Demin Han @ 2024-03-01 8:12 UTC (permalink / raw)
To: 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2, jeffreyalaw, Robin Dapp
[-- Attachment #1: Type: text/plain, Size: 8480 bytes --]
Hi juzhe,
I also thought it’s related to commutive firstly.
Following things make me to do the removal:
1. No tests fails in regression
2. When I write if (a == 2) and if (2 == a), the results are same
3. The vec_duplicate operand is the 5th operand in both cmp and eqne patterns. I think they are equal.
From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: 2024年3月1日 15:24
To: Demin Han <demin.han@starfivetech.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>
Subject: Re:[PATCH 1/5] RISC-V: Remove float vector eqne pattern
Hello, han. Thanks for trying to optimize the codes.
But I believe those vector-scalar patterns (eq/ne) you remove in this patch are necessary.
This is the story:
1. For commutative RTL code in GCC like plus, eq, ne, ... etc,
we known in semantic Both (eq: (reg) (vec_duplicate ... ) and (eq: (vec_duplicate ... ) (reg)) are right.
However, GCC prefer this order as I remembered - (eq: (vec_duplicate ... ) (reg)).
2. Before this patch, the order of the comparison as follows (take eq and lt as an example):
1). (eq: (vec_duplicate ... ) (reg)) --> commutative
2). (lt: (reg) (vec_duplicate ... ) --> non-commutative
These patterns order are different.
So, you see we have dedicated patterns (seems duplicate patterns) for vector-scalar eq/ne, whereas, we unify eq/ne into other comparisons for vector-vector instructions.
If we unify eq/ne into other comparisons for vector-scalar instructions (like your patch does), we will end up have:
(eq: (reg) (vec_duplicate ... ) [after this patch] instead of (eq: (vec_duplicate ... ) (reg)) [Before this patch].
So, I think this patch may not be right.
I may be wrong, Robin/Jerff/kito feel free to correct me if I am wrong.
------------------ Original ------------------
From: "demin.han"<demin.han@starfivetech.com<mailto:demin.han@starfivetech.com>>;
Date: Fri, Mar 1, 2024 02:27 PM
To: "gcc-patches"<gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>;
Cc: "juzhe.zhong"<juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>; "kito.cheng"<kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>; "Li, Pan2"<pan2.li@intel.com<mailto:pan2.li@intel.com>>; "jeffreyalaw"<jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>;
Subject: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
We can unify eqne and other comparison operations.
Tested on RV32 and RV64
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
* config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns
(*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
(*pred_eqne<mode>_scalar): Ditto
(*pred_eqne<mode>_scalar_narrow): Ditto
Signed-off-by: demin.han <demin.han@starfivetech.com<mailto:demin.han@starfivetech.com>>
---
.../riscv/riscv-vector-builtins-bases.cc | 4 -
gcc/config/riscv/vector.md | 86 -------------------
2 files changed, 90 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b6f6e4ff37e..d414721ede8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1420,10 +1420,6 @@ public:
switch (e.op_info->op)
{
case OP_TYPE_vf: {
- if (CODE == EQ || CODE == NE)
- return e.use_compare_insn (CODE, code_for_pred_eqne_scalar (
- e.vector_mode ()));
- else
return e.use_compare_insn (CODE, code_for_pred_cmp_scalar (
e.vector_mode ()));
}
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index ab6e099852d..9210d7c28ad 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7520,92 +7520,6 @@ (define_insn "*pred_cmp<mode>_scalar_narrow"
(set_attr "mode" "<MODE>")
(set_attr "spec_restriction" "none,thv,thv,none,none")])
-(define_expand "@pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand")
- (match_operand 6 "vector_length_operand")
- (match_operand 7 "const_int_operand")
- (match_operand 8 "const_int_operand")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand"))
- (match_operand:V_VLSF 4 "register_operand")])
- (match_operand:<VM> 2 "vector_merge_operand")))]
- "TARGET_VECTOR"
- {})
-
-(define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
- [(set (match_operand:<VM> 0 "register_operand" "=vm")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "register_operand" " 0")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 2 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 4 "register_operand" " f"))
- (match_operand:V_VLSF 3 "register_operand" " vr")])
- (match_dup 1)))]
- "TARGET_VECTOR"
- "vmf%B2.vf\t%0,%3,%4,v0.t"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "merge_op_idx" "1")
- (set_attr "vl_op_idx" "5")
- (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
- (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode>_scalar"
- [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))
- (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
- "vmf%B3.vf\t%0,%4,%5%p1"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL > dest LMUL.
-(define_insn "*pred_eqne<mode>_scalar_narrow"
- [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
- (if_then_else:<VM>
- (unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
- (match_operand 7 "const_int_operand" " i, i, i, i, i")
- (match_operand 8 "const_int_operand" " i, i, i, i, i")
- (reg:SI VL_REGNUM)
- (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (match_operator:<VM> 3 "equality_operator"
- [(vec_duplicate:V_VLSF
- (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
- (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")])
- (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
- "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
- "vmf%B3.vf\t%0,%4,%5%p1"
- [(set_attr "type" "vfcmp")
- (set_attr "mode" "<MODE>")
- (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point merge
;; -------------------------------------------------------------------------------
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
2024-03-01 7:48 ` 钟居哲
@ 2024-03-01 8:26 ` Demin Han
2024-03-05 8:40 ` Demin Han
1 sibling, 0 replies; 32+ messages in thread
From: Demin Han @ 2024-03-01 8:26 UTC (permalink / raw)
To: 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2, jeffreyalaw, Robin Dapp, richard.sandiford
[-- Attachment #1: Type: text/plain, Size: 8964 bytes --]
Hi juzhe,
Yes, for comparison between vector and scalar variable, this patch is not work, because the scalar is duplicated in loop vectorize pass.
I have not found idea for this situation, so solve vector-imm comparison first.
Thanks for remind this, I will try that patch.
Thanks.
From: 钟居哲 <juzhe.zhong@rivai.ai>
Sent: 2024年3月1日 15:49
To: Demin Han <demin.han@starfivetech.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>; richard.sandiford <richard.sandiford@arm.com>
Subject: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
Hi, han. I understand you are trying to support optimize vector-splat_vector into vector-scalar in "expand" stage, that is,
vv -> vx or vv -> vf.
It's a known issue that we know for a long time.
This patch is trying to transform vv->vf when the splat vector is duplicate from a constant (by recognize it is a CONST_VECTOR in expand stage),
but can't transform vv->vf when splat vector is duplicate from a register.
For example, like a[i] = b[i] > x ? c[i] : d[i], the x is a register, this case can not be optimized with your patch.
Actually, we have a solution to do all possible transformation (including the case I mentioned above) from vv to vx or vf by late-combine PASS which
is contributed by ARM Richard Sandiford: https://patchwork.ozlabs.org/project/gcc/patch/mptr0ljn9eh.fsf@arm.com/
You can try to apply this patch and experiment it locally yourself.
And I believe it will be landed in GCC-15. So I don't think we need this patch to do the optimization.
Thanks.
------------------ Original ------------------
From: "demin.han"<demin.han@starfivetech.com<mailto:demin.han@starfivetech.com>>;
Date: Fri, Mar 1, 2024 02:27 PM
To: "gcc-patches"<gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>;
Cc: "juzhe.zhong"<juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>; "kito.cheng"<kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>; "Li, Pan2"<pan2.li@intel.com<mailto:pan2.li@intel.com>>; "jeffreyalaw"<jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>;
Subject: [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
Currently, following instructions generated in autovector:
flw
vsetvli
vfmv.v.f
...
vmfxx.vv
Two issues:
1. Additional vsetvl and vfmv instructions
2. Occupy one vector register and may results in smaller lmul
We expect:
flw
...
vmfxx.vf
Tested on RV32 and RV64
gcc/ChangeLog:
* config/riscv/autovec.md: Accept imm
* config/riscv/riscv-v.cc (get_cmp_insn_code): Select scalar pattern
(expand_vec_cmp): Ditto
* config/riscv/riscv.cc (riscv_const_insns): Exclude float mode
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Add new tests
Signed-off-by: demin.han <demin.han@starfivetech.com<mailto:demin.han@starfivetech.com>>
---
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/riscv-v.cc | 23 +++++++++----
gcc/config/riscv/riscv.cc | 2 +-
.../riscv/rvv/autovec/cmp/vcond-1.c | 34 +++++++++++++++++++
4 files changed, 52 insertions(+), 9 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3b32369f68c..6cfb0800c45 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -690,7 +690,7 @@ (define_expand "vec_cmp<mode><vm>"
[(set (match_operand:<VM> 0 "register_operand")
(match_operator:<VM> 1 "comparison_operator"
[(match_operand:V_VLSF 2 "register_operand")
- (match_operand:V_VLSF 3 "register_operand")]))]
+ (match_operand:V_VLSF 3 "nonmemory_operand")]))]
"TARGET_VECTOR"
{
riscv_vector::expand_vec_cmp_float (operands[0], GET_CODE (operands[1]),
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 14e75b9a117..2a188ac78e0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2610,9 +2610,15 @@ expand_vec_init (rtx target, rtx vals)
/* Get insn code for corresponding comparison. */
static insn_code
-get_cmp_insn_code (rtx_code code, machine_mode mode)
+get_cmp_insn_code (rtx_code code, machine_mode mode, bool scalar_p)
{
insn_code icode;
+ if (FLOAT_MODE_P (mode))
+ {
+ icode = !scalar_p ? code_for_pred_cmp (mode)
+ : code_for_pred_cmp_scalar (mode);
+ return icode;
+ }
switch (code)
{
case EQ:
@@ -2628,10 +2634,7 @@ get_cmp_insn_code (rtx_code code, machine_mode mode)
case LTU:
case GE:
case GEU:
- if (FLOAT_MODE_P (mode))
- icode = code_for_pred_cmp (mode);
- else
- icode = code_for_pred_ltge (mode);
+ icode = code_for_pred_ltge (mode);
break;
default:
gcc_unreachable ();
@@ -2757,7 +2760,6 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
{
machine_mode mask_mode = GET_MODE (target);
machine_mode data_mode = GET_MODE (op0);
- insn_code icode = get_cmp_insn_code (code, data_mode);
if (code == LTGT)
{
@@ -2765,12 +2767,19 @@ expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1, rtx mask,
rtx gt = gen_reg_rtx (mask_mode);
expand_vec_cmp (lt, LT, op0, op1, mask, maskoff);
expand_vec_cmp (gt, GT, op0, op1, mask, maskoff);
- icode = code_for_pred (IOR, mask_mode);
+ insn_code icode = code_for_pred (IOR, mask_mode);
rtx ops[] = {target, lt, gt};
emit_vlmax_insn (icode, BINARY_MASK_OP, ops);
return;
}
+ rtx elt;
+ machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (op1));
+ bool scalar_p = const_vec_duplicate_p (op1, &elt) && FLOAT_MODE_P (data_mode);
+ if (scalar_p)
+ op1 = force_reg (scalar_mode, elt);
+ insn_code icode = get_cmp_insn_code (code, data_mode, scalar_p);
+
rtx cmp = gen_rtx_fmt_ee (code, mask_mode, op0, op1);
if (!mask && !maskoff)
{
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 4100abc9dd1..1ffe4865c19 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1760,7 +1760,7 @@ riscv_const_insns (rtx x)
register vec_duplicate into vmv.v.x. */
scalar_mode smode = GET_MODE_INNER (GET_MODE (x));
if (maybe_gt (GET_MODE_SIZE (smode), UNITS_PER_WORD)
- && !immediate_operand (elt, Pmode))
+ && !FLOAT_MODE_P (smode) && !immediate_operand (elt, Pmode))
return 0;
/* Constants from -16 to 15 can be loaded with vmv.v.i.
The Wc0, Wc1 constraints are already covered by the
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
index 99a230d1c8a..7f6738518ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cmp/vcond-1.c
@@ -141,6 +141,34 @@
TEST_VAR_ALL (DEF_VCOND_VAR)
TEST_IMM_ALL (DEF_VCOND_IMM)
+#define TEST_COND_IMM_FLOAT(T, COND, IMM, SUFFIX) \
+ T (float, float, COND, IMM, SUFFIX##_float_float) \
+ T (double, double, COND, IMM, SUFFIX##_double_double)
+
+#define TEST_IMM_FLOAT_ALL(T) \
+ TEST_COND_IMM_FLOAT (T, >, 0.0, _gt) \
+ TEST_COND_IMM_FLOAT (T, <, 0.0, _lt) \
+ TEST_COND_IMM_FLOAT (T, >=, 0.0, _ge) \
+ TEST_COND_IMM_FLOAT (T, <=, 0.0, _le) \
+ TEST_COND_IMM_FLOAT (T, ==, 0.0, _eq) \
+ TEST_COND_IMM_FLOAT (T, !=, 0.0, _ne) \
+ \
+ TEST_COND_IMM_FLOAT (T, >, 1.0, _gt1) \
+ TEST_COND_IMM_FLOAT (T, <, 1.0, _lt1) \
+ TEST_COND_IMM_FLOAT (T, >=, 1.0, _ge1) \
+ TEST_COND_IMM_FLOAT (T, <=, 1.0, _le1) \
+ TEST_COND_IMM_FLOAT (T, ==, 1.0, _eq1) \
+ TEST_COND_IMM_FLOAT (T, !=, 1.0, _ne1) \
+ \
+ TEST_COND_IMM_FLOAT (T, >, -1.0, _gt2) \
+ TEST_COND_IMM_FLOAT (T, <, -1.0, _lt2) \
+ TEST_COND_IMM_FLOAT (T, >=, -1.0, _ge2) \
+ TEST_COND_IMM_FLOAT (T, <=, -1.0, _le2) \
+ TEST_COND_IMM_FLOAT (T, ==, -1.0, _eq2) \
+ TEST_COND_IMM_FLOAT (T, !=, -1.0, _ne2)
+
+TEST_IMM_FLOAT_ALL (DEF_VCOND_IMM)
+
/* { dg-final { scan-assembler-times {\tvmseq\.vi} 42 } } */
/* { dg-final { scan-assembler-times {\tvmsne\.vi} 42 } } */
/* { dg-final { scan-assembler-times {\tvmsgt\.vi} 30 } } */
@@ -155,3 +183,9 @@ TEST_IMM_ALL (DEF_VCOND_IMM)
/* { dg-final { scan-assembler-times {\tvmslt} 38 } } */
/* { dg-final { scan-assembler-times {\tvmsge} 38 } } */
/* { dg-final { scan-assembler-times {\tvmsle} 82 } } */
+/* { dg-final { scan-assembler-times {\tvmfgt.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmflt.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfge.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfle.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfeq.vf} 6 } } */
+/* { dg-final { scan-assembler-times {\tvmfne.vf} 6 } } */
--
2.43.2
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm
2024-03-01 7:50 ` 钟居哲
@ 2024-03-01 12:07 ` Robin Dapp
2024-03-02 0:24 ` Andrew Waterman
0 siblings, 1 reply; 32+ messages in thread
From: Robin Dapp @ 2024-03-01 12:07 UTC (permalink / raw)
To: 钟居哲, demin.han, gcc-patches
Cc: rdapp.gcc, kito.cheng, Li, Pan2, jeffreyalaw
Hi Han,
in addition to what Juzhe mentioned (and that late-combine is going
to handle such cases) it should be noted that register pressure
should not be the only consideration here. Many uarchs have a higher
latency for register-file-crossing moves. At least without spilling
the vv variant is preferable, with spilling it very much depends.
Regards
Robin
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-03-01 8:12 ` Demin Han
@ 2024-03-01 14:53 ` Robin Dapp
2024-05-15 19:48 ` Robin Dapp
2024-06-08 20:51 ` Jeff Law
1 sibling, 1 reply; 32+ messages in thread
From: Robin Dapp @ 2024-03-01 14:53 UTC (permalink / raw)
To: Demin Han, 钟居哲, gcc-patches
Cc: rdapp.gcc, kito.cheng, Li, Pan2, jeffreyalaw
> 2. When I write if (a == 2) and if (2 == a), the results are
> same
>
> 3. The vec_duplicate operand is the 5th operand in both cmp and
> eqne patterns. I think they are equal.
A comparison with a constant is always canonicalized to have the
constant second, that's why you won't see a difference.
A vector constant follows the same rule because
swap_commutative_operands_p will place it second.
I'm not sure whether we need the vec_duplicate first, honestly.
I don't remember a canonicalization rule that puts it there.
We do have something for constants and vec_merge. As long as
things come from expand I think a constant will always be
second and this patch removes the patterns where the duplicate
is first.
Generally with fast math we could invert the condition so
a comparison should be "commutative". With NaNs I think we
also allow it if the unordered comparisons are supported.
But I'm not even certain that we try something like that with
vectors. On the other hand - as there is no canonical order
nothing would prevent it from being first in the future?
Will need to think about it some more (and try with NaNs) but
we could give try removing the patterns with GCC15 I suppose.
The rest should still be handled in a more generic fashion.
Regards
Robin
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm
2024-03-01 12:07 ` [PATCH " Robin Dapp
@ 2024-03-02 0:24 ` Andrew Waterman
0 siblings, 0 replies; 32+ messages in thread
From: Andrew Waterman @ 2024-03-02 0:24 UTC (permalink / raw)
To: Robin Dapp
Cc: 钟居哲,
demin.han, gcc-patches, kito.cheng, Li, Pan2, jeffreyalaw
On Fri, Mar 1, 2024 at 4:07 AM Robin Dapp <rdapp.gcc@gmail.com> wrote:
>
> Hi Han,
>
> in addition to what Juzhe mentioned (and that late-combine is going
> to handle such cases) it should be noted that register pressure
> should not be the only consideration here. Many uarchs have a higher
> latency for register-file-crossing moves. At least without spilling
> the vv variant is preferable, with spilling it very much depends.
And of course there are uarches for which this is not the case (e.g.
post-commit decoupled vector unit), in which case the .vx and .vf
versions are preferable to the .vv form regardless of vector register
pressure, because they reduce vector regfile access energy (especially
if a splat can be avoided). So it's a job for -mtune.
>
>
> Regards
> Robin
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
2024-03-01 7:48 ` 钟居哲
2024-03-01 8:26 ` Demin Han
@ 2024-03-05 8:40 ` Demin Han
2024-03-05 9:02 ` juzhe.zhong
1 sibling, 1 reply; 32+ messages in thread
From: Demin Han @ 2024-03-05 8:40 UTC (permalink / raw)
To: 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2, jeffreyalaw, Robin Dapp, richard.sandiford
[-- Attachment #1: Type: text/plain, Size: 599 bytes --]
Hi,
I applied the mentioned last_combine patch(https://patchwork.ozlabs.org/project/gcc/patch/mptbka7em9w.fsf@arm.com/).
And did some initial tests.
Found that:
1. Float vector-scalar and vector-imm are OK
2. Integer vector-scalar is OK
3. Integer vector-imm(e.g. a[i] > 16) is not OK.
When reaches last_combine pass, vec_duplicate(0x10) form is still kept, but no pattern match this now,
because all scalar patterns have “register_operand” predication.
I think MD file or expand function of rvv need to change for this situation.
Regards,
Demin
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: RE:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
2024-03-05 8:40 ` Demin Han
@ 2024-03-05 9:02 ` juzhe.zhong
2024-03-05 10:40 ` Demin Han
0 siblings, 1 reply; 32+ messages in thread
From: juzhe.zhong @ 2024-03-05 9:02 UTC (permalink / raw)
To: demin.han, gcc-patches
Cc: kito.cheng, pan2.li, jeffreyalaw, Robin Dapp, richard.sandiford
[-- Attachment #1: Type: text/plain, Size: 1186 bytes --]
Yes. I think we are lacking some combine patterns to do all vector-scalar combinations.
If you are interested at this topic, you can do some investigations on that (I believe currently no body works on it for now).
I bet we should add some patterns for late-combine PASS for example:
(set (plus : (vec_duplicate) (reg)))
juzhe.zhong@rivai.ai
From: Demin Han
Date: 2024-03-05 16:40
To: 钟居哲; gcc-patches
CC: kito.cheng; Li, Pan2; jeffreyalaw; Robin Dapp; richard.sandiford
Subject: RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
Hi,
I applied the mentioned last_combine patch(https://patchwork.ozlabs.org/project/gcc/patch/mptbka7em9w.fsf@arm.com/).
And did some initial tests.
Found that:
1. Float vector-scalar and vector-imm are OK
2. Integer vector-scalar is OK
3. Integer vector-imm(e.g. a[i] > 16) is not OK.
When reaches last_combine pass, vec_duplicate(0x10) form is still kept, but no pattern match this now,
because all scalar patterns have “register_operand” predication.
I think MD file or expand function of rvv need to change for this situation.
Regards,
Demin
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: RE:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
2024-03-05 9:02 ` juzhe.zhong
@ 2024-03-05 10:40 ` Demin Han
0 siblings, 0 replies; 32+ messages in thread
From: Demin Han @ 2024-03-05 10:40 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches
Cc: kito.cheng, pan2.li, jeffreyalaw, Robin Dapp, richard.sandiford
[-- Attachment #1: Type: text/plain, Size: 2058 bytes --]
OK, I will solve the comparison operation first and then do some check over other operations.
Regards,
Demin
From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: 2024年3月5日 17:02
To: Demin Han <demin.han@starfivetech.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; pan2.li <pan2.li@intel.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Robin Dapp <rdapp.gcc@gmail.com>; richard.sandiford <richard.sandiford@arm.com>
Subject: Re: RE:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
Yes. I think we are lacking some combine patterns to do all vector-scalar combinations.
If you are interested at this topic, you can do some investigations on that (I believe currently no body works on it for now).
I bet we should add some patterns for late-combine PASS for example:
(set (plus : (vec_duplicate) (reg)))
________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>
From: Demin Han<mailto:demin.han@starfivetech.com>
Date: 2024-03-05 16:40
To: 钟居哲<mailto:juzhe.zhong@rivai.ai>; gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: kito.cheng<mailto:kito.cheng@gmail.com>; Li, Pan2<mailto:pan2.li@intel.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; Robin Dapp<mailto:rdapp.gcc@gmail.com>; richard.sandiford<mailto:richard.sandiford@arm.com>
Subject: RE: Re:[PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm
Hi,
I applied the mentioned last_combine patch(https://patchwork.ozlabs.org/project/gcc/patch/mptbka7em9w.fsf@arm.com/).
And did some initial tests.
Found that:
1. Float vector-scalar and vector-imm are OK
2. Integer vector-scalar is OK
3. Integer vector-imm(e.g. a[i] > 16) is not OK.
When reaches last_combine pass, vec_duplicate(0x10) form is still kept, but no pattern match this now,
because all scalar patterns have “register_operand” predication.
I think MD file or expand function of rvv need to change for this situation.
Regards,
Demin
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-03-01 14:53 ` [PATCH " Robin Dapp
@ 2024-05-15 19:48 ` Robin Dapp
2024-05-16 1:54 ` Demin Han
0 siblings, 1 reply; 32+ messages in thread
From: Robin Dapp @ 2024-05-15 19:48 UTC (permalink / raw)
To: Demin Han, 钟居哲, gcc-patches
Cc: rdapp.gcc, kito.cheng, Li, Pan2, jeffreyalaw
Hi Demin,
are you still going to continue with this?
Regards
Robin
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-05-15 19:48 ` Robin Dapp
@ 2024-05-16 1:54 ` Demin Han
2024-05-16 19:21 ` Robin Dapp
0 siblings, 1 reply; 32+ messages in thread
From: Demin Han @ 2024-05-16 1:54 UTC (permalink / raw)
To: Robin Dapp, 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2, jeffreyalaw
Hi Robin,
Yes.
Can eqne pattern removal patches be committed firstly?
Regards,
Demin
> -----Original Message-----
> From: Robin Dapp <rdapp.gcc@gmail.com>
> Sent: 2024年5月16日 3:49
> To: Demin Han <demin.han@starfivetech.com>; 钟居哲
> <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
> Cc: rdapp.gcc@gmail.com; kito.cheng <kito.cheng@gmail.com>; Li, Pan2
> <pan2.li@intel.com>; jeffreyalaw <jeffreyalaw@gmail.com>
> Subject: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
>
> Hi Demin,
>
> are you still going to continue with this?
>
> Regards
> Robin
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-05-16 1:54 ` Demin Han
@ 2024-05-16 19:21 ` Robin Dapp
2024-06-08 20:48 ` Jeff Law
0 siblings, 1 reply; 32+ messages in thread
From: Robin Dapp @ 2024-05-16 19:21 UTC (permalink / raw)
To: Demin Han, 钟居哲, gcc-patches
Cc: rdapp.gcc, kito.cheng, Li, Pan2, jeffreyalaw
> Can eqne pattern removal patches be committed firstly?
Please first make sure you test with corner cases, NaNs in
particular. I'm pretty sure we don't have any test cases for
those.
Regards
Robin
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-05-16 19:21 ` Robin Dapp
@ 2024-06-08 20:48 ` Jeff Law
2024-06-10 7:33 ` Robin Dapp
0 siblings, 1 reply; 32+ messages in thread
From: Jeff Law @ 2024-06-08 20:48 UTC (permalink / raw)
To: Robin Dapp, Demin Han, 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2
On 5/16/24 1:21 PM, Robin Dapp wrote:
>> Can eqne pattern removal patches be committed firstly?
>
> Please first make sure you test with corner cases, NaNs in
> particular. I'm pretty sure we don't have any test cases for
> those.
But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0?
target = (a == b) ? x : y
target = (a != b) ? y : x
Are equivalent, even for IEEE IIRC.
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-03-01 6:27 ` [PATCH 1/5] RISC-V: Remove float vector eqne pattern demin.han
2024-03-01 7:23 ` 钟居哲
@ 2024-06-08 20:50 ` Jeff Law
1 sibling, 0 replies; 32+ messages in thread
From: Jeff Law @ 2024-06-08 20:50 UTC (permalink / raw)
To: demin.han, gcc-patches; +Cc: juzhe.zhong, kito.cheng, pan2.li
On 2/29/24 11:27 PM, demin.han wrote:
> We can unify eqne and other comparison operations.
>
> Tested on RV32 and RV64
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
> * config/riscv/vector.md (@pred_eqne<mode>_scalar): Remove patterns
> (*pred_eqne<mode>_scalar_merge_tie_mask): Ditto
> (*pred_eqne<mode>_scalar): Ditto
> (*pred_eqne<mode>_scalar_narrow): Ditto
So I'll tentatively ACK this for the trunk, assuming Robin doesn't
object before Tuesday's patchwork meeting.
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-03-01 8:12 ` Demin Han
2024-03-01 14:53 ` [PATCH " Robin Dapp
@ 2024-06-08 20:51 ` Jeff Law
1 sibling, 0 replies; 32+ messages in thread
From: Jeff Law @ 2024-06-08 20:51 UTC (permalink / raw)
To: Demin Han, 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2, Robin Dapp
On 3/1/24 1:12 AM, Demin Han wrote:
> Hi juzhe,
>
> I also thought it’s related to commutive firstly.
>
> Following things make me to do the removal:
>
> 1.No tests fails in regression
>
> 2.When I write if (a == 2) and if (2 == a), the results are same
GCC canonicalizes comparisons so that constants appear second.
Jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-06-08 20:48 ` Jeff Law
@ 2024-06-10 7:33 ` Robin Dapp
2024-06-10 13:49 ` Jeff Law
0 siblings, 1 reply; 32+ messages in thread
From: Robin Dapp @ 2024-06-10 7:33 UTC (permalink / raw)
To: Jeff Law, Demin Han, 钟居哲, gcc-patches
Cc: rdapp.gcc, kito.cheng, Li, Pan2
> But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0?
>
> target = (a == b) ? x : y
> target = (a != b) ? y : x
>
> Are equivalent, even for IEEE IIRC.
Yes, that should be fine. My concern was not that we do a
canonicalization but that we might not do it for some of the
vector cases. In particular when one of the operands is wrapped
in a vec_duplicate and we end up with it first rather than
second.
My general feeling is that the patch is good but I wasn't entirely
sure about all cases (in particular in case we transform something
after expand). That's why I would have liked to see at least some
small test cases for it along with the patch (for the combinations
we don't test yet).
Regards
Robin
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-06-10 7:33 ` Robin Dapp
@ 2024-06-10 13:49 ` Jeff Law
2024-06-10 14:52 ` Li, Pan2
2024-06-10 16:16 ` Demin Han
0 siblings, 2 replies; 32+ messages in thread
From: Jeff Law @ 2024-06-10 13:49 UTC (permalink / raw)
To: Robin Dapp, Demin Han, 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2
On 6/10/24 1:33 AM, Robin Dapp wrote:
>> But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0?
>>
>> target = (a == b) ? x : y
>> target = (a != b) ? y : x
>>
>> Are equivalent, even for IEEE IIRC.
>
> Yes, that should be fine. My concern was not that we do a
> canonicalization but that we might not do it for some of the
> vector cases. In particular when one of the operands is wrapped
> in a vec_duplicate and we end up with it first rather than
> second.
>
> My general feeling is that the patch is good but I wasn't entirely
> sure about all cases (in particular in case we transform something
> after expand). That's why I would have liked to see at least some
> small test cases for it along with the patch (for the combinations
> we don't test yet).
Ah, OK.
Demin, can you some additional test coverage, guided by Robin's concerns
above?
Thanks,
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* RE: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-06-10 13:49 ` Jeff Law
@ 2024-06-10 14:52 ` Li, Pan2
2024-06-10 16:30 ` Jeff Law
2024-06-10 16:16 ` Demin Han
1 sibling, 1 reply; 32+ messages in thread
From: Li, Pan2 @ 2024-06-10 14:52 UTC (permalink / raw)
To: Jeff Law, Robin Dapp, Demin Han, 钟居哲, gcc-patches
Cc: kito.cheng
Not sure if below float eq implement in sail-riscv is useful or not, but looks like some special handling for nan, as well as snan.
https://github.com/riscv/sail-riscv/blob/master/c_emulator/SoftFloat-3e/source/f32_eq.c
Pan
-----Original Message-----
From: Jeff Law <jeffreyalaw@gmail.com>
Sent: Monday, June 10, 2024 9:50 PM
To: Robin Dapp <rdapp.gcc@gmail.com>; Demin Han <demin.han@starfivetech.com>; 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Subject: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
On 6/10/24 1:33 AM, Robin Dapp wrote:
>> But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0?
>>
>> target = (a == b) ? x : y
>> target = (a != b) ? y : x
>>
>> Are equivalent, even for IEEE IIRC.
>
> Yes, that should be fine. My concern was not that we do a
> canonicalization but that we might not do it for some of the
> vector cases. In particular when one of the operands is wrapped
> in a vec_duplicate and we end up with it first rather than
> second.
>
> My general feeling is that the patch is good but I wasn't entirely
> sure about all cases (in particular in case we transform something
> after expand). That's why I would have liked to see at least some
> small test cases for it along with the patch (for the combinations
> we don't test yet).
Ah, OK.
Demin, can you some additional test coverage, guided by Robin's concerns
above?
Thanks,
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-06-10 13:49 ` Jeff Law
2024-06-10 14:52 ` Li, Pan2
@ 2024-06-10 16:16 ` Demin Han
2024-06-10 16:23 ` Jeff Law
1 sibling, 1 reply; 32+ messages in thread
From: Demin Han @ 2024-06-10 16:16 UTC (permalink / raw)
To: Jeff Law, Robin Dapp, 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2
[-- Attachment #1: Type: text/plain, Size: 1456 bytes --]
Hi，
I‘m on vacation rencently.
I will return in a few days and summit new patch with the test.
Regards，
Demin
________________________________
发件人: Jeff Law <jeffreyalaw@gmail.com>
发送时间: 星期一, 六月 10, 2024 9:49 下午
收件人: Robin Dapp <rdapp.gcc@gmail.com>; Demin Han <demin.han@starfivetech.com>; 钟居哲 <juzhe.zhong@rivai.ai>; gcc-patches <gcc-patches@gcc.gnu.org>
抄送: kito.cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>
主题: Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
On 6/10/24 1:33 AM, Robin Dapp wrote:
>> But isn't canonicalization of EQ/NE safe, even for IEEE NaN and +-0.0?
>>
>> target = (a == b) ? x : y
>> target = (a != b) ? y : x
>>
>> Are equivalent, even for IEEE IIRC.
>
> Yes, that should be fine. My concern was not that we do a
> canonicalization but that we might not do it for some of the
> vector cases. In particular when one of the operands is wrapped
> in a vec_duplicate and we end up with it first rather than
> second.
>
> My general feeling is that the patch is good but I wasn't entirely
> sure about all cases (in particular in case we transform something
> after expand). That's why I would have liked to see at least some
> small test cases for it along with the patch (for the combinations
> we don't test yet).
Ah, OK.
Demin, can you some additional test coverage, guided by Robin's concerns
above?
Thanks,
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-06-10 16:16 ` Demin Han
@ 2024-06-10 16:23 ` Jeff Law
0 siblings, 0 replies; 32+ messages in thread
From: Jeff Law @ 2024-06-10 16:23 UTC (permalink / raw)
To: Demin Han, Robin Dapp, 钟居哲, gcc-patches
Cc: kito.cheng, Li, Pan2
On 6/10/24 10:16 AM, Demin Han wrote:
> Hi，
>
> I‘m on vacation rencently.
> I will return in a few days and summit new patch with the test.
No problem. Enjoy your vacation, this can certainly wait until you return.
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 1/5] RISC-V: Remove float vector eqne pattern
2024-06-10 14:52 ` Li, Pan2
@ 2024-06-10 16:30 ` Jeff Law
0 siblings, 0 replies; 32+ messages in thread
From: Jeff Law @ 2024-06-10 16:30 UTC (permalink / raw)
To: Li, Pan2, Robin Dapp, Demin Han, 钟居哲, gcc-patches
Cc: kito.cheng
On 6/10/24 8:52 AM, Li, Pan2 wrote:
> Not sure if below float eq implement in sail-riscv is useful or not, but looks like some special handling for nan, as well as snan.
>
> https://github.com/riscv/sail-riscv/blob/master/c_emulator/SoftFloat-3e/source/f32_eq.c
Yes, but it's symmetrical, which is what we'd want to see.
jeff
^ permalink raw reply [flat|nested] 32+ messages in thread
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2024-03-01 6:27 [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of demin.han
2024-03-01 6:27 ` [PATCH 1/5] RISC-V: Remove float vector eqne pattern demin.han
2024-03-01 7:23 ` 钟居哲
2024-03-01 8:12 ` Demin Han
2024-03-01 14:53 ` [PATCH " Robin Dapp
2024-05-15 19:48 ` Robin Dapp
2024-05-16 1:54 ` Demin Han
2024-05-16 19:21 ` Robin Dapp
2024-06-08 20:48 ` Jeff Law
2024-06-10 7:33 ` Robin Dapp
2024-06-10 13:49 ` Jeff Law
2024-06-10 14:52 ` Li, Pan2
2024-06-10 16:30 ` Jeff Law
2024-06-10 16:16 ` Demin Han
2024-06-10 16:23 ` Jeff Law
2024-06-08 20:51 ` Jeff Law
2024-06-08 20:50 ` Jeff Law
2024-03-01 6:27 ` [PATCH 2/5] RISC-V: Refactor expand_vec_cmp demin.han
2024-03-01 7:32 ` 钟居哲
2024-03-01 6:27 ` [PATCH 3/5] RISC-V: Support vmfxx.vf for autovec comparison of vec and imm demin.han
2024-03-01 7:48 ` 钟居哲
2024-03-01 8:26 ` Demin Han
2024-03-05 8:40 ` Demin Han
2024-03-05 9:02 ` juzhe.zhong
2024-03-05 10:40 ` Demin Han
2024-03-01 6:27 ` [PATCH 4/5] RISC-V: Remove integer vector eqne pattern demin.han
2024-03-01 7:37 ` 钟居哲
2024-03-01 6:27 ` [PATCH 5/5] RISC-V: Support vmsxx.vx for autovec comparison of vec and imm demin.han
2024-03-01 7:50 ` 钟居哲
2024-03-01 12:07 ` [PATCH " Robin Dapp
2024-03-02 0:24 ` Andrew Waterman
2024-03-01 6:50 ` [PATCH 0/5] RISC-V: Support vf and vx for autovec comparison of Demin Han
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