target/8159: ARM/THUMB code uses sp as index register for automatic arrays

target/8159: ARM/THUMB code uses sp as index register for automatic arrays

[trauscher]

>Number:         8159
>Category:       target
>Synopsis:       ARM/THUMB code uses sp as index register for automatic arrays
>Confidential:   no
>Severity:       serious
>Priority:       low
>Responsible:    unassigned
>State:          open
>Class:          wrong-code
>Submitter-Id:   net
>Arrival-Date:   Mon Oct 07 08:06:00 PDT 2002
>Closed-Date:
>Last-Modified:
>Originator:     Thomas Rauscher
>Release:        3.2
>Organization:
LOYTEC electronics GmbH
>Environment:
System: Linux lexx 2.2.19 #3 Mon Nov 5 10:25:49 CET 2001 i686 unknown
Architecture: i686

	
host: i686-pc-linux-gnu
build: i686-pc-linux-gnu
target: arm-rtems-elf
configured with: ./configure --target=arm-rtems-elf --prefix=/usr/local --enable-languages=c,c++ --with-newlib
>Description:
        The compiler sometimes uses "sp" as index register for 
        loading/storing automatic arrays.
        Optimization must be enabled for the problem to appear.

>How-To-Repeat:

        Edit the following file (x.c)

int f(int n)
{
  int a[1];
  return a[n];
}

        Running the compiler yields:
        arm-rtems-elf-gcc -v -c -O1 -save-temps -mthumb x.c

Reading specs from /usr/local/lib/gcc-lib/arm-rtems-elf/3.2/specs
Configured with: /tmp/arm/gcc-3.2/configure --target=arm-rtems-elf --prefix=/usr/local --enable-languages=c,c++ --with-newlib
Thread model: single
gcc version 3.2
 /usr/local/lib/gcc-lib/arm-rtems-elf/3.2/cpp0 -lang-c -v -D__GNUC__=3 -D__GNUC_MINOR__=2 -D__GNUC_PATCHLEVEL__=0 -D__GXX_ABI_VERSION=102 -D__ELF__ -D__ELF__ -D__OPTIMIZE__ -D__STDC_HOSTED__=1 -Acpu=arm -Amachine=arm -D__ARM_ARCH_4T__ -D__APCS_32__ -D__ARMEL__ -D__THUMBEL__ -D__ELF__ -D__USES_INITFINI__ -D__thumb__ x.c x.i
GNU CPP version 3.2 (cpplib) (ARM/ELF)
ignoring nonexistent directory "/usr/local/arm-rtems-elf/sys-include"
#include "..." search starts here:
#include <...> search starts here:
 /usr/local/lib/gcc-lib/arm-rtems-elf/3.2/include
 /usr/local/arm-rtems-elf/include
End of search list.
 /usr/local/lib/gcc-lib/arm-rtems-elf/3.2/cc1 -fpreprocessed x.i -quiet -dumpbase x.c -mthumb -O1 -version -o x.s
GNU CPP version 3.2 (cpplib) (ARM/ELF)
GNU C version 3.2 (arm-rtems-elf)
        compiled by GNU C version 2.95.2 19991024 (release).
 /usr/local/lib/gcc-lib/arm-rtems-elf/3.2/../../../../arm-rtems-elf/bin/as -mno-fpu -o x.o x.s
x.s: Assembler messages:
x.s:12: Error: lo register required -- `ldr r0,[r0,sp]'

        The wrong assembly output is:

        .file   "x.c"
        .text
        .align  2
        .global f
        .thumb_func
        .type   f,function
f:
        sub     sp, sp, #4
        lsl     r0, r0, #2
        ldr     r0, [r0, sp]        !!!!! This instruction fails to assemble
        add     sp, sp, #4
        @ sp needed for prologue
        bx      lr
.Lfe1:
        .size   f,.Lfe1-f
        .ident  "GCC: (GNU) 3.2"

>Fix:

        None known.
>Release-Note:
>Audit-Trail:
>Unformatted:

Re: target/8159: ARM/THUMB code uses sp as index register for automatic arrays

[rearnsha]

Synopsis: ARM/THUMB code uses sp as index register for automatic arrays

State-Changed-From-To: open->closed
State-Changed-By: rearnsha
State-Changed-When: Fri Jan 31 15:25:26 2003
State-Changed-Why:
    The latest compiler generates 
    
            sub     sp, sp, #4
            lsl     r0, r0, #2
            mov     r3, sp
            ldr     r0, [r0, r3]
            add     sp, sp, #4
            bx      lr

http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=8159