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* Is Non-Blocking cache supported in GCC?
@ 2009-09-18  2:05 Amker.Cheng
  2009-09-18  4:49 ` Ian Lance Taylor
  0 siblings, 1 reply; 4+ messages in thread
From: Amker.Cheng @ 2009-09-18  2:05 UTC (permalink / raw)
  To: gcc

Hi all:
    Recently I found two relative old papers about non-blocking cache,
etc. which are :

        1) Reducing memory latency via non-blocking and prefetching
caches.  BY Tien-Fu Chen and Jean-Loup Baer.
        2) Data Prefetching:A Cost/Performance Analysis   BY Chris Metcalf

It seems the hardware facility does have the potential to improve the
performance with
compiler's assistance(especially instruction scheduling). while on the
other hand, lifting ahead
load instructions may resulting in increasing register pressure.

So I'm thinking :
1, Has anyone from gcc folks done any investigation on this topic yet,
or any statistic data based on gcc available?
2, Does GCC(in any release version) supports it in any targets(such as
mips 24ke) with this hardware feature?
    If not currently, does it possible to support it by using target
definition macros and functions?

Any tips will be highly appreciated, thanks.
-- 
Best Regards.

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Is Non-Blocking cache supported in GCC?
  2009-09-18  2:05 Is Non-Blocking cache supported in GCC? Amker.Cheng
@ 2009-09-18  4:49 ` Ian Lance Taylor
  2009-09-18 17:17   ` Janis Johnson
  0 siblings, 1 reply; 4+ messages in thread
From: Ian Lance Taylor @ 2009-09-18  4:49 UTC (permalink / raw)
  To: Amker.Cheng; +Cc: gcc

"Amker.Cheng" <amker.cheng@gmail.com> writes:

>     Recently I found two relative old papers about non-blocking cache,
> etc. which are :
>
>         1) Reducing memory latency via non-blocking and prefetching
> caches.  BY Tien-Fu Chen and Jean-Loup Baer.
>         2) Data Prefetching:A Cost/Performance Analysis   BY Chris Metcalf
>
> It seems the hardware facility does have the potential to improve the
> performance with
> compiler's assistance(especially instruction scheduling). while on the
> other hand, lifting ahead
> load instructions may resulting in increasing register pressure.
>
> So I'm thinking :
> 1, Has anyone from gcc folks done any investigation on this topic yet,
> or any statistic data based on gcc available?
> 2, Does GCC(in any release version) supports it in any targets(such as
> mips 24ke) with this hardware feature?
>     If not currently, does it possible to support it by using target
> definition macros and functions?

gcc is able to generate prefetches in loops, via the
-fprefetch-loop-arrays option.  There are various related parameters,
prefetch-latency, l1-cache-line-size, etc.  I don't know how well this
works.  To the extent that it does work, it is supported in the MIPS
backend, and should work on the MIPS 24ke.

Ian

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Is Non-Blocking cache supported in GCC?
  2009-09-18  4:49 ` Ian Lance Taylor
@ 2009-09-18 17:17   ` Janis Johnson
  2009-09-19  4:31     ` Amker.Cheng
  0 siblings, 1 reply; 4+ messages in thread
From: Janis Johnson @ 2009-09-18 17:17 UTC (permalink / raw)
  To: Ian Lance Taylor; +Cc: Amker.Cheng, gcc

On Thu, 2009-09-17 at 21:48 -0700, Ian Lance Taylor wrote:
> "Amker.Cheng" <amker.cheng@gmail.com> writes:
> 
> >     Recently I found two relative old papers about non-blocking cache,
> > etc. which are :
> >
> >         1) Reducing memory latency via non-blocking and prefetching
> > caches.  BY Tien-Fu Chen and Jean-Loup Baer.
> >         2) Data Prefetching:A Cost/Performance Analysis   BY Chris Metcalf
> >
> > It seems the hardware facility does have the potential to improve the
> > performance with
> > compiler's assistance(especially instruction scheduling). while on the
> > other hand, lifting ahead
> > load instructions may resulting in increasing register pressure.
> >
> > So I'm thinking :
> > 1, Has anyone from gcc folks done any investigation on this topic yet,
> > or any statistic data based on gcc available?
> > 2, Does GCC(in any release version) supports it in any targets(such as
> > mips 24ke) with this hardware feature?
> >     If not currently, does it possible to support it by using target
> > definition macros and functions?
> 
> gcc is able to generate prefetches in loops, via the
> -fprefetch-loop-arrays option.  There are various related parameters,
> prefetch-latency, l1-cache-line-size, etc.  I don't know how well this
> works.  To the extent that it does work, it is supported in the MIPS
> backend, and should work on the MIPS 24ke.

There's also a prefetch built-in function; see 

http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html#Other-Builtins

It's been in GCC since 3.1.

Janis

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: Is Non-Blocking cache supported in GCC?
  2009-09-18 17:17   ` Janis Johnson
@ 2009-09-19  4:31     ` Amker.Cheng
  0 siblings, 0 replies; 4+ messages in thread
From: Amker.Cheng @ 2009-09-19  4:31 UTC (permalink / raw)
  To: janis187; +Cc: Ian Lance Taylor, gcc

On Sat, Sep 19, 2009 at 1:17 AM, Janis Johnson <janis187@us.ibm.com> wrote:
> On Thu, 2009-09-17 at 21:48 -0700, Ian Lance Taylor wrote:
>
> There's also a prefetch built-in function; see
>
> http://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html#Other-Builtins
>
> It's been in GCC since 3.1.
>
> Janis
>
>
Thank you all, It seems prefetch is more useful than non-blocking, no wonder gcc
takes advantage of prefetch, rather than non-blocking.

-- 
Best Regards.

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2009-09-19  4:31 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-09-18  2:05 Is Non-Blocking cache supported in GCC? Amker.Cheng
2009-09-18  4:49 ` Ian Lance Taylor
2009-09-18 17:17   ` Janis Johnson
2009-09-19  4:31     ` Amker.Cheng

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