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From: Michael Frysinger <vapier@sourceware.org>
To: gdb-cvs@sourceware.org
Subject: [binutils-gdb] sim: riscv: add missing AC_MSG_RESULT call
Date: Mon,  7 Nov 2022 16:45:36 +0000 (GMT)	[thread overview]
Message-ID: <20221107164536.E54773858423@sourceware.org> (raw)

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=4faede6126762a9704da4c79093cca15c15efafa

commit 4faede6126762a9704da4c79093cca15c15efafa
Author: Mike Frysinger <vapier@gentoo.org>
Date:   Mon Nov 7 23:44:36 2022 +0700

    sim: riscv: add missing AC_MSG_RESULT call
    
    Previous commit in here forgot to include this.

Diff:
---
 sim/configure          | 2 ++
 sim/riscv/acinclude.m4 | 1 +
 2 files changed, 3 insertions(+)

diff --git a/sim/configure b/sim/configure
index e25d60c0d90..1916e1d37f6 100755
--- a/sim/configure
+++ b/sim/configure
@@ -16279,6 +16279,8 @@ case $target in #(
   *) :
      ;;
 esac
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $SIM_RISCV_BITSIZE" >&5
+$as_echo "$SIM_RISCV_BITSIZE" >&6; }
 
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether sim rx should be cycle accurate" >&5
diff --git a/sim/riscv/acinclude.m4 b/sim/riscv/acinclude.m4
index 29dcaebc61d..0a421f4d4d5 100644
--- a/sim/riscv/acinclude.m4
+++ b/sim/riscv/acinclude.m4
@@ -18,4 +18,5 @@ AC_MSG_CHECKING([riscv bitsize])
 SIM_RISCV_BITSIZE=64
 AS_CASE([$target],
 	[riscv32*], [SIM_RISCV_BITSIZE=32])
+AC_MSG_RESULT([$SIM_RISCV_BITSIZE])
 AC_SUBST(SIM_RISCV_BITSIZE)

                 reply	other threads:[~2022-11-07 16:45 UTC|newest]

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