From: <bhushan.attarde@imgtec.com>
To: <gdb-patches@sourceware.org>
Cc: <aburgess@redhat.com>, <vapier@gentoo.org>,
<Jaydeep.Patil@imgtec.com>,
Bhushan Attarde <bhushan.attarde@imgtec.com>
Subject: [PATCH 05/11] sim: riscv: Add single precision floating-point basic arithmetic instructions
Date: Mon, 26 Feb 2024 14:26:22 +0000 [thread overview]
Message-ID: <20240226142628.1629048-2-bhushan.attarde@imgtec.com> (raw)
In-Reply-To: <20240226142628.1629048-1-bhushan.attarde@imgtec.com>
From: Bhushan Attarde <bhushan.attarde@imgtec.com>
Added simulation of following single precision floating-point instructions
fadd.s, fsub.s, fmul.s, fdiv.s and fsqrt.s.
Updated test file sim/testsuite/riscv/s-basic-arith.s to test these
instructions.
---
sim/riscv/sim-main.c | 50 ++++++++++++++++++++++++++++
sim/testsuite/riscv/s-basic-arith.s | 51 +++++++++++++++++++++++++++++
2 files changed, 101 insertions(+)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index dd91431ad12..5d8ff9dc6ee 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -91,6 +91,11 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
#define FMSUB 8
#define FNMADD 9
#define FNMSUB 10
+#define FADD 11
+#define FSUB 12
+#define FMUL 13
+#define FDIV 14
+#define FSQRT 15
static INLINE void
store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
@@ -942,6 +947,31 @@ float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2,
TRACE_INSN (cpu, "fmin.s %s, %s, %s;", frd_name, frs1_name, frs2_name);
result = fminf (a, b);
break;
+ case FADD:
+ TRACE_INSN (cpu, "fadd.s %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, rm);
+ result = a + b;
+ break;
+ case FSUB:
+ TRACE_INSN (cpu, "fsub.s %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, rm);
+ result = a - b;
+ break;
+ case FMUL:
+ TRACE_INSN (cpu, "fmul.s %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, rm);
+ result = a * b;
+ break;
+ case FDIV:
+ TRACE_INSN (cpu, "fdiv.s %s, %s, %s, rm=%d;",
+ frd_name, frs1_name, frs2_name, rm);
+ result = a / b;
+ break;
+ case FSQRT:
+ TRACE_INSN (cpu, "fsqrt.s %s, %s, rm=%d;",
+ frd_name, frs1_name, rm);
+ result = sqrtf (a);
+ break;
}
if (rm == RMM)
@@ -1173,6 +1203,26 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case MATCH_FNMSUB_S | MASK_RM:
float32_math (cpu, rd, rs1, rs2, rs3, rm, FNMSUB);
break;
+ case MATCH_FADD_S:
+ case MATCH_FADD_S | MASK_RM:
+ float32_math (cpu, rd, rs1, rs2, rs3, rm, FADD);
+ break;
+ case MATCH_FSUB_S:
+ case MATCH_FSUB_S | MASK_RM:
+ float32_math (cpu, rd, rs1, rs2, rs3, rm, FSUB);
+ break;
+ case MATCH_FMUL_S:
+ case MATCH_FMUL_S | MASK_RM:
+ float32_math (cpu, rd, rs1, rs2, rs3, rm, FMUL);
+ break;
+ case MATCH_FDIV_S:
+ case MATCH_FDIV_S | MASK_RM:
+ float32_math (cpu, rd, rs1, rs2, rs3, rm, FDIV);
+ break;
+ case MATCH_FSQRT_S:
+ case MATCH_FSQRT_S | MASK_RM:
+ float32_math (cpu, rd, rs1, rs2, rs3, rm, FSQRT);
+ break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
diff --git a/sim/testsuite/riscv/s-basic-arith.s b/sim/testsuite/riscv/s-basic-arith.s
index a05a0d0a2c3..15d07f9e6cd 100644
--- a/sim/testsuite/riscv/s-basic-arith.s
+++ b/sim/testsuite/riscv/s-basic-arith.s
@@ -14,9 +14,16 @@
_arg1:
.float -12.5
+ .float 1.5
+ .float 2.2
+ .float 1.75
+ .float 5.0
_arg2:
.float 2.5
+ .float 0.5
+ .float 1.1
+ .float 0.1
_arg3:
.float 7.45
@@ -26,6 +33,11 @@ _result:
.float 38.7000008
.float -38.7000008
.float 23.7999992
+ .float 2.0
+ .float 1.1
+ .float 0.175
+ .float 17.5
+ .float 2.23606801
start
.option push
@@ -73,6 +85,45 @@ _result:
feq.s a5,fa4,fa4
bne a5,a4,test_fail
+ # Test fadd instruction.
+ flw fa0,4(a0)
+ flw fa1,4(a1)
+ flw fa2,16(a3)
+ fadd.s fa4,fa0,fa1,rne
+ feq.s a5,fa4,fa2
+ bne a5,a4,test_fail
+
+ # Test fsub instruction.
+ flw fa0,8(a0)
+ flw fa1,8(a1)
+ flw fa2,20(a3)
+ fsub.s fa4,fa0,fa1,rne
+ feq.s a5,fa4,fa2
+ bne a5,a4,test_fail
+
+ # Test fmul instruction.
+ flw fa0,12(a0)
+ flw fa1,12(a1)
+ flw fa2,24(a3)
+ fmul.s fa4,fa0,fa1,rne
+ feq.s a5,fa4,fa2
+ bne a5,a4,test_fail
+
+ # Test fdiv instruction.
+ flw fa0,12(a0) # Use same input values as of fmul
+ flw fa1,12(a1)
+ flw fa2,28(a3)
+ fdiv.s fa4,fa0,fa1,rne
+ feq.s a5,fa4,fa2
+ bne a5,a4,test_fail
+
+ # Test fsqrt instruction.
+ flw fa0,16(a0)
+ flw fa2,32(a3)
+ fsqrt.s fa4,fa0,rne
+ feq.s a5,fa4,fa2
+ bne a5,a4,test_fail
+
test_pass:
pass
--
2.25.1
next prev parent reply other threads:[~2024-02-26 14:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-26 14:26 [PATCH 04/11] sim: riscv: Add single precision floating-point MAC instructions bhushan.attarde
2024-02-26 14:26 ` bhushan.attarde [this message]
2024-02-26 14:26 ` [PATCH 06/11] sim: riscv: Add single-precision floating-point conversion instructions bhushan.attarde
2024-02-26 14:26 ` [PATCH 07/11] sim: riscv: Add double precision floating-point load-store, move, compare and classify instructions bhushan.attarde
2024-02-26 14:26 ` [PATCH 08/11] sim: riscv: Add double precision floating-point sign-injection, min and max instructions bhushan.attarde
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