[PATCH 04/11] sim: riscv: Add single precision floating-point MAC instructions

[PATCH 04/11] sim: riscv: Add single precision floating-point MAC instructions

[bhushan.attarde]

From: Bhushan Attarde <bhushan.attarde@imgtec.com>

Added simulation of following single precision floating-point instructions
fmadd.s, fnmadd.s, fmsub.s and fnmsub.s.

Added test file sim/testsuite/riscv/s-basic-arith.s to test these instructions.
---
 sim/riscv/sim-main.c                | 171 +++++++++++++++++++++++++++-
 sim/testsuite/riscv/s-basic-arith.s |  80 +++++++++++++
 2 files changed, 246 insertions(+), 5 deletions(-)
 create mode 100644 sim/testsuite/riscv/s-basic-arith.s

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 0e873895f76..dd91431ad12 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -25,6 +25,7 @@
 #include "defs.h"
 
 #include <math.h>
+#include <fenv.h>
 #include <inttypes.h>
 #include <time.h>
 
@@ -71,12 +72,25 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
 #define FCSR_DZ		0x8	/* Divide by zero.  */
 #define FCSR_NV		0x10	/* Invalid Operation.  */
 
+#define RNE	0x000
+#define RTZ	0x001
+#define RDN	0x002
+#define RUP	0x003
+#define RMM	0x004
+#define DYN	0x007
+
+#define MASK_RM (OP_MASK_RM << OP_SH_RM)
+
 #define FEQ	1
 #define FLT	2
 #define FLE	3
 #define FCLASS	4
 #define FMIN	5
 #define FMAX	6
+#define FMADD	7
+#define FMSUB	8
+#define FNMADD	9
+#define FNMSUB	10
 
 static INLINE void
 store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
@@ -721,6 +735,45 @@ mulhsu (int64_t a, uint64_t b)
   return negate ? ~res + (a * b == 0) : res;
 }
 
+/* Handle the rounding modes.  */
+static int
+set_riscv_rounding_mode (int rm)
+{
+  int old_rm = fegetround ();
+
+  /* Instruction does not set rm.  */
+  if (rm == -1)
+    return old_rm;
+
+  if (rm == RNE)
+    fesetround (FE_TONEAREST);
+  else if (rm == RTZ)
+    fesetround (FE_TOWARDZERO);
+  else if (rm == RDN)
+    fesetround (FE_DOWNWARD);
+  else if (rm == RUP)
+    fesetround (FE_UPWARD);
+  else
+    {
+      /* No direct match for RMM.  Simulate it.  */
+    }
+
+  return old_rm;
+}
+
+/* Checks whether the fractional part of a floating-point number is
+   exactly 0.5.  If the fractional part is 0.5, the function returns 1;
+   otherwise, it returns 0.  */
+static int
+is_float_halfway (float value)
+{
+  float frac_part, int_part;
+  frac_part = modff (value, &int_part);
+  if (fabsf (frac_part) == 0.5f)
+    return 1;
+  return 0;
+}
+
 /* Handle single precision floating point compare instructions.  */
 static void
 float32_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
@@ -829,22 +882,58 @@ float32_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
 
 /* Handle single precision floating point math instructions.  */
 static void
-float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
+float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2,
+	      int rs3, int rm, int flags)
 {
   struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
-  float a, b, result = 0;
-  uint32_t rs1_bits, rs2_bits, rd_bits;
+  float a, b, c, result = 0;
+  int old_rm, old_except, new_except;
+  uint32_t rs1_bits, rs2_bits, rs3_bits, rd_bits;
   const char *frd_name = riscv_fpr_names_abi[rd];
   const char *frs1_name = riscv_fpr_names_abi[rs1];
   const char *frs2_name = riscv_fpr_names_abi[rs2];
+  const char *frs3_name = riscv_fpr_names_abi[rs3];
+
+  if (rm == DYN)
+    rm = riscv_cpu->csr.frm;
+
+  old_rm = set_riscv_rounding_mode (rm);
+  old_except = fetestexcept (FE_ALL_EXCEPT);
 
   rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1];
   memcpy (&a, &rs1_bits, sizeof (a));
   rs2_bits = (uint32_t) riscv_cpu->fpregs[rs2];
   memcpy (&b, &rs2_bits, sizeof (b));
 
+  if (flags == FMADD || flags == FNMADD
+      || flags == FMSUB || flags == FNMSUB)
+    {
+      rs3_bits = (uint32_t) riscv_cpu->fpregs[rs3];
+      memcpy (&c, &rs3_bits, sizeof (c));
+    }
+
   switch (flags)
     {
+    case FMADD:
+      TRACE_INSN (cpu, "fmadd.s %s, %s, %s, %s, rm=%d;",
+		  frd_name, frs1_name, frs2_name, frs3_name, rm);
+      result = (a * b) + c;
+      break;
+    case FNMADD:
+      TRACE_INSN (cpu, "fnmadd.s %s, %s, %s, %s, rm=%d;",
+		  frd_name, frs1_name, frs2_name, frs3_name, rm);
+      result = -((a * b) - c);
+      break;
+    case FMSUB:
+      TRACE_INSN (cpu, "fmsub.s %s, %s, %s, %s, rm=%d;",
+		  frd_name, frs1_name, frs2_name, frs3_name, rm);
+      result = (a * b) - c;
+      break;
+    case FNMSUB:
+      TRACE_INSN (cpu, "fnmsub.s %s, %s, %s, %s, rm=%d;",
+		  frd_name, frs1_name, frs2_name, frs3_name, rm);
+      result = -((a * b) + c);
+      break;
     case FMAX:
       TRACE_INSN (cpu, "fmax.s %s, %s, %s;", frd_name, frs1_name, frs2_name);
       result = fmaxf (a, b);
@@ -855,9 +944,63 @@ float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
       break;
     }
 
+  if (rm == RMM)
+    {
+      if (is_float_halfway (result))
+	{
+	  if (result > 0)
+	    result = nextafterf (result, INFINITY);
+	  else
+	    result = nextafterf (result, -INFINITY);
+	}
+    }
+
   /* Store result.  */
   memcpy (&rd_bits, &result, sizeof (result));
   store_fp (cpu, rd, rd_bits);
+
+  /* Restore rounding mode.  */
+  fesetround (old_rm);
+
+  /* Set exception.  */
+  new_except = fetestexcept (FE_ALL_EXCEPT);
+
+  if (old_except != new_except)
+    {
+      if (new_except & FE_OVERFLOW)
+	{
+	  riscv_cpu->csr.fcsr |= FCSR_OF;
+	  riscv_cpu->csr.fflags |= FCSR_OF;
+	  TRACE_REGISTER (cpu, "wrote CSR fcsr |= OF");
+	}
+      else if (new_except & FE_UNDERFLOW)
+	{
+	  riscv_cpu->csr.fcsr |= FCSR_UF;
+	  riscv_cpu->csr.fflags |= FCSR_UF;
+	  TRACE_REGISTER (cpu, "wrote CSR fcsr |= UF");
+	}
+      else if (new_except & FE_INEXACT)
+	{
+	  riscv_cpu->csr.fcsr |= FCSR_NX;
+	  riscv_cpu->csr.fflags |= FCSR_NX;
+	  TRACE_REGISTER (cpu, "wrote CSR fcsr |= NX");
+	}
+      else if (new_except & FE_DIVBYZERO)
+	{
+	  riscv_cpu->csr.fcsr |= FCSR_DZ;
+	  riscv_cpu->csr.fflags |= FCSR_DZ;
+	  TRACE_REGISTER (cpu, "wrote CSR fcsr |= DZ");
+	}
+      else if (new_except & FE_INVALID)
+	{
+	  riscv_cpu->csr.fcsr |= FCSR_NV;
+	  riscv_cpu->csr.fflags |= FCSR_NV;
+	  TRACE_REGISTER (cpu, "wrote CSR fcsr |= NV");
+	}
+
+      feclearexcept (FE_ALL_EXCEPT);
+      feraiseexcept (old_except);
+    }
 }
 
 /* Simulate single precision floating point instructions.  */
@@ -869,6 +1012,8 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
   int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
   int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
+  int rs3 = (iw >> OP_SH_RS3) & OP_MASK_RS3;
+  int rm = (iw >> OP_SH_RM) & OP_MASK_RM;
   const char *frd_name = riscv_fpr_names_abi[rd];
   const char *rd_name = riscv_gpr_names_abi[rd];
   const char *frs1_name = riscv_fpr_names_abi[rs1];
@@ -959,10 +1104,10 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	break;
       }
     case MATCH_FMIN_S:
-      float32_math (cpu, rd, rs1, rs2, FMIN);
+      float32_math (cpu, rd, rs1, rs2, 0, -1, FMIN);
       break;
     case MATCH_FMAX_S:
-      float32_math (cpu, rd, rs1, rs2, FMAX);
+      float32_math (cpu, rd, rs1, rs2, 0, -1, FMAX);
       break;
     case MATCH_FRCSR:
       TRACE_INSN (cpu, "frcsr %s;", rd_name);
@@ -1012,6 +1157,22 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       riscv_cpu->csr.fcsr |= rs1 & 0x1f;
       TRACE_REGISTER (cpu, "wrote CSR fcsr = %#" PRIxTW, riscv_cpu->csr.fcsr);
       break;
+    case MATCH_FMADD_S:
+    case MATCH_FMADD_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FMADD);
+      break;
+    case MATCH_FNMADD_S:
+    case MATCH_FNMADD_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FNMADD);
+      break;
+    case MATCH_FMSUB_S:
+    case MATCH_FMSUB_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FMSUB);
+      break;
+    case MATCH_FNMSUB_S:
+    case MATCH_FNMSUB_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FNMSUB);
+      break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
       sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
diff --git a/sim/testsuite/riscv/s-basic-arith.s b/sim/testsuite/riscv/s-basic-arith.s
new file mode 100644
index 00000000000..a05a0d0a2c3
--- /dev/null
+++ b/sim/testsuite/riscv/s-basic-arith.s
@@ -0,0 +1,80 @@
+# Single precision basic arithmetic tests.
+# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IF
+# sim(riscv64): --model RV64ID
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32if
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+	.section	.data
+	.align 2
+
+_arg1:
+	.float -12.5
+
+_arg2:
+	.float 2.5
+
+_arg3:
+	.float 7.45
+
+_result:
+	.float -23.799999
+	.float 38.7000008
+	.float -38.7000008
+	.float 23.7999992
+
+	start
+	.option push
+	.option norelax
+	la	a0,_arg1
+	la	a1,_arg2
+	la	a2,_arg3
+	la	a3,_result
+	li	a4,1
+	.option pop
+
+	# Test fmadd instruction.
+	flw	fa0,0(a0)
+	flw	fa1,0(a1)
+	flw	fa2,0(a2)
+	flw	fa3,0(a3)
+	fmadd.s	fa4,fa0,fa1,fa0,rne
+	feq.s	a5,fa4,fa4
+	bne	a5,a4,test_fail
+
+	# Test fnmadd instruction.
+	flw	fa0,0(a0)
+	flw	fa1,0(a1)
+	flw	fa2,0(a2)
+	flw	fa3,4(a3)
+	fnmadd.s	fa4,fa0,fa1,fa0,rne
+	feq.s	a5,fa4,fa4
+	bne	a5,a4,test_fail
+
+	# Test fmsub instruction.
+	flw	fa0,0(a0)
+	flw	fa1,0(a1)
+	flw	fa2,0(a2)
+	flw	fa3,8(a3)
+	fmsub.s	fa4,fa0,fa1,fa0,rne
+	feq.s	a5,fa4,fa4
+	bne	a5,a4,test_fail
+
+	# Test fnmsub instruction.
+	flw	fa0,0(a0)
+	flw	fa1,0(a1)
+	flw	fa2,0(a2)
+	flw	fa3,12(a3)
+	fmsub.s	fa4,fa0,fa1,fa0,rne
+	feq.s	a5,fa4,fa4
+	bne	a5,a4,test_fail
+
+test_pass:
+	pass
+
+test_fail:
+	fail
-- 
2.25.1

[PATCH 05/11] sim: riscv: Add single precision floating-point basic arithmetic instructions

[bhushan.attarde]

From: Bhushan Attarde <bhushan.attarde@imgtec.com>

Added simulation of following single precision floating-point instructions
fadd.s, fsub.s, fmul.s, fdiv.s and fsqrt.s.

Updated test file sim/testsuite/riscv/s-basic-arith.s to test these
instructions.
---
 sim/riscv/sim-main.c                | 50 ++++++++++++++++++++++++++++
 sim/testsuite/riscv/s-basic-arith.s | 51 +++++++++++++++++++++++++++++
 2 files changed, 101 insertions(+)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index dd91431ad12..5d8ff9dc6ee 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -91,6 +91,11 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
 #define FMSUB	8
 #define FNMADD	9
 #define FNMSUB	10
+#define FADD	11
+#define FSUB	12
+#define FMUL	13
+#define FDIV	14
+#define FSQRT	15
 
 static INLINE void
 store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
@@ -942,6 +947,31 @@ float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2,
       TRACE_INSN (cpu, "fmin.s %s, %s, %s;", frd_name, frs1_name, frs2_name);
       result = fminf (a, b);
       break;
+    case FADD:
+      TRACE_INSN (cpu, "fadd.s %s, %s, %s, rm=%d;",
+		  frd_name, frs1_name, frs2_name, rm);
+      result = a + b;
+      break;
+    case FSUB:
+      TRACE_INSN (cpu, "fsub.s %s, %s, %s, rm=%d;",
+		  frd_name, frs1_name, frs2_name, rm);
+      result = a - b;
+      break;
+    case FMUL:
+      TRACE_INSN (cpu, "fmul.s %s, %s, %s, rm=%d;",
+	frd_name, frs1_name, frs2_name, rm);
+      result = a * b;
+      break;
+    case FDIV:
+      TRACE_INSN (cpu, "fdiv.s %s, %s, %s, rm=%d;",
+		  frd_name, frs1_name, frs2_name, rm);
+      result = a / b;
+      break;
+    case FSQRT:
+      TRACE_INSN (cpu, "fsqrt.s %s, %s, rm=%d;",
+		  frd_name, frs1_name, rm);
+      result = sqrtf (a);
+      break;
     }
 
   if (rm == RMM)
@@ -1173,6 +1203,26 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_FNMSUB_S | MASK_RM:
       float32_math (cpu, rd, rs1, rs2, rs3, rm, FNMSUB);
       break;
+    case MATCH_FADD_S:
+    case MATCH_FADD_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FADD);
+      break;
+    case MATCH_FSUB_S:
+    case MATCH_FSUB_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FSUB);
+      break;
+    case MATCH_FMUL_S:
+    case MATCH_FMUL_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FMUL);
+      break;
+    case MATCH_FDIV_S:
+    case MATCH_FDIV_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FDIV);
+      break;
+    case MATCH_FSQRT_S:
+    case MATCH_FSQRT_S | MASK_RM:
+      float32_math (cpu, rd, rs1, rs2, rs3, rm, FSQRT);
+      break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
       sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
diff --git a/sim/testsuite/riscv/s-basic-arith.s b/sim/testsuite/riscv/s-basic-arith.s
index a05a0d0a2c3..15d07f9e6cd 100644
--- a/sim/testsuite/riscv/s-basic-arith.s
+++ b/sim/testsuite/riscv/s-basic-arith.s
@@ -14,9 +14,16 @@
 
 _arg1:
 	.float -12.5
+	.float 1.5
+	.float 2.2
+	.float 1.75
+	.float 5.0
 
 _arg2:
 	.float 2.5
+	.float 0.5
+	.float 1.1
+	.float 0.1
 
 _arg3:
 	.float 7.45
@@ -26,6 +33,11 @@ _result:
 	.float 38.7000008
 	.float -38.7000008
 	.float 23.7999992
+	.float 2.0
+	.float 1.1
+	.float 0.175
+	.float 17.5
+	.float 2.23606801
 
 	start
 	.option push
@@ -73,6 +85,45 @@ _result:
 	feq.s	a5,fa4,fa4
 	bne	a5,a4,test_fail
 
+	# Test fadd instruction.
+	flw	fa0,4(a0)
+	flw	fa1,4(a1)
+	flw	fa2,16(a3)
+	fadd.s	fa4,fa0,fa1,rne
+	feq.s	a5,fa4,fa2
+	bne	a5,a4,test_fail
+
+	# Test fsub instruction.
+	flw	fa0,8(a0)
+	flw	fa1,8(a1)
+	flw	fa2,20(a3)
+	fsub.s	fa4,fa0,fa1,rne
+	feq.s	a5,fa4,fa2
+	bne	a5,a4,test_fail
+
+	# Test fmul instruction.
+	flw	fa0,12(a0)
+	flw	fa1,12(a1)
+	flw	fa2,24(a3)
+	fmul.s	fa4,fa0,fa1,rne
+	feq.s	a5,fa4,fa2
+	bne	a5,a4,test_fail
+
+	# Test fdiv instruction.
+	flw	fa0,12(a0)	# Use same input values as of fmul
+	flw	fa1,12(a1)
+	flw	fa2,28(a3)
+	fdiv.s	fa4,fa0,fa1,rne
+	feq.s	a5,fa4,fa2
+	bne	a5,a4,test_fail
+
+	# Test fsqrt instruction.
+	flw	fa0,16(a0)
+	flw	fa2,32(a3)
+	fsqrt.s	fa4,fa0,rne
+	feq.s	a5,fa4,fa2
+	bne	a5,a4,test_fail
+
 test_pass:
 	pass
 
-- 
2.25.1

[PATCH 06/11] sim: riscv: Add single-precision floating-point conversion instructions

[bhushan.attarde]

From: Bhushan Attarde <bhushan.attarde@imgtec.com>

Added simulation of following single precision floating-point instructions
fcvt.w.s, fcvt.wu.s, fcvt.s.w, fcvt.s.wu, fcvt.l.s, fcvt.lu.s, fcvt.s.l and
fcvt.s.lu.

Added test files s-conversion.s and s-conversion-l.s in
sim/testsuite/riscv/s-conversion.s to test these instructions.
---
 sim/riscv/sim-main.c                 | 265 +++++++++++++++++++++++++++
 sim/testsuite/riscv/s-conversion-l.s |  60 ++++++
 sim/testsuite/riscv/s-conversion.s   |  61 ++++++
 3 files changed, 386 insertions(+)
 create mode 100644 sim/testsuite/riscv/s-conversion-l.s
 create mode 100644 sim/testsuite/riscv/s-conversion.s

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 5d8ff9dc6ee..4d4ad82cce9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -97,6 +97,9 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
 #define FDIV	14
 #define FSQRT	15
 
+#define UNSIGNED	0
+#define SIGNED	1
+
 static INLINE void
 store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
 {
@@ -1033,6 +1036,224 @@ float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2,
     }
 }
 
+/* Round and return the float value.  This function is used before we
+   perform any operation on the input float value.  */
+static float
+round_float_input (float value, int rm)
+{
+  float result = value;
+  if (rm == RNE)
+    {
+      float fractional_part = value - truncf (value);
+      /* Check if the number is halfway between two values.  */
+      if (fractional_part == 0.5 || fractional_part == -0.5)
+	{
+	  result = floorf (value);
+	  if (fmod (result, 2.0) != 0)
+	    result += (value > 0) ? 1.0 : -1.0;
+	}
+      else
+	result = roundf (value);
+    }
+  else if (rm == RTZ)
+    result = truncf (value);
+  else if (rm == RDN)
+    result = floorf (value);
+  else if (rm == RUP)
+    result = ceilf (value);
+  else
+    {
+      /* No direct match for RMM.  Simulate it.  */
+      float fracPart = value - (int) value;
+      if (fracPart > 0.5f || fracPart < -0.5f)
+	result = roundf (value);
+      else if (fracPart == 0.5f)
+	result = ceilf (value);
+      else if (fracPart == -0.5f)
+	result = floorf (value);
+      else
+	result = value;
+    }
+  return result;
+}
+
+/* Round and return the float value.  This function is used after we
+   perform the operation to get the result rounded.  */
+static float
+round_float_output (float value, int rm)
+{
+  float result;
+  if (rm == RNE)
+    result = value;
+  else if (rm == RTZ)
+    result = truncf (value);
+  else if (rm == RDN)
+    result = floorf (value);
+  else if (rm == RUP)
+    result = ceilf (value);
+  else
+    {
+      /* No direct match for RMM.  Simulate it.  */
+      float fracPart = value - (int) value;
+      if (fracPart > 0.5f || fracPart < -0.5f)
+	result = roundf (value);
+      else if (fracPart == 0.5f)
+	result = ceilf (value);
+      else if (fracPart == -0.5f)
+	result = floorf (value);
+      else
+	result = value;
+    }
+  return result;
+}
+
+static void
+convert_float_to_int (SIM_CPU *cpu, int rd, int rs1, int sign,
+		      int rm, int is_32bit)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  float src, rounded;
+  uint32_t rs1_bits;
+  rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1];
+  memcpy (&src, &rs1_bits, sizeof (src));
+
+  if (rm == DYN)
+    rm = riscv_cpu->csr.frm;
+
+  /* Get the input rounded.  */
+  rounded = round_float_input (src, rm);
+
+  if (sign == SIGNED)
+    {
+      if (is_32bit)
+	store_rd (cpu, rd, (int) rounded);
+      else
+	store_rd (cpu, rd, (int64_t) rounded);
+    }
+  else
+    {
+      if (is_32bit)
+	store_rd (cpu, rd, (uint32_t) rounded);
+      else
+	store_rd (cpu, rd, (uint64_t) rounded);
+    }
+}
+
+static void
+convert_int_to_float (SIM_CPU *cpu, int rd, int rs1, int sign,
+		      int rm)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  uint32_t rd_bits;
+  uint32_t usrc = (uint32_t) riscv_cpu->regs[rs1];
+  int32_t isrc = (int32_t) riscv_cpu->regs[rs1];
+  float result = .0f;
+  int old_rm;
+  if (rm == DYN)
+    rm = riscv_cpu->csr.frm;
+
+  if (rm == RMM)
+    {
+      if (sign == SIGNED)
+	{
+	  if (isrc >= 0)
+	    {
+	      fesetround (FE_UPWARD);
+	      result = (float) isrc;
+	      result = ceilf (result);
+	    }
+	  else
+	    {
+	      fesetround (FE_DOWNWARD);
+	      result = (float) isrc;
+	      result = floorf (result);
+	    }
+	}
+      else
+	{
+	  /* Since it's unsigned, it's always positive.  */
+	  fesetround (FE_UPWARD);
+	  result = (float) usrc;
+	  result = ceilf (result);
+	}
+    }
+  else
+    {
+      old_rm = set_riscv_rounding_mode (rm);
+
+      if (sign == SIGNED)
+	result = (float) isrc;
+      else
+	result = (float) usrc;
+
+      /* Get the result rounded.  */
+      result = round_float_output (result, rm);
+      /* Restore rounding mode.  */
+      fesetround (old_rm);
+    }
+  /* Store the result.  */
+  memcpy (&rd_bits, &result, sizeof (result));
+  store_fp (cpu, rd, rd_bits);
+}
+
+static void
+convert_long_to_float (SIM_CPU *cpu, int rd, int rs1, int sign,
+		      int rm)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  uint32_t rd_bits;
+  uint64_t usrc = (uint64_t) riscv_cpu->regs[rs1];
+  int64_t isrc = (int64_t) riscv_cpu->regs[rs1];
+  float result = .0f;
+  int old_rm;
+
+  if (rm == DYN)
+    rm = riscv_cpu->csr.frm;
+
+  if (rm == RMM)
+    {
+      if (sign == SIGNED)
+	{
+	  if (isrc > 0)
+	    {
+	      fesetround (FE_UPWARD);
+	      result = (float) isrc;
+	      result = ceilf (result);
+	    }
+	  else
+	    {
+	      fesetround (FE_DOWNWARD);
+	      result = (float) isrc;
+	      result = floorf (result);
+	    }
+	}
+      else
+	{
+	  /* Since it's unsigned, it's always positive.  */
+	  fesetround (FE_UPWARD);
+	  result = (float) usrc;
+	  result = ceilf (result);
+	}
+    }
+  else
+    {
+      old_rm = set_riscv_rounding_mode (rm);
+
+      if (sign == SIGNED)
+	result = (float) isrc;
+      else
+	result = (float) usrc;
+
+      /* Get the result rounded.  */
+      result = round_float_output (result, rm);
+      /* Restore rounding mode.  */
+      fesetround (old_rm);
+    }
+  /* Store the result.  */
+  memcpy (&rd_bits, &result, sizeof (result));
+  store_fp (cpu, rd, rd_bits);
+}
+
 /* Simulate single precision floating point instructions.  */
 static sim_cia
 execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
@@ -1223,6 +1444,50 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_FSQRT_S | MASK_RM:
       float32_math (cpu, rd, rs1, rs2, rs3, rm, FSQRT);
       break;
+    case MATCH_FCVT_W_S:
+    case MATCH_FCVT_W_S | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.w.s %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      convert_float_to_int (cpu, rd, rs1, SIGNED, rm, is_32bit);
+      break;
+    case MATCH_FCVT_WU_S:
+    case MATCH_FCVT_WU_S | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.wu.s %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      convert_float_to_int (cpu, rd, rs1, UNSIGNED, rm, is_32bit);
+      break;
+    case MATCH_FCVT_S_W:
+    case MATCH_FCVT_S_W | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.s.w %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      convert_int_to_float (cpu, rd, rs1, SIGNED, rm);
+      break;
+    case MATCH_FCVT_S_WU:
+    case MATCH_FCVT_S_WU | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.s.wu %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      convert_int_to_float (cpu, rd, rs1, UNSIGNED, rm);
+      break;
+    case MATCH_FCVT_L_S:
+    case MATCH_FCVT_L_S | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.l.s %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+      convert_float_to_int (cpu, rd, rs1, SIGNED, rm, is_32bit);
+      break;
+    case MATCH_FCVT_LU_S:
+    case MATCH_FCVT_LU_S | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.lu.s %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+      convert_float_to_int (cpu, rd, rs1, UNSIGNED, rm, is_32bit);
+      break;
+    case MATCH_FCVT_S_L:
+    case MATCH_FCVT_S_L | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.s.l %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+      convert_long_to_float (cpu, rd, rs1, SIGNED, rm);
+      break;
+    case MATCH_FCVT_S_LU:
+    case MATCH_FCVT_S_LU | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.s.lu %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+      convert_long_to_float (cpu, rd, rs1, UNSIGNED, rm);
+      break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
       sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
diff --git a/sim/testsuite/riscv/s-conversion-l.s b/sim/testsuite/riscv/s-conversion-l.s
new file mode 100644
index 00000000000..a3b0f264d47
--- /dev/null
+++ b/sim/testsuite/riscv/s-conversion-l.s
@@ -0,0 +1,60 @@
+# Single precision conversion tests only for RV64.
+# mach: riscv64
+# sim(riscv64): --model RV64ID
+# ld(riscv64): -m elf64lriscv
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+	.section	.rodata
+	.align 2
+
+_arg1:
+	.float -3e9
+	.float 3e9
+	.dword 16777217
+
+_result:
+	.dword -3000000000
+	.dword 3000000000
+	.float 16777216
+
+	start
+	.option push
+	.option norelax
+	la	a0,_arg1
+	la	a1,_result
+	li	a2,1
+	.option pop
+
+	# Test fcvt.l.s instruction.
+	flw	fa0,0(a0)
+	ld	a3,0(a1)
+	fcvt.l.s	a5,fa0,rne
+	bne	a5,a3,test_fail
+
+	# Test fcvt.lu.s instruction.
+	flw	fa0,4(a0)
+	ld	a3,8(a1)
+	fcvt.lu.s	a5,fa0,rne
+	bne	a5,a3,test_fail
+
+	# Test fcvt.s.l instruction.
+	ld	a3,8(a0)
+	flw	fa0,16(a1)
+	fcvt.s.l	fa1,a3,rne
+	feq.s	a4,fa0,fa1
+	bne	a4,a2,test_fail
+
+	# Test fcvt.s.lu instruction.
+	ld	a3,8(a0)
+	flw	fa0,16(a1)
+	fcvt.s.l	fa1,a3,rne
+	feq.s	a4,fa0,fa1
+	bne	a4,a2,test_fail
+
+test_pass:
+	pass
+
+test_fail:
+	fail
diff --git a/sim/testsuite/riscv/s-conversion.s b/sim/testsuite/riscv/s-conversion.s
new file mode 100644
index 00000000000..e87059c1d2f
--- /dev/null
+++ b/sim/testsuite/riscv/s-conversion.s
@@ -0,0 +1,61 @@
+# Single precision conversion tests.
+# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IF
+# sim(riscv64): --model RV64ID
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32if
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+	.section	.rodata
+	.align 2
+
+_arg1:
+	.float 123.49
+	.word 123
+
+_result:
+	.word 123
+	.float 123.0
+
+	start
+	.option push
+	.option norelax
+	la	a0,_arg1
+	la	a1,_result
+	li	a2,1
+	.option pop
+
+	# Test fcvt.w.s instruction.
+	flw	fa0,0(a0)
+	lw	a3,0(a1)
+	fcvt.w.s	a5,fa0,rne
+	bne	a3,a5,test_fail
+
+	# Test fcvt.wu.s instruction.
+	flw	fa0,0(a0)
+	lw	a3,0(a1)
+	fcvt.wu.s	a5,fa0,rne
+	bne	a3,a5,test_fail
+
+	# Test fcvt.s.w instruction.
+	lw	a3,4(a0)
+	flw	fa0,4(a1)
+	fcvt.s.w	fa1,a3,rne
+	feq.s	a4,fa0,fa1
+	bne	a4,a2,test_fail
+
+	# Test fcvt.s.wu instruction.
+	lw	a3,4(a0)
+	flw	fa0,4(a1)
+	fcvt.s.wu	fa1,a3,rne
+	feq.s	a4,fa0,fa1
+	bne	a4,a2,test_fail
+
+test_pass:
+	pass
+
+test_fail:
+	fail
-- 
2.25.1

[PATCH 07/11] sim: riscv: Add double precision floating-point load-store, move, compare and classify instructions

[bhushan.attarde]

From: Bhushan Attarde <bhushan.attarde@imgtec.com>

Added simulation of following single precision floating-point instructions
fld, fsd, fmv.x.d, fmv.d.x, fsgnj.d, feq.d, flt.d, fle.d and fclass.d.

Added test files d-fp-compare.s and d-fp-load-store.s in sim/testsuite/riscv/
to test these instructions.
---
 sim/riscv/sim-main.c                  | 183 ++++++++++++++++++++++++++
 sim/testsuite/riscv/d-fp-compare.s    |  72 ++++++++++
 sim/testsuite/riscv/d-fp-load-store.s |  58 ++++++++
 3 files changed, 313 insertions(+)
 create mode 100755 sim/testsuite/riscv/d-fp-compare.s
 create mode 100755 sim/testsuite/riscv/d-fp-load-store.s

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4d4ad82cce9..4313516b8b7 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1254,6 +1254,111 @@ convert_long_to_float (SIM_CPU *cpu, int rd, int rs1, int sign,
   store_fp (cpu, rd, rd_bits);
 }
 
+/* Handle double precision floating point compare instructions.  */
+static void
+float64_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  double a, b = .0f;
+  uint64_t result = 0, exception = 0, sign = 0, bit_pos;
+  uint64_t rs1_bits, rs2_bits;
+  const char *rd_name = riscv_gpr_names_abi[rd];
+  const char *frs1_name = riscv_fpr_names_abi[rs1];
+  const char *frs2_name = riscv_fpr_names_abi[rs2];
+
+  rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1];
+  memcpy (&a, &rs1_bits, sizeof (a));
+  if (flags != FCLASS)
+    {
+      rs2_bits = (uint64_t) riscv_cpu->fpregs[rs2];
+      memcpy (&b, &rs2_bits, sizeof (b));
+    }
+
+  switch (flags)
+    {
+    case FEQ:
+      TRACE_INSN (cpu, "feq.d %s, %s, %s;", rd_name, frs1_name, frs2_name);
+      if (__isnan (a) || __isnan (b))
+	{
+	  result = 0;
+	  if (__issignaling (a) || __issignaling (b))
+	    exception = 1;
+	}
+      else
+	result = (a == b);
+      break;
+    case FLT:
+      TRACE_INSN (cpu, "flt.d %s, %s, %s;", rd_name, frs1_name, frs2_name);
+      if (__isnan (a) || __isnan (b))
+	{
+	  result = 0;
+	  exception = 1;
+	}
+      else
+	result = (a < b);
+      break;
+    case FLE:
+      TRACE_INSN (cpu, "fle.d %s, %s, %s;", rd_name, frs1_name, frs2_name);
+      if (__isnan (a) || __isnan (b))
+	{
+	  result = 0;
+	  exception = 1;
+	}
+      else
+	result = (a <= b);
+      break;
+    case FCLASS:
+      TRACE_INSN (cpu, "fclass.d %s, %s;", rd_name, frs1_name);
+      bit_pos = 0;
+      exception = 0;
+      result = riscv_cpu->regs[rd];
+      sign = __signbit (a);
+      if (__isinf (a))
+	{
+	  if (sign)
+	    bit_pos = 0;	/* -INF.  */
+	  else
+	    bit_pos = 7;	/* +INF.  */
+	}
+      else if (fpclassify (a) == FP_SUBNORMAL)
+	{
+	  if (sign)
+	    bit_pos = 2;	/* -SUBNORMAL.  */
+	  else
+	    bit_pos = 5;	/* +SUBNORMAL.  */
+	}
+      else if (fpclassify (a) == FP_ZERO)
+	{
+	  if (sign)
+	    bit_pos = 3;	/* -ZERO.  */
+	  else
+	    bit_pos = 4;	/* +ZERO.  */
+	}
+      else if (__issignaling (a))
+	bit_pos = 8;	/* signaling NaN.  */
+      else if (__isnan (a))
+	bit_pos = 9;	/* quiet NaN.  */
+      else
+	{
+	  if (sign)
+	    bit_pos = 1;	/* -NORMAL.  */
+	  else
+	    bit_pos = 6;	/* +NORMAL.  */
+	}
+      result |= (1 << bit_pos);
+      break;
+    }
+
+  store_rd (cpu, rd, result);
+
+  if (exception)
+    {
+      riscv_cpu->csr.fcsr |= FCSR_NV;
+      riscv_cpu->csr.fflags |= FCSR_NV;
+      TRACE_REGISTER (cpu, "wrote CSR fcsr |= NV");
+    }
+}
+
 /* Simulate single precision floating point instructions.  */
 static sim_cia
 execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
@@ -1496,6 +1601,81 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   return pc;
 }
 
+/* Simulate double precision floating point instructions.  */
+static sim_cia
+execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  SIM_DESC sd = CPU_STATE (cpu);
+  int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+  int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
+  int rs2 = (iw >> OP_SH_RS2) & OP_MASK_RS2;
+  const char *frd_name = riscv_fpr_names_abi[rd];
+  const char *rd_name = riscv_gpr_names_abi[rd];
+  const char *frs1_name = riscv_fpr_names_abi[rs1];
+  const char *frs2_name = riscv_fpr_names_abi[rs2];
+  const char *rs1_name = riscv_gpr_names_abi[rs1];
+  signed_word i_imm = EXTRACT_ITYPE_IMM (iw);
+  signed_word s_imm = EXTRACT_STYPE_IMM (iw);
+
+  sim_cia pc = riscv_cpu->pc + 4;
+
+  switch (op->match)
+    {
+    case MATCH_FLD:
+      TRACE_INSN (cpu, "fld %s, %" PRIiTW "(%s);",
+		  frd_name, i_imm, rs1_name);
+      store_fp (cpu, rd, sim_core_read_unaligned_8
+				(cpu, riscv_cpu->pc, read_map,
+				 riscv_cpu->regs[rs1] + i_imm));
+      break;
+    case MATCH_FSD:
+      TRACE_INSN (cpu, "fsd %s, %" PRIiTW "(%s);",
+		  frs2_name, s_imm, rs1_name);
+      sim_core_write_unaligned_8
+	(cpu, riscv_cpu->pc, write_map,
+	 riscv_cpu->regs[rs1] + s_imm, riscv_cpu->fpregs[rs2]);
+      break;
+    case MATCH_FMV_X_D:
+      TRACE_INSN (cpu, "fmv.x.d %s, %s;", rd_name, frs1_name);
+      store_rd (cpu, rd, riscv_cpu->fpregs[rs1]);
+      break;
+    case MATCH_FMV_D_X:
+      TRACE_INSN (cpu, "fmv.d.x %s, %s;", frd_name, rs1_name);
+      store_fp (cpu, rd, riscv_cpu->regs[rs1]);
+      break;
+    case MATCH_FEQ_D:
+      float64_compare (cpu, rd, rs1, rs2, FEQ);
+      break;
+    case MATCH_FLT_D:
+      float64_compare (cpu, rd, rs1, rs2, FLT);
+      break;
+    case MATCH_FLE_D:
+      float64_compare (cpu, rd, rs1, rs2, FLE);
+      break;
+    case MATCH_FCLASS_D:
+      float64_compare (cpu, rd, rs1, 0, FCLASS);
+      break;
+    case MATCH_FSGNJ_D:
+      {
+	uint64_t rs1_bits, rs2_bits;
+	TRACE_INSN (cpu, "fsgnj.d %s, %s, %s;",
+		    frd_name, frs1_name, frs2_name);
+	rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1];
+	rs2_bits = (uint64_t) riscv_cpu->fpregs[rs2];
+	rs1_bits = (rs2_bits & 0x8000000000000000ull)
+		    | (rs1_bits & 0x7fffffffffffffffull);
+	store_fp (cpu, rd, rs1_bits);
+	break;
+      }
+    default:
+      TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+      sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
+    }
+
+  return pc;
+}
+
 static sim_cia
 execute_m (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 {
@@ -2127,6 +2307,9 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	  sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled,
 			   SIM_SIGILL);
 	}
+    case INSN_CLASS_D:
+    case INSN_CLASS_D_INX:
+      return execute_d (cpu, iw, op);
     case INSN_CLASS_F:
     case INSN_CLASS_F_INX:
       return execute_f (cpu, iw, op);
diff --git a/sim/testsuite/riscv/d-fp-compare.s b/sim/testsuite/riscv/d-fp-compare.s
new file mode 100755
index 00000000000..0e168fed9de
--- /dev/null
+++ b/sim/testsuite/riscv/d-fp-compare.s
@@ -0,0 +1,72 @@
+# Double precision compare and classify tests.
+# mach: riscv64
+# sim(riscv64): --model RV64ID
+# ld(riscv64): -m elf64lriscv
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+	.section	.data
+	.align 3
+
+_arg1:
+	.double 0.5
+	.double 1.1
+	.dword 0xfff0000000000000	# -INF
+	.dword 0x7ff4000000000000	# sNAN
+	.dword 0x7ff8000000000000	# qNAN
+
+_arg2:
+	.double 0.5
+	.double 2.2
+
+	start
+	.option push
+	.option norelax
+	la	a0,_arg1
+	la	a1,_arg2
+	li	a3,1
+	.option pop
+
+	# Test feq instruction.
+	fld	fa0,0(a0)
+	fld	fa1,0(a1)
+	feq.d	a4,fa0,fa1
+	bne	a4,a3,test_fail
+
+	# Test flt instruction.
+	fld	fa0,8(a0)
+	fld	fa1,8(a1)
+	mv	a4,x0
+	flt.d	a4,fa0,fa1
+	bne	a4,a3,test_fail
+
+	# Test fle instruction.
+	fld	fa0,8(a0)
+	fld	fa1,8(a1)
+	mv	a4,x0
+	fle.d	a4,fa0,fa1
+	bne	a4,a3,test_fail
+
+	# Test fclass instruction.
+	fld	fa0,16(a0)
+	mv	a4,x0
+	li	a3,0x1	# 1 << 0
+	fclass.d	a4,fa0
+	bne	a3,a4,test_fail
+	fld	fa0,24(a0)
+	mv	a4,x0
+	li	a3,0x100	# 1 << 8
+	fclass.d	a4,fa0
+	bne	a3,a4,test_fail
+	fld	fa0,32(a0)
+	mv	a4,x0
+	li	a3,0x200	# 1 << 9
+	fclass.d	a4,fa0
+	bne	a3,a4,test_fail
+
+test_pass:
+	pass
+
+test_fail:
+	fail
diff --git a/sim/testsuite/riscv/d-fp-load-store.s b/sim/testsuite/riscv/d-fp-load-store.s
new file mode 100755
index 00000000000..1eccf5720a9
--- /dev/null
+++ b/sim/testsuite/riscv/d-fp-load-store.s
@@ -0,0 +1,58 @@
+# Double precision load-store and move tests.
+# mach: riscv64
+# sim(riscv64): --model RV64ID
+# ld(riscv64): -m elf64lriscv
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+	.section	.data
+	.align 3
+
+_src:
+	.double 0.5
+
+_dst:
+	.double 0.5
+	.double 0
+	.dword 0x3FE0000000000000	# 0.5
+
+	start
+	.option push
+	.option norelax
+	la	a0,_src
+	la	a1,_dst
+	li	a3,1
+	.option pop
+
+	# Test load instruction.
+	fld	fa0,0(a0)
+	fld	fa1,0(a1)
+	feq.d	a4,fa0,fa1
+	bne	a4,a3,test_fail
+
+	# Test store instruction.
+	fld	fa0,0(a0)
+	fsd	fa0,8(a1)
+	fld	fa1,8(a1)
+	feq.d	a4,fa0,fa1
+	bne	a4,a3,test_fail
+
+	# Test convert double value to integer encoding instruction.
+	fld	fa0,0(a0)	# load double value.
+	ld	a4,16(a1)	# load expected result.
+	fmv.x.d	a2,fa0		# convert bit pattern into integer register.
+	bne	a4,a2,test_fail	# compare result with expected.
+
+	# Test convert integer encoding to double value instruction.
+	lw	a4,16(a1)	# load integer encoding.
+	fmv.d.x	fa1,a4		# convert encoding into double value.
+	flw	fa0,0(a0)	# load expected double value.
+	feq.d	a5,fa0,fa1	# compare result with expected.
+	bne	a5,a3,test_fail
+
+test_pass:
+	pass
+
+test_fail:
+	fail
-- 
2.25.1

[PATCH 08/11] sim: riscv: Add double precision floating-point sign-injection, min and max instructions

[bhushan.attarde]

From: Bhushan Attarde <bhushan.attarde@imgtec.com>

Added simulation of following single precision floating-point instructions
fsgnjn.d, fsgnjx.d, fmin.d and fmax.d.

Updated test file d-fp-compare.s and added d-fp-sign-inject.s in
sim/testsuite/riscv/ to test these instructions.
---
 sim/riscv/sim-main.c                   | 65 +++++++++++++++++++
 sim/testsuite/riscv/d-fp-compare.s     | 22 +++++++
 sim/testsuite/riscv/d-fp-sign-inject.s | 87 ++++++++++++++++++++++++++
 3 files changed, 174 insertions(+)
 create mode 100644 sim/testsuite/riscv/d-fp-sign-inject.s

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4313516b8b7..4f347fbfc5e 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1359,6 +1359,40 @@ float64_compare (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
     }
 }
 
+/* Handle double precision floating point math instructions.  */
+static void
+float64_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int flags)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  double a, b, result = 0;
+  uint64_t rs1_bits, rs2_bits, rd_bits;
+  const char *frd_name = riscv_fpr_names_abi[rd];
+  const char *frs1_name = riscv_fpr_names_abi[rs1];
+  const char *frs2_name = riscv_fpr_names_abi[rs2];
+
+  rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1];
+  memcpy (&a, &rs1_bits, sizeof (a));
+  rs2_bits = (uint64_t) riscv_cpu->fpregs[rs2];
+  memcpy (&b, &rs2_bits, sizeof (b));
+
+  switch (flags)
+    {
+    case FMAX:
+      TRACE_INSN (cpu, "fmax.d %s, %s, %s;", frd_name, frs1_name, frs2_name);
+      result = fmax (a, b);
+      break;
+    case FMIN:
+      TRACE_INSN (cpu, "fmin.d %s, %s, %s;", frd_name, frs1_name, frs2_name);
+      result = fmin (a, b);
+      break;
+    }
+
+  /* Store result.  */
+  memcpy (&rd_bits, &result, sizeof (result));
+  store_fp (cpu, rd, rd_bits);
+
+}
+
 /* Simulate single precision floating point instructions.  */
 static sim_cia
 execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
@@ -1668,6 +1702,37 @@ execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 	store_fp (cpu, rd, rs1_bits);
 	break;
       }
+    case MATCH_FSGNJN_D:
+      {
+	uint64_t rs1_bits, rs2_bits;
+	TRACE_INSN (cpu, "fsgnjn.d %s, %s, %s;", frd_name, frs1_name,
+		    frs2_name);
+	rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1];
+	rs2_bits = ~((uint64_t) riscv_cpu->fpregs[rs2]);
+	rs1_bits = (rs2_bits & 0x8000000000000000ull)
+		    | (rs1_bits & 0x7fffffffffffffffull);
+	store_fp (cpu, rd, rs1_bits);
+	break;
+      }
+    case MATCH_FSGNJX_D:
+      {
+	uint64_t rs1_bits, rs2_bits;
+	TRACE_INSN (cpu, "fsgnjx.d %s, %s, %s;", frd_name, frs1_name,
+		    frs2_name);
+	rs1_bits = (uint64_t) riscv_cpu->fpregs[rs1];
+	rs2_bits = (uint64_t) riscv_cpu->fpregs[rs2];
+	rs1_bits = ((rs1_bits & 0x8000000000000000ull)
+		    ^ (rs2_bits & 0x8000000000000000ull))
+			| (rs1_bits & 0x7fffffffffffffffull);
+	store_fp (cpu, rd, rs1_bits);
+	break;
+      }
+    case MATCH_FMIN_D:
+      float64_math (cpu, rd, rs1, rs2, FMIN);
+      break;
+    case MATCH_FMAX_D:
+      float64_math (cpu, rd, rs1, rs2, FMAX);
+      break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
       sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
diff --git a/sim/testsuite/riscv/d-fp-compare.s b/sim/testsuite/riscv/d-fp-compare.s
index 0e168fed9de..1a926211216 100755
--- a/sim/testsuite/riscv/d-fp-compare.s
+++ b/sim/testsuite/riscv/d-fp-compare.s
@@ -20,11 +20,16 @@ _arg2:
 	.double 0.5
 	.double 2.2
 
+_expected:
+	.double 0.5
+	.double 2.2
+
 	start
 	.option push
 	.option norelax
 	la	a0,_arg1
 	la	a1,_arg2
+	la	a2,_expected
 	li	a3,1
 	.option pop
 
@@ -65,6 +70,23 @@ _arg2:
 	fclass.d	a4,fa0
 	bne	a3,a4,test_fail
 
+	# Test fmin.d instruction.
+	fld	fa0,0(a0)
+	fld	fa1,8(a1)
+	fld	fa2,0(a2)
+	fmin.d	fa3,fa0,fa1
+	feq.d	a4,fa3,fa2
+	li	a3,1
+	bne	a4,a3,test_fail
+
+	# Test fmax.d instruction.
+	fld	fa0,0(a0)
+	fld	fa1,8(a1)
+	fld	fa2,8(a2)
+	fmax.d	fa3,fa0,fa1
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+
 test_pass:
 	pass
 
diff --git a/sim/testsuite/riscv/d-fp-sign-inject.s b/sim/testsuite/riscv/d-fp-sign-inject.s
new file mode 100644
index 00000000000..c2f61ba3cdd
--- /dev/null
+++ b/sim/testsuite/riscv/d-fp-sign-inject.s
@@ -0,0 +1,87 @@
+# Double precision sign-injection instructions.
+# mach: riscv64
+# sim(riscv64): --model RV64ID
+# ld(riscv64): -m elf64lriscv
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+	.section	.data
+	.align 3
+
+_arg1:
+	.double 2.0
+	.double -2.0
+
+_arg2:
+	.double 1.0
+	.double -1.0
+
+_expected:
+	.double 2.0
+	.double -2.0
+
+	start
+	.option push
+	.option norelax
+	la	a0,_arg1
+	la	a1,_arg2
+	la	a2,_expected
+	li	a3,1
+	.option pop
+
+	# Test fsgnj.d instruction.
+	fld	fa0,0(a0)
+	fld	fa1,0(a1)
+	fld	fa2,0(a2)
+	fsgnj.d	fa3,fa0,fa1
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+	fld	fa1,8(a1)
+	fld	fa2,8(a2)
+	fsgnj.d	fa3,fa0,fa1
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+
+	# Test fsgnjn.d (fneg.d) instruction.
+	fld	fa0,0(a0)
+	fld	fa1,0(a1)
+	fld	fa2,8(a2)
+	fsgnjn.d	fa3,fa0,fa1
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+	fld	fa1,8(a1)
+	fld	fa2,0(a2)
+	fsgnjn.d	fa3,fa0,fa1
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+	fld	fa0,0(a0)
+	fld	fa2,8(a2)
+	fneg.d	fa3,fa0
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+
+	# Test fsgnjx.d (fabs.d) instruction.
+	fld	fa0,0(a0)
+	fld	fa1,8(a1)
+	fld	fa2,8(a2)
+	fsgnjx.d	fa3,fa0,fa1
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+	fld	fa0,8(a0)
+	fld	fa1,8(a1)
+	fld	fa2,0(a2)
+	fsgnjx.d	fa3,fa0,fa1
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+	fld	fa0,8(a0)
+	fld	fa2,0(a2)
+	fabs.d	fa3,fa0
+	feq.d	a4,fa3,fa2
+	bne	a4,a3,test_fail
+
+test_pass:
+	pass
+
+test_fail:
+	fail
-- 
2.25.1