From: Torbjorn SVENSSON <torbjorn.svensson@foss.st.com>
To: Luis Machado <luis.machado@arm.com>, <gdb-patches@sourceware.org>
Cc: <vanekt@volny.cz>, Yvan Roux <yvan.roux@foss.st.com>
Subject: Re: [PATCH v2 4/4] gdb/arm: Use new dwarf2 function cache
Date: Tue, 29 Nov 2022 16:19:35 +0100 [thread overview]
Message-ID: <6bf733c9-ed5f-76e6-d1b8-35bf4eff9720@foss.st.com> (raw)
In-Reply-To: <bdaddc34-33c6-e744-251b-9f7980337fc3@arm.com>
Hi,
I've had a long discussion with Luis on IRC regarding the points
mentioned here, but I'll reply to the list now in order to get more eyes
on the topic.
On 2022-11-21 22:04, Luis Machado wrote:
> Hi,
>
> On 11/18/22 15:52, Torbjörn SVENSSON wrote:
>> This patch resolves the performance issue reported in pr/29738 by
>> caching the values for the stack pointers for the inner frame. By
>> doing so, the impact can be reduced to checking the state and
>> returning the appropriate value.
>>
>> Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
>> Signed-off-by: Yvan Roux <yvan.roux@foss.st.com>
>> ---
>> gdb/arm-tdep.c | 96 +++++++++++++++++++++++++++++++++-----------------
>> 1 file changed, 64 insertions(+), 32 deletions(-)
>>
>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>> index c011b2aa973..59cd0964d96 100644
>> --- a/gdb/arm-tdep.c
>> +++ b/gdb/arm-tdep.c
>> @@ -3953,6 +3953,18 @@ struct frame_base arm_normal_base = {
>> arm_normal_frame_base
>> };
>> +struct arm_dwarf2_prev_register_cache
>> +{
>> + /* Cached value of the coresponding stack pointer for the inner
>> frame. */
>
> coresponding -> corresponding
>
>> + CORE_ADDR sp;
>> + CORE_ADDR msp;
>> + CORE_ADDR msp_s;
>> + CORE_ADDR msp_ns;
>> + CORE_ADDR psp;
>> + CORE_ADDR psp_s;
>> + CORE_ADDR psp_ns;
>> +};
>> +
>
> Given SP is the cfa, do we need to cache it here?
As I said off-list, it's not the value of sp, msp etc, it's the value of
the inner frame, so what is actually "cached" here is basically the
state of the frame, not the values.
The cache could be simplified in a few ways, but before doing the
polishing, I would like to know if it's an acceptable way to implement
the fix for the performance issue.
>
>> static struct value *
>> arm_dwarf2_prev_register (frame_info_ptr this_frame, void **this_cache,
>> int regnum)
>> @@ -3961,6 +3973,48 @@ arm_dwarf2_prev_register (frame_info_ptr
>> this_frame, void **this_cache,
>> arm_gdbarch_tdep *tdep = gdbarch_tdep<arm_gdbarch_tdep> (gdbarch);
>> CORE_ADDR lr;
>> ULONGEST cpsr;
>> + struct arm_dwarf2_prev_register_cache *cache
>> + = (struct arm_dwarf2_prev_register_cache *)
>> dwarf2_frame_get_fn_data (
>> + this_frame, this_cache, arm_dwarf2_prev_register);
>> +
>> + if (!cache)
>> + {
>> + const unsigned int size = sizeof (struct
>> arm_dwarf2_prev_register_cache);
>> + cache = (struct arm_dwarf2_prev_register_cache *)
>> + dwarf2_frame_allocate_fn_data (this_frame, this_cache,
>> + arm_dwarf2_prev_register, size);
>> +
>> + if (tdep->have_sec_ext)
>> + {
>> + cache->sp
>> + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
>
> We fetch ARM_SP_REGNUM in both legs of the conditional. How about moving
> it outside of the conditional blocks?
Sure. Before doing more here, I would like to get the agreement that
this is a good approach to the problem.
>> +
>> + cache->msp_s
>> + = get_frame_register_unsigned (this_frame,
>> + tdep->m_profile_msp_s_regnum);
>> + cache->msp_ns
>> + = get_frame_register_unsigned (this_frame,
>> + tdep->m_profile_msp_ns_regnum);
>> + cache->psp_s
>> + = get_frame_register_unsigned (this_frame,
>> + tdep->m_profile_psp_s_regnum);
>> + cache->psp_ns
>> + = get_frame_register_unsigned (this_frame,
>> + tdep->m_profile_psp_ns_regnum);
>> + }
>> + else if (tdep->is_m)
>> + {
>> + cache->sp
>> + = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
>> +
>> + cache->msp
>> + = get_frame_register_unsigned (this_frame,
>> + tdep->m_profile_msp_regnum);
>> + cache->psp
>> + = get_frame_register_unsigned (this_frame,
>> + tdep->m_profile_psp_regnum);
>> + }
>> + }
>> if (regnum == ARM_PC_REGNUM)
>> {
>> @@ -4000,33 +4054,18 @@ arm_dwarf2_prev_register (frame_info_ptr
>> this_frame, void **this_cache,
>> if (tdep->have_sec_ext)
>> {
>> - CORE_ADDR sp
>> - = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
>> - CORE_ADDR msp_s
>> - = get_frame_register_unsigned (this_frame,
>> - tdep->m_profile_msp_s_regnum);
>> - CORE_ADDR msp_ns
>> - = get_frame_register_unsigned (this_frame,
>> - tdep->m_profile_msp_ns_regnum);
>> - CORE_ADDR psp_s
>> - = get_frame_register_unsigned (this_frame,
>> - tdep->m_profile_psp_s_regnum);
>> - CORE_ADDR psp_ns
>> - = get_frame_register_unsigned (this_frame,
>> - tdep->m_profile_psp_ns_regnum);
>> -
>> bool is_msp = (regnum == tdep->m_profile_msp_regnum)
>> - && (msp_s == sp || msp_ns == sp);
>> + && (cache->msp_s == cache->sp || cache->msp_ns == cache->sp);
>> bool is_msp_s = (regnum == tdep->m_profile_msp_s_regnum)
>> - && (msp_s == sp);
>> + && (cache->msp_s == cache->sp);
>> bool is_msp_ns = (regnum == tdep->m_profile_msp_ns_regnum)
>> - && (msp_ns == sp);
>> + && (cache->msp_ns == cache->sp);
>> bool is_psp = (regnum == tdep->m_profile_psp_regnum)
>> - && (psp_s == sp || psp_ns == sp);
>> + && (cache->psp_s == cache->sp || cache->psp_ns == cache->sp);
>> bool is_psp_s = (regnum == tdep->m_profile_psp_s_regnum)
>> - && (psp_s == sp);
>> + && (cache->psp_s == cache->sp);
>> bool is_psp_ns = (regnum == tdep->m_profile_psp_ns_regnum)
>> - && (psp_ns == sp);
>> + && (cache->psp_ns == cache->sp);
>> override_with_sp_value = is_msp || is_msp_s || is_msp_ns
>> || is_psp || is_psp_s || is_psp_ns;
>> @@ -4034,17 +4073,10 @@ arm_dwarf2_prev_register (frame_info_ptr
>> this_frame, void **this_cache,
>> }
>> else if (tdep->is_m)
>> {
>> - CORE_ADDR sp
>> - = get_frame_register_unsigned (this_frame, ARM_SP_REGNUM);
>> - CORE_ADDR msp
>> - = get_frame_register_unsigned (this_frame,
>> - tdep->m_profile_msp_regnum);
>> - CORE_ADDR psp
>> - = get_frame_register_unsigned (this_frame,
>> - tdep->m_profile_psp_regnum);
>> -
>> - bool is_msp = (regnum == tdep->m_profile_msp_regnum) && (sp ==
>> msp);
>> - bool is_psp = (regnum == tdep->m_profile_psp_regnum) && (sp ==
>> psp);
>> + bool is_msp = (regnum == tdep->m_profile_msp_regnum)
>> + && (cache->sp == cache->msp);
>> + bool is_psp = (regnum == tdep->m_profile_psp_regnum)
>> + && (cache->sp == cache->psp);
>> override_with_sp_value = is_msp || is_psp;
>> }
>
> As we've discussed off-list, I think we can reduce the number of
> get_frame_register_unsigned calls we do for each call to
> arm_dwarf2_prev_register by using some conditionals.
Likely, but let's focus on the dwarf2 part of the patch first and do the
polishing after, okay?
Kind regards,
Torbjörn
prev parent reply other threads:[~2022-11-29 15:19 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-18 15:52 [PATCH 0/4] v2 gdb/arm: Fixes for Cortex-M stack unwinding Torbjörn SVENSSON
2022-11-18 15:52 ` [PATCH v2 1/4] gdb/arm: Update active msp/psp when switching stack Torbjörn SVENSSON
2022-11-21 14:04 ` Luis Machado
2022-11-18 15:52 ` [PATCH v2 2/4] gdb/arm: Ensure that stack pointers are in sync Torbjörn SVENSSON
2022-11-21 14:04 ` Luis Machado
2022-11-18 15:52 ` [PATCH v2 3/4] gdb: dwarf2 generic implementation for caching function data Torbjörn SVENSSON
2022-11-18 16:01 ` Torbjorn SVENSSON
2022-12-20 21:04 ` Tom Tromey
2022-11-21 21:16 ` Luis Machado
2022-11-29 15:19 ` Torbjorn SVENSSON
2022-11-29 16:24 ` Tomas Vanek
2022-11-30 10:16 ` Torbjorn SVENSSON
2022-11-30 10:19 ` Luis Machado
2022-12-08 1:11 ` Luis Machado
2022-12-19 19:28 ` [PING] " Torbjorn SVENSSON
2022-12-20 21:02 ` Tom Tromey
2022-12-28 16:16 ` Torbjorn SVENSSON
2023-01-05 20:53 ` Torbjorn SVENSSON
2023-01-14 6:54 ` Joel Brobecker
2023-01-18 18:47 ` Tom Tromey
2023-01-19 10:31 ` Torbjorn SVENSSON
2022-11-18 15:52 ` [PATCH v2 4/4] gdb/arm: Use new dwarf2 function cache Torbjörn SVENSSON
2022-11-21 21:04 ` Luis Machado
2022-11-29 15:19 ` Torbjorn SVENSSON [this message]
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