From: Luis Machado <luis.machado@arm.com>
To: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Cc: gdb-patches@sourceware.org
Subject: Re: [PATCH v4 14/16] [gdb/aarch64] sme: Core file support for Linux
Date: Wed, 30 Aug 2023 11:28:13 +0100 [thread overview]
Message-ID: <7df51262-d537-70c3-9d6d-0f47e26ae3c2@arm.com> (raw)
In-Reply-To: <87r0nqn1cu.fsf@linaro.org>
On 8/26/23 00:33, Thiago Jung Bauermann wrote:
>
> Hello Luis,
>
> Just one minor comment:
>
> Luis Machado <luis.machado@arm.com> writes:
>
>> +/* Collect an inactive SVE register set state. This is equivalent to a
>> + fpsimd layout.
>> +
>> + Collect the data from REGCACHE to BUF, using the register
>> + map in REGSET. */
>> +
>> +static void
>> +collect_inactive_sve_regset (const struct regcache *regcache,
>> + void *buf, size_t size, int vg_regnum)
>> +{
>> + gdb_byte *header = (gdb_byte *) buf;
>> + struct gdbarch *gdbarch = regcache->arch ();
>> + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
>> +
>> + gdb_assert (buf != nullptr);
>> + gdb_assert (size >= SVE_CORE_DUMMY_SIZE);
>> +
>> + /* Zero out everything first. */
>> + memset ((gdb_byte *) buf, 0, SVE_CORE_DUMMY_SIZE);
>> +
>> + /* BUF starts with a SVE header prior to the register dump. */
>> +
>> + /* Dump the default size of an empty SVE payload. */
>> + uint32_t real_size = SVE_CORE_DUMMY_SIZE;
>> + store_unsigned_integer (header + SVE_HEADER_SIZE_OFFSET,
>> + SVE_HEADER_SIZE_LENGTH, byte_order, real_size);
>> +
>> + /* Dump a dummy max size. */
>> + uint32_t max_size = SVE_CORE_DUMMY_MAX_SIZE;
>> + store_unsigned_integer (header + SVE_HEADER_MAX_SIZE_OFFSET,
>> + SVE_HEADER_MAX_SIZE_LENGTH, byte_order, max_size);
>> +
>> + /* Dump the vector length. */
>> + ULONGEST vg = 0;
>> + regcache->raw_collect (vg_regnum, &vg);
>> + uint16_t vl = sve_vl_from_vg (vg);
>> + store_unsigned_integer (header + SVE_HEADER_VL_OFFSET, SVE_HEADER_VL_LENGTH,
>> + byte_order, vl);
>> +
>> + /* Dump the standard maximum vector length. */
>> + uint16_t max_vl = SVE_CORE_DUMMY_MAX_VL;
>> + store_unsigned_integer (header + SVE_HEADER_MAX_VL_OFFSET,
>> + SVE_HEADER_MAX_VL_LENGTH, byte_order,
>> + max_vl);
>> +
>> + /* The rest of the fields are zero. */
>> + uint16_t flags = SVE_CORE_DUMMY_FLAGS;
>> + store_unsigned_integer (header + SVE_HEADER_FLAGS_OFFSET,
>> + SVE_HEADER_FLAGS_LENGTH, byte_order,
>> + flags);
>> + uint16_t reserved = SVE_CORE_DUMMY_RESERVED;
>> + store_unsigned_integer (header + SVE_HEADER_RESERVED_OFFSET,
>> + SVE_HEADER_RESERVED_LENGTH, byte_order, reserved);
>> +
>> + /* We are done with the header part of it. Now dump the register state
>> + in the FPSIMD format. */
>> +
>> + /* Dump the first 128 bits of each of the Z registers. */
>> + header += AARCH64_SVE_CONTEXT_REGS_OFFSET;
>> + for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++)
>> + regcache->raw_collect_part (AARCH64_SVE_Z0_REGNUM + i, 0, V_REGISTER_SIZE,
>> + header + V_REGISTER_SIZE * i);
>> +
>> + /* Dump FPSR and FPCR. */
>> + header += 32 * V_REGISTER_SIZE;
>> + regcache->raw_collect (AARCH64_FPSR_REGNUM, header);
>> + header += 4;
>> + regcache->raw_collect (AARCH64_FPCR_REGNUM, header);
>> +
>> + /* Dump two reserved empty fields of 4 bytes. */
>> + header += 8;
>
> Sorry, I missed this on my previous review: the header adjustment
> position above looks a bit strange. Shouldn't the two reserved fields
> come right after FPCR, instead of having a 4-byte gap?
>
Yes indeed. I think I changed the code around and eventually added the 4 byte increment to the header pointer.
Fixed now by passing header + offset when collecting FPCR and then incrementing 8 bytes correctly.
>> + memset (header, 0, 8);
>> +
>> + /* We should have a FPSIMD-formatted register dump now. */
>> +}
>
next prev parent reply other threads:[~2023-08-30 10:28 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-22 11:21 [PATCH v4 00/16] SME support for AArch64 gdb/gdbserver on Linux Luis Machado
2023-08-22 11:21 ` [PATCH v4 01/16] [gdb/aarch64] Fix register fetch/store order for native AArch64 Linux Luis Machado
2023-08-22 11:21 ` [PATCH v4 02/16] [gdb/aarch64] refactor: Rename SVE-specific files Luis Machado
2023-08-22 11:21 ` [PATCH v4 03/16] [gdb/gdbserver] refactor: Simplify SVE interface to read/write registers Luis Machado
2023-08-22 11:21 ` [PATCH v4 04/16] [gdb/aarch64] sve: Fix return command when using V registers in a SVE-enabled target Luis Machado
2023-08-22 11:21 ` [PATCH v4 05/16] [gdb/aarch64] sme: Enable SME registers and pseudo-registers Luis Machado
2023-08-22 11:21 ` [PATCH v4 06/16] [gdbserver/aarch64] refactor: Adjust expedited registers dynamically Luis Machado
2023-08-22 11:21 ` [PATCH v4 07/16] [gdbserver/aarch64] sme: Add support for SME Luis Machado
2023-08-27 1:32 ` Thiago Jung Bauermann
2023-08-30 10:37 ` Luis Machado
2023-08-22 11:21 ` [PATCH v4 08/16] [gdb/aarch64] sve: Fix signal frame z/v register restore Luis Machado
2023-08-22 11:21 ` [PATCH v4 09/16] [gdb/aarch64] sme: Signal frame support Luis Machado
2023-08-22 11:21 ` [PATCH v4 10/16] [gdb/aarch64] sme: Fixup sigframe gdbarch when vg/svg changes Luis Machado
2023-08-22 11:21 ` [PATCH v4 11/16] [gdb/aarch64] sme: Support TPIDR2 signal frame context Luis Machado
2023-08-22 11:21 ` [PATCH v4 12/16] [gdb/generic] corefile/bug: Use thread-specific gdbarch when dumping register state to core files Luis Machado
2023-08-22 11:21 ` [PATCH v4 13/16] [gdb/generic] corefile/bug: Fixup (gcore) core file target description reading order Luis Machado
2023-08-22 11:21 ` [PATCH v4 14/16] [gdb/aarch64] sme: Core file support for Linux Luis Machado
2023-08-25 23:33 ` Thiago Jung Bauermann
2023-08-30 10:28 ` Luis Machado [this message]
2023-08-22 11:21 ` [PATCH v4 15/16] [gdb/testsuite] sme: Add SVE/SME testcases Luis Machado
2023-08-22 11:21 ` [PATCH v4 16/16] [gdb/docs] sme: Document SME registers and features Luis Machado
2023-08-22 11:31 ` Eli Zaretskii
2023-08-22 11:39 ` Luis Machado
2023-08-22 11:56 ` Luis Machado
2023-08-22 12:37 ` Eli Zaretskii
2023-08-25 23:35 ` [PATCH v4 00/16] SME support for AArch64 gdb/gdbserver on Linux Thiago Jung Bauermann
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