* [PATCH] sim: riscv: Fix confusion with c.jal vs. c.addiw
@ 2024-04-15 8:36 Bernd Edlinger
2024-04-15 8:56 ` Andrew Burgess
0 siblings, 1 reply; 3+ messages in thread
From: Bernd Edlinger @ 2024-04-15 8:36 UTC (permalink / raw)
To: gdb-patches, Andrew Burgess
There was apparently a confusion which cpu model uses
compressed JAL and which ADDIW. Fixed that in execute_c,
case MATCH_C_JAL | MATCH_C_ADDIW.
Fixes 3224e32fb84f ("sim: riscv: Add support for compressed integer instructions")
---
sim/riscv/sim-main.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index adff99921c6..9fd2cc70657 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1016,9 +1016,9 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
break;
case MATCH_C_JAL | MATCH_C_ADDIW:
- /* JAL and ADDIW have the same mask but are only available on RV64 or
- RV32 respectively. */
- if (RISCV_XLEN (cpu) == 64)
+ /* JAL and ADDIW have the same mask but are only available on RV32 or
+ RV64 respectively. */
+ if (RISCV_XLEN (cpu) == 32)
{
imm = EXTRACT_CJTYPE_IMM (iw);
TRACE_INSN (cpu, "c.jal %" PRIxTW,
@@ -1027,7 +1027,7 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
pc = riscv_cpu->pc + imm;
TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
}
- else if (RISCV_XLEN (cpu) == 32)
+ else if (RISCV_XLEN (cpu) == 64)
{
imm = EXTRACT_CITYPE_IMM (iw);
TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW,
--
2.39.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] sim: riscv: Fix confusion with c.jal vs. c.addiw
2024-04-15 8:36 [PATCH] sim: riscv: Fix confusion with c.jal vs. c.addiw Bernd Edlinger
@ 2024-04-15 8:56 ` Andrew Burgess
2024-04-15 9:05 ` Bernd Edlinger
0 siblings, 1 reply; 3+ messages in thread
From: Andrew Burgess @ 2024-04-15 8:56 UTC (permalink / raw)
To: Bernd Edlinger, gdb-patches
Bernd Edlinger <bernd.edlinger@hotmail.de> writes:
> There was apparently a confusion which cpu model uses
> compressed JAL and which ADDIW. Fixed that in execute_c,
> case MATCH_C_JAL | MATCH_C_ADDIW.
>
> Fixes 3224e32fb84f ("sim: riscv: Add support for compressed integer
> instructions")
Thanks for splitting this off. This looks good.
Approved-By: Andrew Burgess <aburgess@redhat.com>
Thanks,
Andrew
> ---
> sim/riscv/sim-main.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
> index adff99921c6..9fd2cc70657 100644
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
> @@ -1016,9 +1016,9 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
> TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
> break;
> case MATCH_C_JAL | MATCH_C_ADDIW:
> - /* JAL and ADDIW have the same mask but are only available on RV64 or
> - RV32 respectively. */
> - if (RISCV_XLEN (cpu) == 64)
> + /* JAL and ADDIW have the same mask but are only available on RV32 or
> + RV64 respectively. */
> + if (RISCV_XLEN (cpu) == 32)
> {
> imm = EXTRACT_CJTYPE_IMM (iw);
> TRACE_INSN (cpu, "c.jal %" PRIxTW,
> @@ -1027,7 +1027,7 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
> pc = riscv_cpu->pc + imm;
> TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
> }
> - else if (RISCV_XLEN (cpu) == 32)
> + else if (RISCV_XLEN (cpu) == 64)
> {
> imm = EXTRACT_CITYPE_IMM (iw);
> TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW,
> --
> 2.39.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] sim: riscv: Fix confusion with c.jal vs. c.addiw
2024-04-15 8:56 ` Andrew Burgess
@ 2024-04-15 9:05 ` Bernd Edlinger
0 siblings, 0 replies; 3+ messages in thread
From: Bernd Edlinger @ 2024-04-15 9:05 UTC (permalink / raw)
To: Andrew Burgess, gdb-patches
On 4/15/24 10:56, Andrew Burgess wrote:
> Bernd Edlinger <bernd.edlinger@hotmail.de> writes:
>
>> There was apparently a confusion which cpu model uses
>> compressed JAL and which ADDIW. Fixed that in execute_c,
>> case MATCH_C_JAL | MATCH_C_ADDIW.
>>
>> Fixes 3224e32fb84f ("sim: riscv: Add support for compressed integer
>> instructions")
>
> Thanks for splitting this off. This looks good.
>
> Approved-By: Andrew Burgess <aburgess@redhat.com>
>
Okay, no problem. Pushed.
Thanks
Bernd.
> Thanks,
> Andrew
>
>
>> ---
>> sim/riscv/sim-main.c | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
>> index adff99921c6..9fd2cc70657 100644
>> --- a/sim/riscv/sim-main.c
>> +++ b/sim/riscv/sim-main.c
>> @@ -1016,9 +1016,9 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>> TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
>> break;
>> case MATCH_C_JAL | MATCH_C_ADDIW:
>> - /* JAL and ADDIW have the same mask but are only available on RV64 or
>> - RV32 respectively. */
>> - if (RISCV_XLEN (cpu) == 64)
>> + /* JAL and ADDIW have the same mask but are only available on RV32 or
>> + RV64 respectively. */
>> + if (RISCV_XLEN (cpu) == 32)
>> {
>> imm = EXTRACT_CJTYPE_IMM (iw);
>> TRACE_INSN (cpu, "c.jal %" PRIxTW,
>> @@ -1027,7 +1027,7 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>> pc = riscv_cpu->pc + imm;
>> TRACE_BRANCH (cpu, "to %#" PRIxTW, pc);
>> }
>> - else if (RISCV_XLEN (cpu) == 32)
>> + else if (RISCV_XLEN (cpu) == 64)
>> {
>> imm = EXTRACT_CITYPE_IMM (iw);
>> TRACE_INSN (cpu, "c.addiw %s, %s, %#" PRIxTW "; // %s += %#" PRIxTW,
>> --
>> 2.39.2
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-04-15 8:36 [PATCH] sim: riscv: Fix confusion with c.jal vs. c.addiw Bernd Edlinger
2024-04-15 8:56 ` Andrew Burgess
2024-04-15 9:05 ` Bernd Edlinger
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