RE: [PATCH v5 0/2] sim: riscv: Compressed instruction simulation

[Jaydeep Patil <Jaydeep.Patil@imgtec.com>]

Hi Mike, Andrew,

Could you please review this patch?

Regards,
Jaydeep


-----Original Message-----
From: Jaydeep Patil <Jaydeep.Patil@imgtec.com> 
Sent: Friday, December 22, 2023 10:57 AM
To: gdb-patches@sourceware.org
Cc: aburgess@redhat.com; vapier@gentoo.org; Joseph Faulls <Joseph.Faulls@imgtec.com>; Bhushan Attarde <Bhushan.Attarde@imgtec.com>; Jaydeep Patil <Jaydeep.Patil@imgtec.com>
Subject: [PATCH v5 0/2] sim: riscv: Compressed instruction simulation

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From: Jaydeep Patil <jaydeep.patil@imgtec.com>

Hi Mike, Andrew,

Addressed review comments.
 - Simplified the checking for C extension
 - Simplified the .exp file for tests. Options moved to individual .s files.

Jaydeep Patil (2):
  [sim/riscv] Fix crash during instruction decoding
  [sim/riscv] Add support for compressed integer instructions

 opcodes/riscv-dis.c             |   2 +-
 sim/riscv/model_list.def        |   9 +
 sim/riscv/sim-main.c            | 339 ++++++++++++++++++++++++++++++--
 sim/testsuite/riscv/allinsn.exp |   2 +-
 sim/testsuite/riscv/c-ext.s     |  95 +++++++++
 sim/testsuite/riscv/jalr.s      |   2 +-
 sim/testsuite/riscv/m-ext.s     |   2 +-
 sim/testsuite/riscv/pass.s      |   2 +-
 8 files changed, 437 insertions(+), 16 deletions(-)  create mode 100644 sim/testsuite/riscv/c-ext.s

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2.25.1