From: Mike Frysinger <vapier@gentoo.org>
To: Jaydeep Patil <Jaydeep.Patil@imgtec.com>
Cc: "gdb-patches@sourceware.org" <gdb-patches@sourceware.org>,
"aburgess@redhat.com" <aburgess@redhat.com>,
Joseph Faulls <Joseph.Faulls@imgtec.com>,
Bhushan Attarde <Bhushan.Attarde@imgtec.com>
Subject: Re: [PATCH v5 0/2] sim: riscv: Compressed instruction simulation
Date: Fri, 5 Jan 2024 00:41:54 -0500 [thread overview]
Message-ID: <ZZeWokzu28MJKXdH@vapier> (raw)
In-Reply-To: <CWXP265MB5321C9B3ADB821449DC039568C67A@CWXP265MB5321.GBRP265.PROD.OUTLOOK.COM>
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On 04 Jan 2024 04:24, Jaydeep Patil wrote:
> Could you please review this patch?
i was mostly being lazy and waiting on the first one to merge. i assume
Andrew needs to sign off on that as i don't usually touch opcodes/.
also, can you stick to normal "tag:" commit summary style, not "[tag]" ?
git treats "[...]" text specially and likes to discard it in some cases
which makes merging your patches difficult. so use "sim: riscv:", not
"[sim/riscv]".
-mike
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prev parent reply other threads:[~2024-01-05 5:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-22 5:26 jaydeep.patil
2023-12-22 5:26 ` [PATCH v5 1/2] [sim/riscv] Fix crash during instruction decoding jaydeep.patil
2024-01-10 10:22 ` Andrew Burgess
2024-01-10 11:34 ` [EXTERNAL] " Jaydeep Patil
2023-12-22 5:26 ` [PATCH v5 2/2] [sim/riscv] Add support for compressed integer instructions jaydeep.patil
2024-01-04 4:24 ` [PATCH v5 0/2] sim: riscv: Compressed instruction simulation Jaydeep Patil
2024-01-05 5:41 ` Mike Frysinger [this message]
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