RE: [EXTERNAL] Re: [PATCH v5 1/2] [sim/riscv] Fix crash during instruction decoding

[Jaydeep Patil <Jaydeep.Patil@imgtec.com>]

<aburgess@redhat.com> writes:

>This second commit talks about treating a NULL as actually meaning match_always.  I've not dug into this beyond looking at those commits, but that second commit does include some code similar to yours, except in that case they've gone with something like:
>
>  if (op->match_func && !(op->match_func) (op, word))
>    continue;
>
>I'd like to see a commit message that references this history, and explains why this commit does something different.
>
>Also, does your change indicate that there exists an instruction encoding which, if we try to disassemble it, will cause the disassembler to segfault?  That would be a good candidate for making into a test, maybe in the gas testsuite?
>

Looking at the riscv_opcodes[] table in opcodes/riscv-opc.c, we don't need to modify opcodes/riscv-dis.c.
The match_never() has been replaced with NULL for INSN_MACRO types. Thus disassembler will never segfault because of following code:

@@ -818,7 +818,7 @@ riscv_disassemble_insn (bfd_vma memaddr,
	  if (op->pinfo == INSN_MACRO)
	    continue;

The segfault happens only in step_once() of sim/riscv/sim-main.c.

Regards,
Jaydeep