* Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
@ 2022-04-12 4:47 Carl Love
2022-04-18 16:20 ` will schmidt
0 siblings, 1 reply; 6+ messages in thread
From: Carl Love @ 2022-04-12 4:47 UTC (permalink / raw)
To: gdb-patches, Ulrich Weigand, cel; +Cc: Will Schmidt, Rogerio Alves, tromey
GDB maintainers:
The floating point format changed recently resulting in a large number
of regresssion errors on Powerpc for tests gdb.arch/altivec-regs.exp
and gdb.arch/vsx-regs.exp. The following patch updates the expected
floating point values. It also makes an additional change in the vsx-
regs.exp test to inialize both double words. This was needed on BE to
fix a regression error on the expected value of vs0 where word[1] was
initially not zero.
The patch has been run on Power 10, Power 8LE, and Power 8BE to verify
the patch.
Please let me know if this patch is acceptable for mainline. Thanks.
Carl Love
-----------------------------------------------------------------------
Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
The format for printing the floating point values was changed by commit:
commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e
Author: Tom Tromey <tromey@adacore.com>
Date: Thu Feb 17 13:43:59 2022 -0700
Change how "print/x" displays floating-point value
Currently, "print/x" will display a floating-point value by first
casting it to an integer type. This yields weird results like:
(gdb) print/x 1.5
$1 = 0x1
...
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242
The above change results in 417 regression test failures since the expected
Power vector register output no longer match. This patch updates the
expected floating point register prints to the new values for both big
endian and little endian systems. Additionally, the initialization of
the vs registers is updated in vsx-regs.exp to inialize both double words.
The patch has been tested on Power 10, Power 8 LE and Power 8 BE.
---
gdb/testsuite/gdb.arch/altivec-regs.exp | 8 ++++----
gdb/testsuite/gdb.arch/vsx-regs.exp | 27 +++++++++++++------------
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/gdb/testsuite/gdb.arch/altivec-regs.exp b/gdb/testsuite/gdb.arch/altivec-regs.exp
index 7bae979b984..d4c13afa8a1 100644
--- a/gdb/testsuite/gdb.arch/altivec-regs.exp
+++ b/gdb/testsuite/gdb.arch/altivec-regs.exp
@@ -84,9 +84,9 @@ set endianness [get_endianness]
# b) the register read (below) also works.
if {$endianness == "big"} {
-set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
} else {
-set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
+set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
}
for {set i 0} {$i < 32} {incr i 1} {
@@ -104,9 +104,9 @@ gdb_test "info reg vscr" "vscr.*0x1\[ \t\]+1" "info reg vscr"
# the way gdb works.
if {$endianness == "big"} {
- set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
+ set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
} else {
- set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
+ set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
}
for {set i 0} {$i < 32} {incr i 1} {
diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp
index 8b3841362fe..7c2ddaa92c3 100644
--- a/gdb/testsuite/gdb.arch/vsx-regs.exp
+++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
@@ -61,29 +61,29 @@ set endianness [get_endianness]
# Data sets used throughout the test
if {$endianness == "big"} {
- set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
+ set vector_register1 ".float128 = 0x3ff4cccccccccccd0000000000000000, uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x3ff4cccccccccccd, 0x0., v4_float = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
- set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+ set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
- set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
+ set vector_register2 ".float128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
- set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
+ set vector_register2_vr ".uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
- set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+ set vector_register3 ".float128 = 0x1000000010000000100000001, uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
- set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+ set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
} else {
- set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
+ set vector_register1 ".float128 = 0x3ff4cccccccccccd0000000000000000, uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x3ff4cccccccccccd., v4_float = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
- set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
+ set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
- set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
+ set vector_register2 ".float128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
- set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
+ set vector_register2_vr ".uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
- set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
+ set vector_register3 ".float128 = 0x1000000010000000100000001, uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
- set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
+ set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
}
set float_register ".raw 0xdeadbeefdeadbeef."
@@ -96,9 +96,10 @@ set float_register ".raw 0xdeadbeefdeadbeef."
# initialize the doubleword1 portions before we run our tests against
# values currently in those registers.
-# 0: Initialize the (doubleword 1) portion of the VS0-VS31 registers.
+# 0: Initialize the (doubleword 0 and 1) portion of the VS0-VS31 registers.
for {set i 0} {$i < 32} {incr i 1} {
gdb_test_no_output "set \$vs$i.v2_double\[0\] = 0"
+ gdb_test_no_output "set \$vs$i.v2_double\[1\] = 0"
}
# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
--
2.31.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
2022-04-12 4:47 Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp Carl Love
@ 2022-04-18 16:20 ` will schmidt
2022-04-18 20:04 ` [PATCH V2] " Carl Love
0 siblings, 1 reply; 6+ messages in thread
From: will schmidt @ 2022-04-18 16:20 UTC (permalink / raw)
To: Carl Love, gdb-patches, Ulrich Weigand; +Cc: Rogerio Alves, tromey
On Mon, 2022-04-11 at 21:47 -0700, Carl Love wrote:
> GDB maintainers:
>
Hi.
The "Powerpc" in the subject should be "PowerPC". Maybe should
actually be rs6000, dunno.. :-)
> The floating point format changed recently resulting in a large number
> of regresssion errors on Powerpc for tests gdb.arch/altivec-regs.exp
> and gdb.arch/vsx-regs.exp. The following patch updates the expected
> floating point values. It also makes an additional change in the vsx-
> regs.exp test to inialize both double words. This was needed on BE to
> fix a regression error on the expected value of vs0 where word[1] was
> initially not zero.
>
> The patch has been run on Power 10, Power 8LE, and Power 8BE to verify
> the patch.
>
> Please let me know if this patch is acceptable for mainline. Thanks.
>
> Carl Love
>
>
> -----------------------------------------------------------------------
> Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
>
> The format for printing the floating point values was changed by commit:
>
> commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e
> Author: Tom Tromey <tromey@adacore.com>
> Date: Thu Feb 17 13:43:59 2022 -0700
>
> Change how "print/x" displays floating-point value
>
> Currently, "print/x" will display a floating-point value by first
> casting it to an integer type. This yields weird results like:
>
> (gdb) print/x 1.5
> $1 = 0x1
> ...
> Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242
>
> The above change results in 417 regression test failures since the expected
> Power vector register output no longer match. This patch updates the
> expected floating point register prints to the new values for both big
Not "new values" , same values printed in a hexadecimal format.
> endian and little endian systems. Additionally, the initialization of
> the vs registers is updated in vsx-regs.exp to inialize both double words.
Ok.
>
> The patch has been tested on Power 10, Power 8 LE and Power 8 BE.
ok
> ---
> gdb/testsuite/gdb.arch/altivec-regs.exp | 8 ++++----
> gdb/testsuite/gdb.arch/vsx-regs.exp | 27 +++++++++++++------------
> 2 files changed, 18 insertions(+), 17 deletions(-)
>
> diff --git a/gdb/testsuite/gdb.arch/altivec-regs.exp b/gdb/testsuite/gdb.arch/altivec-regs.exp
> index 7bae979b984..d4c13afa8a1 100644
> --- a/gdb/testsuite/gdb.arch/altivec-regs.exp
> +++ b/gdb/testsuite/gdb.arch/altivec-regs.exp
> @@ -84,9 +84,9 @@ set endianness [get_endianness]
> # b) the register read (below) also works.
>
> if {$endianness == "big"} {
> -set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
> +set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
Ok.
> } else {
> -set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
> +set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
> }
ok
>
> for {set i 0} {$i < 32} {incr i 1} {
> @@ -104,9 +104,9 @@ gdb_test "info reg vscr" "vscr.*0x1\[ \t\]+1" "info reg vscr"
> # the way gdb works.
>
> if {$endianness == "big"} {
> - set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
> + set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
> } else {
> - set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
> + set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
> }
Just an indentation change? If there is a value change, i'm not
seeing it.
>
> for {set i 0} {$i < 32} {incr i 1} {
> diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp
> index 8b3841362fe..7c2ddaa92c3 100644
> --- a/gdb/testsuite/gdb.arch/vsx-regs.exp
> +++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
> @@ -61,29 +61,29 @@ set endianness [get_endianness]
> # Data sets used throughout the test
>
> if {$endianness == "big"} {
> - set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
> + set vector_register1 ".float128 = 0x3ff4cccccccccccd0000000000000000, uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x3ff4cccccccccccd, 0x0., v4_float = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
>
It looks like this is adding the float128 field to the output. That
seems to be a good fix, and worth a mention in the description.
> - set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
> + set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
>
> - set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
> + set vector_register2 ".float128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
>
> - set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
> + set vector_register2_vr ".uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
>
> - set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
> + set vector_register3 ".float128 = 0x1000000010000000100000001, uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
>
> - set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
> + set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
> } else {
> - set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
> + set vector_register1 ".float128 = 0x3ff4cccccccccccd0000000000000000, uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x3ff4cccccccccccd., v4_float = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
>
> - set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
> + set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
>
> - set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
> + set vector_register2 ".float128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
>
> - set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
> + set vector_register2_vr ".uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
>
> - set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
> + set vector_register3 ".float128 = 0x1000000010000000100000001, uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
>
> - set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
> + set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
> }
>
> set float_register ".raw 0xdeadbeefdeadbeef."
> @@ -96,9 +96,10 @@ set float_register ".raw 0xdeadbeefdeadbeef."
> # initialize the doubleword1 portions before we run our tests against
> # values currently in those registers.
>
> -# 0: Initialize the (doubleword 1) portion of the VS0-VS31 registers.
> +# 0: Initialize the (doubleword 0 and 1) portion of the VS0-VS31 registers.
> for {set i 0} {$i < 32} {incr i 1} {
> gdb_test_no_output "set \$vs$i.v2_double\[0\] = 0"
> + gdb_test_no_output "set \$vs$i.v2_double\[1\] = 0"
> }
The comment before this piece of code should also be updated.
It is currently:
# Since dl_main uses some VS* registers, and
per inspection
their values are
# no longer zero when our test reaches main(), we need to
explicitly
# initialize the doubleword1 portions before we run our tests
against
# values currently in those registers.
Since both doublewords are now re-initialized for this test, the
reference to doubleword1 portion can be simplified to stl "we need to
explicitly initialize the VS* registers before we run..."
>
> # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V2] Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
2022-04-18 16:20 ` will schmidt
@ 2022-04-18 20:04 ` Carl Love
2022-04-22 19:50 ` [PATCH V2 Ping] " Carl Love
2022-04-26 14:28 ` [PATCH V2] " Ulrich Weigand
0 siblings, 2 replies; 6+ messages in thread
From: Carl Love @ 2022-04-18 20:04 UTC (permalink / raw)
To: will schmidt, gdb-patches, Ulrich Weigand; +Cc: Rogerio Alves, tromey, cel, cel
Will, GDB maintainers:
On Mon, 2022-04-18 at 11:20 -0500, will schmidt wrote:
> On Mon, 2022-04-11 at 21:47 -0700, Carl Love wrote:
> > GDB maintainers:
> >
>
> Hi.
> The "Powerpc" in the subject should be "PowerPC". Maybe should
> actually be rs6000, dunno.. :-)
Changed it to PowerPC.
Updated commit message to indicate the formatting fix, to say
hexadecimal format and add new float128 entry in the VSX expected
values.
Fixed up the comment in the test case as Will pointed out.
Retested the Patch on Power 10.
Please let me know if anyone sees any additional issues that need
fixing. Thanks.
Carl Love
--------------------------------------------------
PowerPC: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
The format for printing the floating point values was changed by commit:
commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e
Author: Tom Tromey <tromey@adacore.com>
Date: Thu Feb 17 13:43:59 2022 -0700
Change how "print/x" displays floating-point value
Currently, "print/x" will display a floating-point value by first
casting it to an integer type. This yields weird results like:
(gdb) print/x 1.5
$1 = 0x1
...
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242
The above change results in 417 regression test failures since the expected
Power vector register output no longer match.
This patch updates the expected Altivec floating point register prints to the
hexadecimal format for both big endian and little endian systems. The patch
also fixes a formatting isue with the decimal_vector expected value assign
statements.
The expected VSX vector_register1, vector_register1_vr, vector_register2,
vector_register2_vr are updated to include the new float128 entry.
Additionally, the initialization of the vs registers is updated in vsx-regs.exp
to inialize both double words.
The patch has been tested on Power 10, Power 8 LE and Power 8 BE.
---
PowerPC: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
The format for printing the floating point values was changed by commit:
commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e
Author: Tom Tromey <tromey@adacore.com>
Date: Thu Feb 17 13:43:59 2022 -0700
Change how "print/x" displays floating-point value
Currently, "print/x" will display a floating-point value by first
casting it to an integer type. This yields weird results like:
(gdb) print/x 1.5
$1 = 0x1
...
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242
The above change results in 417 regression test failures since the expected
Power vector register output no longer match.
This patch updates the expected Altivec floating point register prints to the
hexadecimal format for both big endian and little endian systems. The patch
also fixes a formatting isue with the decimal_vector expected value assign
statements.
The expected VSX vector_register1, vector_register1_vr, vector_register2,
vector_register2_vr variables are updated to include the new float128 entry.
Additionally, the comment in the vsx expect file about the initialization
of the vs registers is updated.
The patch has been tested on Power 10, Power 8 LE and Power 8 BE.
---
gdb/testsuite/gdb.arch/altivec-regs.exp | 8 +++----
gdb/testsuite/gdb.arch/vsx-regs.exp | 31 +++++++++++++------------
2 files changed, 20 insertions(+), 19 deletions(-)
diff --git a/gdb/testsuite/gdb.arch/altivec-regs.exp b/gdb/testsuite/gdb.arch/altivec-regs.exp
index 7bae979b984..d4c13afa8a1 100644
--- a/gdb/testsuite/gdb.arch/altivec-regs.exp
+++ b/gdb/testsuite/gdb.arch/altivec-regs.exp
@@ -84,9 +84,9 @@ set endianness [get_endianness]
# b) the register read (below) also works.
if {$endianness == "big"} {
-set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
} else {
-set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
+set vector_register ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
}
for {set i 0} {$i < 32} {incr i 1} {
@@ -104,9 +104,9 @@ gdb_test "info reg vscr" "vscr.*0x1\[ \t\]+1" "info reg vscr"
# the way gdb works.
if {$endianness == "big"} {
- set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
+ set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
} else {
- set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
+ set decimal_vector ".uint128 = 79228162532711081671548469249, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
}
for {set i 0} {$i < 32} {incr i 1} {
diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp
index 8b3841362fe..56fea796a9b 100644
--- a/gdb/testsuite/gdb.arch/vsx-regs.exp
+++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
@@ -61,29 +61,29 @@ set endianness [get_endianness]
# Data sets used throughout the test
if {$endianness == "big"} {
- set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
+ set vector_register1 ".float128 = 0x3ff4cccccccccccd0000000000000000, uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x3ff4cccccccccccd, 0x0., v4_float = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
- set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+ set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
- set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
+ set vector_register2 ".float128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
- set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
+ set vector_register2_vr ".uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
- set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+ set vector_register3 ".float128 = 0x1000000010000000100000001, uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
- set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+ set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
} else {
- set vector_register1 ".uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
+ set vector_register1 ".float128 = 0x3ff4cccccccccccd0000000000000000, uint128 = 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x3ff4cccccccccccd., v4_float = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
- set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
+ set vector_register1_vr ".uint128 = 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
- set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000, 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
+ set vector_register2 ".float128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef, 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
- set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
+ set vector_register2_vr ".uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
- set vector_register3 ".uint128 = 0x1000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
+ set vector_register3 ".float128 = 0x1000000010000000100000001, uint128 = 0x1000000010000000100000001, v2_double = .0x100000001, 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
- set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
+ set vector_register3_vr ".uint128 = 0x1000000010000000100000001, v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
}
set float_register ".raw 0xdeadbeefdeadbeef."
@@ -93,12 +93,13 @@ set float_register ".raw 0xdeadbeefdeadbeef."
# after updates to F*.
# Since dl_main uses some VS* registers, and per inspection their values are
# no longer zero when our test reaches main(), we need to explicitly
-# initialize the doubleword1 portions before we run our tests against
-# values currently in those registers.
+# initialize the VS* registers before we run our tests against the values
+# currently in those registers.
-# 0: Initialize the (doubleword 1) portion of the VS0-VS31 registers.
+# 0: Initialize the (doubleword 0 and 1) portion of the VS0-VS31 registers.
for {set i 0} {$i < 32} {incr i 1} {
gdb_test_no_output "set \$vs$i.v2_double\[0\] = 0"
+ gdb_test_no_output "set \$vs$i.v2_double\[1\] = 0"
}
# 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
--
2.31.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2 Ping] Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
2022-04-18 20:04 ` [PATCH V2] " Carl Love
@ 2022-04-22 19:50 ` Carl Love
2022-04-26 14:28 ` [PATCH V2] " Ulrich Weigand
1 sibling, 0 replies; 6+ messages in thread
From: Carl Love @ 2022-04-22 19:50 UTC (permalink / raw)
To: will schmidt, gdb-patches, Ulrich Weigand; +Cc: Rogerio Alves, tromey, cel
Will, GDB maintainers:
Just checking to see if there were any more comments? If not, is the
patch ready to commit?
Thanks.
Carl Love
On Mon, 2022-04-18 at 13:04 -0700, Carl Love wrote:
> Will, GDB maintainers:
>
> On Mon, 2022-04-18 at 11:20 -0500, will schmidt wrote:
> > On Mon, 2022-04-11 at 21:47 -0700, Carl Love wrote:
> > > GDB maintainers:
> > >
> >
> > Hi.
> > The "Powerpc" in the subject should be "PowerPC". Maybe should
> > actually be rs6000, dunno.. :-)
>
> Changed it to PowerPC.
>
> Updated commit message to indicate the formatting fix, to say
> hexadecimal format and add new float128 entry in the VSX expected
> values.
>
> Fixed up the comment in the test case as Will pointed out.
>
> Retested the Patch on Power 10.
>
> Please let me know if anyone sees any additional issues that need
> fixing. Thanks.
>
> Carl Love
> --------------------------------------------------
> PowerPC: Update expected floating point output for gdb.arch/altivec-
> regs.exp and gdb.arch/vsx-regs.exp
>
> The format for printing the floating point values was changed by
> commit:
>
> commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e
> Author: Tom Tromey <tromey@adacore.com>
> Date: Thu Feb 17 13:43:59 2022 -0700
>
> Change how "print/x" displays floating-point value
>
> Currently, "print/x" will display a floating-point value by
> first
> casting it to an integer type. This yields weird results
> like:
>
> (gdb) print/x 1.5
> $1 = 0x1
> ...
> Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242
>
> The above change results in 417 regression test failures since the
> expected
> Power vector register output no longer match.
>
> This patch updates the expected Altivec floating point register
> prints to the
> hexadecimal format for both big endian and little endian
> systems. The patch
> also fixes a formatting isue with the decimal_vector expected value
> assign
> statements.
>
> The expected VSX vector_register1, vector_register1_vr,
> vector_register2,
> vector_register2_vr are updated to include the new float128 entry.
> Additionally, the initialization of the vs registers is updated in
> vsx-regs.exp
> to inialize both double words.
>
> The patch has been tested on Power 10, Power 8 LE and Power 8 BE.
> ---
> PowerPC: Update expected floating point output for gdb.arch/altivec-
> regs.exp and gdb.arch/vsx-regs.exp
>
> The format for printing the floating point values was changed by
> commit:
>
> commit 56262a931b7ca8ee3ec9104bc7e9e0b40cf3d64e
> Author: Tom Tromey <tromey@adacore.com>
> Date: Thu Feb 17 13:43:59 2022 -0700
>
> Change how "print/x" displays floating-point value
>
> Currently, "print/x" will display a floating-point value by
> first
> casting it to an integer type. This yields weird results
> like:
>
> (gdb) print/x 1.5
> $1 = 0x1
> ...
> Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=16242
>
> The above change results in 417 regression test failures since the
> expected
> Power vector register output no longer match.
>
> This patch updates the expected Altivec floating point register
> prints to the
> hexadecimal format for both big endian and little endian
> systems. The patch
> also fixes a formatting isue with the decimal_vector expected value
> assign
> statements.
>
> The expected VSX vector_register1, vector_register1_vr,
> vector_register2,
> vector_register2_vr variables are updated to include the new float128
> entry.
> Additionally, the comment in the vsx expect file about the
> initialization
> of the vs registers is updated.
>
> The patch has been tested on Power 10, Power 8 LE and Power 8 BE.
> ---
> gdb/testsuite/gdb.arch/altivec-regs.exp | 8 +++----
> gdb/testsuite/gdb.arch/vsx-regs.exp | 31 +++++++++++++--------
> ----
> 2 files changed, 20 insertions(+), 19 deletions(-)
>
> diff --git a/gdb/testsuite/gdb.arch/altivec-regs.exp
> b/gdb/testsuite/gdb.arch/altivec-regs.exp
> index 7bae979b984..d4c13afa8a1 100644
> --- a/gdb/testsuite/gdb.arch/altivec-regs.exp
> +++ b/gdb/testsuite/gdb.arch/altivec-regs.exp
> @@ -84,9 +84,9 @@ set endianness [get_endianness]
> # b) the register read (below) also works.
>
> if {$endianness == "big"} {
> -set vector_register ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1.."
> +set vector_register ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1.."
> } else {
> -set vector_register ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
> 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0.."
> +set vector_register ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
> 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0.."
> }
>
> for {set i 0} {$i < 32} {incr i 1} {
> @@ -104,9 +104,9 @@ gdb_test "info reg vscr" "vscr.*0x1\[ \t\]+1"
> "info reg vscr"
> # the way gdb works.
>
> if {$endianness == "big"} {
> - set decimal_vector ".uint128 = 79228162532711081671548469249,
> v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1,
> 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0,
> 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
> + set decimal_vector ".uint128 = 79228162532711081671548469249,
> v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1,
> 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0,
> 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
> } else {
> - set decimal_vector ".uint128 = 79228162532711081671548469249,
> v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1,
> 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1,
> 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
> + set decimal_vector ".uint128 = 79228162532711081671548469249,
> v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1,
> 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1,
> 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0.."
> }
>
> for {set i 0} {$i < 32} {incr i 1} {
> diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp
> b/gdb/testsuite/gdb.arch/vsx-regs.exp
> index 8b3841362fe..56fea796a9b 100644
> --- a/gdb/testsuite/gdb.arch/vsx-regs.exp
> +++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
> @@ -61,29 +61,29 @@ set endianness [get_endianness]
> # Data sets used throughout the test
>
> if {$endianness == "big"} {
> - set vector_register1 ".uint128 =
> 0x3ff4cccccccccccd0000000000000000, v2_double = .0x1, 0x0., v4_float
> = .0x1, 0xf9999998, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd,
> 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x0, 0x0,
> 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd,
> 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
> + set vector_register1 ".float128 =
> 0x3ff4cccccccccccd0000000000000000, uint128 =
> 0x3ff4cccccccccccd0000000000000000, v2_double = .0x3ff4cccccccccccd,
> 0x0., v4_float = .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v4_int32 =
> .0x3ff4cccc, 0xcccccccd, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc,
> 0xcccc, 0xcccd, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc,
> 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> 0x0.."
>
> - set vector_register1_vr ".uint128 =
> 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0xf9999998, 0x0,
> 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1., v8_int16 =
> .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1., v16_int8 =
> .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0, 0x0, 0x1,
> 0x0, 0x0, 0x0, 0x1.."
> + set vector_register1_vr ".uint128 =
> 0x3ff4cccccccccccd0000000100000001, v4_float = .0x3ff4cccc,
> 0xcccccccd, 0x1, 0x1., v4_int32 = .0x3ff4cccc, 0xcccccccd, 0x1, 0x1.,
> v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccd, 0x0, 0x1, 0x0, 0x1.,
> v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcd, 0x0, 0x0,
> 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
>
> - set vector_register2 "uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000,
> 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 =
> .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead,
> 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 =
> .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe,
> 0xef, 0xde, 0xad, 0xbe, 0xef.."
> + set vector_register2 ".float128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef,
> 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
> 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
> 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead,
> 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde,
> 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
>
> - set vector_register2_vr "uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0.,
> v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16
> = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef.,
> v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde,
> 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
> + set vector_register2_vr ".uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef,
> 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef,
> 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef,
> 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde,
> 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef,
> 0xde, 0xad, 0xbe, 0xef.."
>
> - set vector_register3 ".uint128 = 0x1000000010000000100000001,
> v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 =
> .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0,
> 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
> + set vector_register3 ".float128 = 0x1000000010000000100000001,
> uint128 = 0x1000000010000000100000001, v2_double = .0x100000001,
> 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1,
> 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1.,
> v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1, 0x0, 0x0, 0x0, 0x1.."
>
> - set vector_register3_vr ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1.."
> + set vector_register3_vr ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
> 0x1.."
> } else {
> - set vector_register1 ".uint128 =
> 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0, 0x1., v4_float
> = .0x0, 0x0, 0xf9999998, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccd,
> 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc,
> 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd,
> 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.."
> + set vector_register1 ".float128 =
> 0x3ff4cccccccccccd0000000000000000, uint128 =
> 0x3ff4cccccccccccd0000000000000000, v2_double = .0x0,
> 0x3ff4cccccccccccd., v4_float = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc.,
> v4_int32 = .0x0, 0x0, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x0, 0x0,
> 0x0, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0,
> 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4,
> 0x3f.."
>
> - set vector_register1_vr ".uint128 =
> 0x3ff4cccccccccccd0000000100000001, v4_float = .0x0, 0x0, 0xf9999998,
> 0x1., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16 = .0x1,
> 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc,
> 0xf4, 0x3f.."
> + set vector_register1_vr ".uint128 =
> 0x3ff4cccccccccccd0000000100000001, v4_float = .0x1, 0x1, 0xcccccccd,
> 0x3ff4cccc., v4_int32 = .0x1, 0x1, 0xcccccccd, 0x3ff4cccc., v8_int16
> = .0x1, 0x0, 0x1, 0x0, 0xcccd, 0xcccc, 0xcccc, 0x3ff4., v16_int8 =
> .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcd, 0xcc, 0xcc, 0xcc,
> 0xcc, 0xcc, 0xf4, 0x3f.."
>
> - set vector_register2 "uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x8000000000000000,
> 0x8000000000000000., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 =
> .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef,
> 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 =
> .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad,
> 0xde, 0xef, 0xbe, 0xad, 0xde.."
> + set vector_register2 ".float128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0xdeadbeefdeadbeef,
> 0xdeadbeefdeadbeef., v4_float = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
> 0xdeadbeef., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
> 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef,
> 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef,
> 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
>
> - set vector_register2_vr "uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0.,
> v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16
> = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead.,
> v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef,
> 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.."
> + set vector_register2_vr ".uint128 =
> 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0xdeadbeef,
> 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v4_int32 = .0xdeadbeef,
> 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead,
> 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef,
> 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde,
> 0xef, 0xbe, 0xad, 0xde.."
>
> - set vector_register3 ".uint128 = 0x1000000010000000100000001,
> v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 =
> .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1,
> 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0,
> 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.."
> + set vector_register3 ".float128 = 0x1000000010000000100000001,
> uint128 = 0x1000000010000000100000001, v2_double = .0x100000001,
> 0x100000001., v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1,
> 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0.,
> v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0, 0x1, 0x0, 0x0, 0x0.."
>
> - set vector_register3_vr ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
> 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0.."
> + set vector_register3_vr ".uint128 = 0x1000000010000000100000001,
> v4_float = .0x1, 0x1, 0x1, 0x1., v4_int32 = .0x1, 0x1, 0x1, 0x1.,
> v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1,
> 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0,
> 0x0.."
> }
>
> set float_register ".raw 0xdeadbeefdeadbeef."
> @@ -93,12 +93,13 @@ set float_register ".raw 0xdeadbeefdeadbeef."
> # after updates to F*.
> # Since dl_main uses some VS* registers, and per inspection their
> values are
> # no longer zero when our test reaches main(), we need to explicitly
> -# initialize the doubleword1 portions before we run our tests
> against
> -# values currently in those registers.
> +# initialize the VS* registers before we run our tests against the
> values
> +# currently in those registers.
>
> -# 0: Initialize the (doubleword 1) portion of the VS0-VS31
> registers.
> +# 0: Initialize the (doubleword 0 and 1) portion of the VS0-VS31
> registers.
> for {set i 0} {$i < 32} {incr i 1} {
> gdb_test_no_output "set \$vs$i.v2_double\[0\] = 0"
> + gdb_test_no_output "set \$vs$i.v2_double\[1\] = 0"
> }
>
> # 1: Set F0~F31 registers and check if it reflects on VS0~VS31.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2] Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
2022-04-18 20:04 ` [PATCH V2] " Carl Love
2022-04-22 19:50 ` [PATCH V2 Ping] " Carl Love
@ 2022-04-26 14:28 ` Ulrich Weigand
2022-04-26 17:24 ` Carl Love
1 sibling, 1 reply; 6+ messages in thread
From: Ulrich Weigand @ 2022-04-26 14:28 UTC (permalink / raw)
To: gdb-patches, will_schmidt_vnet.ibm.com, cel; +Cc: Rogerio Alves Cardoso, tromey
Carl Love <cel@us.ibm.com> wrote:
>PowerPC: Update expected floating point output for gdb.arch/altivec-
>regs.exp and gdb.arch/vsx-regs.exp
This patch is OK.
As additional comment, I'm wondering whether the display of vector
registers via the union we're using is actually useful when in
hexadecimal mode. The intent of the union is that it should be easy to
interpret the register contents in various ways, in particular both as
integer and as floating-point value, as we may not know what type is
currently being held in the register.
However, with the new way of printing floating-point values when /x is
in effect, it seems that the contents of v4_float will now always be
identical to v4_int32, and similar for the other floating-point union
members.
So maybe it would be better to always show the floating-point members
as actual floating-point, even when the rest of the union is printed
via /x. However, that may be a more invasive change, so I think you
should go ahead and commit the patch as-is now, to improve the
testsuite results.
Bye,
Ulrich
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V2] Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp
2022-04-26 14:28 ` [PATCH V2] " Ulrich Weigand
@ 2022-04-26 17:24 ` Carl Love
0 siblings, 0 replies; 6+ messages in thread
From: Carl Love @ 2022-04-26 17:24 UTC (permalink / raw)
To: Ulrich Weigand, gdb-patches, will_schmidt_vnet.ibm.com
Cc: Rogerio Alves Cardoso, tromey
Ulrich:
I had similar thoughts to your comments below. The output now seems a
bit redundant. I didn't want to try and address that in this patch.
I have committed the patch as is. I have created an internal to do for
us to look at cleaning up the output on Power per your comments.
Thanks.
Carl
On Tue, 2022-04-26 at 14:28 +0000, Ulrich Weigand wrote:
> Carl Love <cel@us.ibm.com> wrote:
>
> > PowerPC: Update expected floating point output for
> > gdb.arch/altivec-
> > regs.exp and gdb.arch/vsx-regs.exp
>
> This patch is OK.
>
> As additional comment, I'm wondering whether the display of vector
> registers via the union we're using is actually useful when in
> hexadecimal mode. The intent of the union is that it should be easy
> to
> interpret the register contents in various ways, in particular both
> as
> integer and as floating-point value, as we may not know what type is
> currently being held in the register.
>
> However, with the new way of printing floating-point values when /x
> is
> in effect, it seems that the contents of v4_float will now always be
> identical to v4_int32, and similar for the other floating-point union
> members.
>
> So maybe it would be better to always show the floating-point members
> as actual floating-point, even when the rest of the union is printed
> via /x. However, that may be a more invasive change, so I think you
> should go ahead and commit the patch as-is now, to improve the
> testsuite results.
>
> Bye,
> Ulrich
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-04-26 17:24 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-12 4:47 Powerpc: Update expected floating point output for gdb.arch/altivec-regs.exp and gdb.arch/vsx-regs.exp Carl Love
2022-04-18 16:20 ` will schmidt
2022-04-18 20:04 ` [PATCH V2] " Carl Love
2022-04-22 19:50 ` [PATCH V2 Ping] " Carl Love
2022-04-26 14:28 ` [PATCH V2] " Ulrich Weigand
2022-04-26 17:24 ` Carl Love
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