* [PATCH v2 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs [not found] <cover.1690251857.git.research_trasio@irq.a4lg.com> @ 2023-08-31 3:21 ` Tsukasa OI 2023-08-31 3:21 ` [PATCH v2 1/3] RISC-V: Remove RV64E conflict Tsukasa OI ` (3 more replies) 0 siblings, 4 replies; 9+ messages in thread From: Tsukasa OI @ 2023-08-31 3:21 UTC (permalink / raw) To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu, Kito Cheng Cc: binutils, gdb-patches Hi, PATCH v1 (only Binutils): <https://sourceware.org/pipermail/binutils/2023-July/128583.html> Changes: v1 -> v2 - Added preliminary GDB support Related Project: PATCH 1/3: Binutils PATCH 2/3: Binutils PATCH 3/3: GDB This patch set reflects ratified 'E' base ISAs (except version number of 'E') and draft/pre-draft RVE ABIs, ILP32E and LP64E. RV32E / RV64E (ratified): The latest RISC-V ISA Manual <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23> ILP32E (draft): RISCV ABIs Specification version 1.0 <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0> LP64E (pre-draft): Submission to add RVE API corresponding RV64E <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/299> Adding pre-draft LP64E would be a problem on GCC but I bet not on Binutils (ELF flags [to handle on Binutils/GAS] are not very detailed). Note that this patch set does not reflect the version number of the 'E' base ISA (ratified version 2.0) because the latest ratified specification, "20191213", comes with the draft version 1.9 and adding the version 2.0 with ISA_SPEC_CLASS_DRAFT does not work (due to the default value of `DEFAULT_RISCV_ISA_SPEC'; note that it cannot be set to "draft"). I think the next unprivileged ISA specification release is the best timing to add 'E' version 2.0 (along with new ISA_SPEC_CLASS_20??????). Thanks, Tsukasa Tsukasa OI (3): RISC-V: Remove RV64E conflict RISC-V: Add "lp64e" ABI support RISC-V: Add RV64E support to GDB bfd/elfxx-riscv.c | 7 ----- gas/config/tc-riscv.c | 4 ++- gas/doc/c-riscv.texi | 5 ++- .../gas/riscv/mabi-fail-rv32e-lp64d.l | 2 +- .../gas/riscv/mabi-fail-rv32e-lp64f.l | 2 +- .../gas/riscv/mabi-fail-rv32e-lp64q.l | 2 +- gas/testsuite/gas/riscv/march-fail-base-02.d | 3 -- gas/testsuite/gas/riscv/march-fail-base-02.l | 2 -- gdb/arch/riscv.c | 15 +++++++-- gdb/arch/riscv.h | 2 +- gdb/features/Makefile | 1 + gdb/features/riscv/rv64e-xregs.c | 30 ++++++++++++++++++ gdb/features/riscv/rv64e-xregs.xml | 31 +++++++++++++++++++ gdb/riscv-tdep.c | 9 +----- 14 files changed, 85 insertions(+), 30 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.l create mode 100644 gdb/features/riscv/rv64e-xregs.c create mode 100644 gdb/features/riscv/rv64e-xregs.xml base-commit: 68a2d9bf874643da970fe945a9c60c397f6882ad -- 2.42.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] RISC-V: Remove RV64E conflict 2023-08-31 3:21 ` [PATCH v2 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI @ 2023-08-31 3:21 ` Tsukasa OI 2023-08-31 3:21 ` [PATCH v2 2/3] RISC-V: Add "lp64e" ABI support Tsukasa OI ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: Tsukasa OI @ 2023-08-31 3:21 UTC (permalink / raw) To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu, Kito Cheng Cc: binutils, gdb-patches From: Tsukasa OI <research_trasio@irq.a4lg.com> Since RV32E *and* RV64E are ratified, RV64E is no longer invalid. This commit removes a restriction that prevents making base ISA with reduced GPRs with XLEN > 32. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove RV64E conflict since the ratified 'E' base ISAs include RV64E. gas/ChangeLog: * testsuite/gas/riscv/march-fail-base-02.d: Removed. * testsuite/gas/riscv/march-fail-base-02.l: Removed. --- bfd/elfxx-riscv.c | 7 ------- gas/testsuite/gas/riscv/march-fail-base-02.d | 3 --- gas/testsuite/gas/riscv/march-fail-base-02.l | 2 -- 3 files changed, 12 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.l diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index cb65024beaff..9a397c5a8d1c 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1942,13 +1942,6 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) int xlen = *rps->xlen; bool no_conflict = true; - if (riscv_lookup_subset (rps->subset_list, "e", &subset) - && xlen > 32) - { - rps->error_handler - (_("rv%d does not support the `e' extension"), xlen); - no_conflict = false; - } if (riscv_lookup_subset (rps->subset_list, "q", &subset) && (subset->major_version < 2 || (subset->major_version == 2 && subset->minor_version < 2)) diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.d b/gas/testsuite/gas/riscv/march-fail-base-02.d deleted file mode 100644 index cfe085ab21aa..000000000000 --- a/gas/testsuite/gas/riscv/march-fail-base-02.d +++ /dev/null @@ -1,3 +0,0 @@ -#as: -march=rv64e -#source: empty.s -#error_output: march-fail-base-02.l diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.l b/gas/testsuite/gas/riscv/march-fail-base-02.l deleted file mode 100644 index 52fee96af368..000000000000 --- a/gas/testsuite/gas/riscv/march-fail-base-02.l +++ /dev/null @@ -1,2 +0,0 @@ -.*Assembler messages: -.*Error: rv64 does not support the `e' extension -- 2.42.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] RISC-V: Add "lp64e" ABI support 2023-08-31 3:21 ` [PATCH v2 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI 2023-08-31 3:21 ` [PATCH v2 1/3] RISC-V: Remove RV64E conflict Tsukasa OI @ 2023-08-31 3:21 ` Tsukasa OI 2023-08-31 3:21 ` [PATCH v2 3/3] RISC-V: Add RV64E support to GDB Tsukasa OI 2023-09-05 9:08 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI 3 siblings, 0 replies; 9+ messages in thread From: Tsukasa OI @ 2023-08-31 3:21 UTC (permalink / raw) To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu, Kito Cheng Cc: binutils, gdb-patches From: Tsukasa OI <research_trasio@irq.a4lg.com> Since RV32E and RV64E are now ratified, this commit prepares the ABI support for LP64E (LP64 with reduced GPRs). gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Update the error message. (md_parse_option): Accept "lp64e". * doc/c-riscv.texi: Update the documentation to allow "lp64e". * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Change error message. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise. --- gas/config/tc-riscv.c | 4 +++- gas/doc/c-riscv.texi | 5 ++--- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 959cbbc32a5e..d0caf691fc65 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -384,7 +384,7 @@ riscv_set_abi_by_arch (void) as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) - as_bad ("only the ilp32e ABI is supported for e extension"); + as_bad ("only ilp32e/lp64e ABI are supported for e extension"); if (float_abi == FLOAT_ABI_SINGLE && !riscv_subset_supports (&riscv_rps_as, "f")) @@ -3897,6 +3897,8 @@ md_parse_option (int c, const char *arg) riscv_set_abi (32, FLOAT_ABI_QUAD, false); else if (strcmp (arg, "lp64") == 0) riscv_set_abi (64, FLOAT_ABI_SOFT, false); + else if (strcmp (arg, "lp64e") == 0) + riscv_set_abi (64, FLOAT_ABI_SOFT, true); else if (strcmp (arg, "lp64f") == 0) riscv_set_abi (64, FLOAT_ABI_SINGLE, false); else if (strcmp (arg, "lp64d") == 0) diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b175ba0a7293..e7fdbfa22afb 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -65,9 +65,8 @@ aren't set, then assembler will check the default configure setting @item -mabi=ABI Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or -quad-precision floating-point calling convention, or none to indicate -the soft-float calling convention. Also, "ilp32" can optionally be followed -by "e" to indicate the RVE ABI, which is always soft-float. +quad-precision floating-point calling convention, or none or "e" to indicate +the soft-float calling convention ("e" indicates a soft-float RVE ABI). @cindex @samp{-mrelax} option, RISC-V @item -mrelax diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l index f7306cb24d20..419a01d5d53a 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32d/lp64d ABI can't be used when d extension isn't supported diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l index 706690ac9c64..7b2fcda8d685 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32f/lp64f ABI can't be used when f extension isn't supported diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l index ab64b1546f63..a06e9ea1aa93 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32q/lp64q ABI can't be used when q extension isn't supported -- 2.42.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] RISC-V: Add RV64E support to GDB 2023-08-31 3:21 ` [PATCH v2 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI 2023-08-31 3:21 ` [PATCH v2 1/3] RISC-V: Remove RV64E conflict Tsukasa OI 2023-08-31 3:21 ` [PATCH v2 2/3] RISC-V: Add "lp64e" ABI support Tsukasa OI @ 2023-08-31 3:21 ` Tsukasa OI 2023-09-05 9:08 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI 3 siblings, 0 replies; 9+ messages in thread From: Tsukasa OI @ 2023-08-31 3:21 UTC (permalink / raw) To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu, Kito Cheng Cc: binutils, gdb-patches From: Tsukasa OI <research_trasio@irq.a4lg.com> Since RV32E and RV64E are ratified, RV64E is no longer invalid. So, this commit adds RV64E support for various parts. --- gdb/arch/riscv.c | 15 +++++++++++++-- gdb/arch/riscv.h | 2 +- gdb/features/Makefile | 1 + gdb/features/riscv/rv64e-xregs.c | 30 +++++++++++++++++++++++++++++ gdb/features/riscv/rv64e-xregs.xml | 31 ++++++++++++++++++++++++++++++ gdb/riscv-tdep.c | 9 +-------- 6 files changed, 77 insertions(+), 11 deletions(-) create mode 100644 gdb/features/riscv/rv64e-xregs.c create mode 100644 gdb/features/riscv/rv64e-xregs.xml diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c index 6f6fcb081e81..346fc1d0230d 100644 --- a/gdb/arch/riscv.c +++ b/gdb/arch/riscv.c @@ -25,6 +25,7 @@ #include "../features/riscv/32bit-fpu.c" #include "../features/riscv/64bit-fpu.c" #include "../features/riscv/rv32e-xregs.c" +#include "../features/riscv/rv64e-xregs.c" #ifndef GDBSERVER #define STATIC_IN_GDB static @@ -51,7 +52,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) arch_name.append (":rv32i"); } else if (features.xlen == 8) - arch_name.append (":rv64i"); + { + if (features.embedded) + arch_name.append (":rv64e"); + else + arch_name.append (":rv64i"); + } else if (features.xlen == 16) arch_name.append (":rv128i"); @@ -76,7 +82,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum); } else if (features.xlen == 8) - regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum); + { + if (features.embedded) + regnum = create_feature_riscv_rv64e_xregs (tdesc.get (), regnum); + else + regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum); + } /* For now we only support creating 32-bit or 64-bit f-registers. */ if (features.flen == 4) diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h index e1965da69ebb..abbac59aa09b 100644 --- a/gdb/arch/riscv.h +++ b/gdb/arch/riscv.h @@ -53,7 +53,7 @@ struct riscv_gdbarch_features vector size. */ int vlen = 0; - /* When true this target is RV32E. */ + /* When true this target is RV32E or RV64E. */ bool embedded = false; /* Track if the target description has an fcsr, fflags, and frm diff --git a/gdb/features/Makefile b/gdb/features/Makefile index 32341f718156..a2719d0cd813 100644 --- a/gdb/features/Makefile +++ b/gdb/features/Makefile @@ -238,6 +238,7 @@ FEATURE_XMLFILES = aarch64-core.xml \ loongarch/base64.xml \ loongarch/fpu.xml \ riscv/rv32e-xregs.xml \ + riscv/rv64e-xregs.xml \ riscv/32bit-cpu.xml \ riscv/32bit-fpu.xml \ riscv/64bit-cpu.xml \ diff --git a/gdb/features/riscv/rv64e-xregs.c b/gdb/features/riscv/rv64e-xregs.c new file mode 100644 index 000000000000..4346c3004ba8 --- /dev/null +++ b/gdb/features/riscv/rv64e-xregs.c @@ -0,0 +1,30 @@ +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: + Original: rv64e-xregs.xml */ + +#include "gdbsupport/tdesc.h" + +static int +create_feature_riscv_rv64e_xregs (struct target_desc *result, long regnum) +{ + struct tdesc_feature *feature; + + feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.cpu"); + tdesc_create_reg (feature, "zero", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "ra", regnum++, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "sp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "gp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "tp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "t0", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "t1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "t2", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "fp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "s1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a0", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a2", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a3", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a4", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a5", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 64, "code_ptr"); + return regnum; +} diff --git a/gdb/features/riscv/rv64e-xregs.xml b/gdb/features/riscv/rv64e-xregs.xml new file mode 100644 index 000000000000..103588fd7f2d --- /dev/null +++ b/gdb/features/riscv/rv64e-xregs.xml @@ -0,0 +1,31 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2023 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- Register numbers are hard-coded in order to maintain backward + compatibility with older versions of tools that didn't use xml + register descriptions. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.cpu"> + <reg name="zero" bitsize="64" type="int" regnum="0"/> + <reg name="ra" bitsize="64" type="code_ptr"/> + <reg name="sp" bitsize="64" type="data_ptr"/> + <reg name="gp" bitsize="64" type="data_ptr"/> + <reg name="tp" bitsize="64" type="data_ptr"/> + <reg name="t0" bitsize="64" type="int"/> + <reg name="t1" bitsize="64" type="int"/> + <reg name="t2" bitsize="64" type="int"/> + <reg name="fp" bitsize="64" type="data_ptr"/> + <reg name="s1" bitsize="64" type="int"/> + <reg name="a0" bitsize="64" type="int"/> + <reg name="a1" bitsize="64" type="int"/> + <reg name="a2" bitsize="64" type="int"/> + <reg name="a3" bitsize="64" type="int"/> + <reg name="a4" bitsize="64" type="int"/> + <reg name="a5" bitsize="64" type="int"/> + <reg name="pc" bitsize="64" type="code_ptr"/> +</feature> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index ae18eb644527..b230ba634147 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -3847,14 +3847,7 @@ riscv_features_from_bfd (const bfd *abfd) features.flen = 4; if (e_flags & EF_RISCV_RVE) - { - if (features.xlen == 8) - { - warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit")); - features.xlen = 4; - } - features.embedded = true; - } + features.embedded = true; } return features; -- 2.42.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs 2023-08-31 3:21 ` [PATCH v2 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI ` (2 preceding siblings ...) 2023-08-31 3:21 ` [PATCH v2 3/3] RISC-V: Add RV64E support to GDB Tsukasa OI @ 2023-09-05 9:08 ` Tsukasa OI 2023-09-05 9:08 ` [PATCH v3 1/3] RISC-V: Remove RV64E conflict Tsukasa OI ` (3 more replies) 3 siblings, 4 replies; 9+ messages in thread From: Tsukasa OI @ 2023-09-05 9:08 UTC (permalink / raw) To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu, Kito Cheng Cc: binutils, gdb-patches Hi, PATCH v1 (only Binutils): <https://sourceware.org/pipermail/binutils/2023-July/128583.html> PATCH v2 (Binutils+GDB): <https://sourceware.org/pipermail/binutils/2023-August/129314.html> Changes: v1 -> v2 - Added GDB support Changes: v2 -> v3 - Rebased against the latest master (PATCH 1/3 related merge conflict is now resolved) Related Project: PATCH 1/3: Binutils PATCH 2/3: Binutils PATCH 3/3: GDB This patch set reflects ratified 'E' base ISAs (except version number of 'E') and draft/pre-draft RVE ABIs, ILP32E and LP64E. RV32E / RV64E (ratified): The latest RISC-V ISA Manual <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23> ILP32E (draft): RISCV ABIs Specification version 1.0 <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0> LP64E (pre-draft): Submission to add RVE API corresponding RV64E <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/299> Adding pre-draft LP64E would be a problem on GCC but I bet not on Binutils (ELF flags [to handle on Binutils/GAS] are not very detailed). Note that this patch set does not reflect the version number of the 'E' base ISA (ratified version 2.0) because the latest ratified specification, "20191213", comes with the draft version 1.9 and adding the version 2.0 with ISA_SPEC_CLASS_DRAFT does not work (due to the default value of `DEFAULT_RISCV_ISA_SPEC'; note that it cannot be set to "draft"). I think the next unprivileged ISA specification release is the best timing to add 'E' version 2.0 (along with new ISA_SPEC_CLASS_20??????). Thanks, Tsukasa Tsukasa OI (3): RISC-V: Remove RV64E conflict RISC-V: Add "lp64e" ABI support RISC-V: Add RV64E support to GDB bfd/elfxx-riscv.c | 7 ----- gas/config/tc-riscv.c | 4 ++- gas/doc/c-riscv.texi | 5 ++- .../gas/riscv/mabi-fail-rv32e-lp64d.l | 2 +- .../gas/riscv/mabi-fail-rv32e-lp64f.l | 2 +- .../gas/riscv/mabi-fail-rv32e-lp64q.l | 2 +- gas/testsuite/gas/riscv/march-fail-base-02.d | 3 -- gas/testsuite/gas/riscv/march-fail-base-02.l | 2 -- gdb/arch/riscv.c | 15 +++++++-- gdb/arch/riscv.h | 2 +- gdb/features/Makefile | 1 + gdb/features/riscv/rv64e-xregs.c | 30 ++++++++++++++++++ gdb/features/riscv/rv64e-xregs.xml | 31 +++++++++++++++++++ gdb/riscv-tdep.c | 9 +----- 14 files changed, 85 insertions(+), 30 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.l create mode 100644 gdb/features/riscv/rv64e-xregs.c create mode 100644 gdb/features/riscv/rv64e-xregs.xml base-commit: d4868004365e6bc4232a1b8ebd4b328fc5bec8b1 -- 2.42.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/3] RISC-V: Remove RV64E conflict 2023-09-05 9:08 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI @ 2023-09-05 9:08 ` Tsukasa OI 2023-09-05 9:08 ` [PATCH v3 2/3] RISC-V: Add "lp64e" ABI support Tsukasa OI ` (2 subsequent siblings) 3 siblings, 0 replies; 9+ messages in thread From: Tsukasa OI @ 2023-09-05 9:08 UTC (permalink / raw) To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu, Kito Cheng Cc: binutils, gdb-patches From: Tsukasa OI <research_trasio@irq.a4lg.com> Since RV32E *and* RV64E are ratified, RV64E is no longer invalid. This commit removes a restriction that prevents making base ISA with reduced GPRs with XLEN > 32. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): Remove RV64E conflict since the ratified 'E' base ISAs include RV64E. gas/ChangeLog: * testsuite/gas/riscv/march-fail-base-02.d: Removed. * testsuite/gas/riscv/march-fail-base-02.l: Removed. --- bfd/elfxx-riscv.c | 7 ------- gas/testsuite/gas/riscv/march-fail-base-02.d | 3 --- gas/testsuite/gas/riscv/march-fail-base-02.l | 2 -- 3 files changed, 12 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-base-02.l diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e642a05fe5b8..4553075735f8 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1946,13 +1946,6 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) int xlen = *rps->xlen; bool no_conflict = true; - if (riscv_lookup_subset (rps->subset_list, "e", &subset) - && xlen > 32) - { - rps->error_handler - (_("rv%d does not support the `e' extension"), xlen); - no_conflict = false; - } if (riscv_subset_supports (rps, "e") && riscv_subset_supports (rps, "h")) { diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.d b/gas/testsuite/gas/riscv/march-fail-base-02.d deleted file mode 100644 index cfe085ab21aa..000000000000 --- a/gas/testsuite/gas/riscv/march-fail-base-02.d +++ /dev/null @@ -1,3 +0,0 @@ -#as: -march=rv64e -#source: empty.s -#error_output: march-fail-base-02.l diff --git a/gas/testsuite/gas/riscv/march-fail-base-02.l b/gas/testsuite/gas/riscv/march-fail-base-02.l deleted file mode 100644 index 52fee96af368..000000000000 --- a/gas/testsuite/gas/riscv/march-fail-base-02.l +++ /dev/null @@ -1,2 +0,0 @@ -.*Assembler messages: -.*Error: rv64 does not support the `e' extension -- 2.42.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 2/3] RISC-V: Add "lp64e" ABI support 2023-09-05 9:08 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI 2023-09-05 9:08 ` [PATCH v3 1/3] RISC-V: Remove RV64E conflict Tsukasa OI @ 2023-09-05 9:08 ` Tsukasa OI 2023-09-05 9:08 ` [PATCH v3 3/3] RISC-V: Add RV64E support to GDB Tsukasa OI 2023-09-25 3:07 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Nelson Chu 3 siblings, 0 replies; 9+ messages in thread From: Tsukasa OI @ 2023-09-05 9:08 UTC (permalink / raw) To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu, Kito Cheng Cc: binutils, gdb-patches From: Tsukasa OI <research_trasio@irq.a4lg.com> Since RV32E and RV64E are now ratified, this commit prepares the ABI support for LP64E (LP64 with reduced GPRs). gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Update the error message. (md_parse_option): Accept "lp64e". * doc/c-riscv.texi: Update the documentation to allow "lp64e". * testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l: Change error message. * testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l: Likewise. * testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l: Likewise. --- gas/config/tc-riscv.c | 4 +++- gas/doc/c-riscv.texi | 5 ++--- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l | 2 +- gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l | 2 +- 5 files changed, 8 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index e3bcf8b280eb..f2a031735eb4 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -386,7 +386,7 @@ riscv_set_abi_by_arch (void) as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) - as_bad ("only the ilp32e ABI is supported for e extension"); + as_bad ("only ilp32e/lp64e ABI are supported for e extension"); if (float_abi == FLOAT_ABI_SINGLE && !riscv_subset_supports (&riscv_rps_as, "f")) @@ -3871,6 +3871,8 @@ md_parse_option (int c, const char *arg) riscv_set_abi (32, FLOAT_ABI_QUAD, false); else if (strcmp (arg, "lp64") == 0) riscv_set_abi (64, FLOAT_ABI_SOFT, false); + else if (strcmp (arg, "lp64e") == 0) + riscv_set_abi (64, FLOAT_ABI_SOFT, true); else if (strcmp (arg, "lp64f") == 0) riscv_set_abi (64, FLOAT_ABI_SINGLE, false); else if (strcmp (arg, "lp64d") == 0) diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b175ba0a7293..e7fdbfa22afb 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -65,9 +65,8 @@ aren't set, then assembler will check the default configure setting @item -mabi=ABI Selects the ABI, which is either "ilp32" or "lp64", optionally followed by "f", "d", or "q" to indicate single-precision, double-precision, or -quad-precision floating-point calling convention, or none to indicate -the soft-float calling convention. Also, "ilp32" can optionally be followed -by "e" to indicate the RVE ABI, which is always soft-float. +quad-precision floating-point calling convention, or none or "e" to indicate +the soft-float calling convention ("e" indicates a soft-float RVE ABI). @cindex @samp{-mrelax} option, RISC-V @item -mrelax diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l index f7306cb24d20..419a01d5d53a 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64d.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32d/lp64d ABI can't be used when d extension isn't supported diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l index 706690ac9c64..7b2fcda8d685 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64f.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32f/lp64f ABI can't be used when f extension isn't supported diff --git a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l index ab64b1546f63..a06e9ea1aa93 100644 --- a/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l +++ b/gas/testsuite/gas/riscv/mabi-fail-rv32e-lp64q.l @@ -1,4 +1,4 @@ .*Assembler messages: .*Error: can't have 64-bit ABI on 32-bit ISA -.*Error: only the ilp32e ABI is supported for e extension +.*Error: only ilp32e/lp64e ABI are supported for e extension .*Error: ilp32q/lp64q ABI can't be used when q extension isn't supported -- 2.42.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] RISC-V: Add RV64E support to GDB 2023-09-05 9:08 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI 2023-09-05 9:08 ` [PATCH v3 1/3] RISC-V: Remove RV64E conflict Tsukasa OI 2023-09-05 9:08 ` [PATCH v3 2/3] RISC-V: Add "lp64e" ABI support Tsukasa OI @ 2023-09-05 9:08 ` Tsukasa OI 2023-09-25 3:07 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Nelson Chu 3 siblings, 0 replies; 9+ messages in thread From: Tsukasa OI @ 2023-09-05 9:08 UTC (permalink / raw) To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson, Nelson Chu, Kito Cheng Cc: binutils, gdb-patches From: Tsukasa OI <research_trasio@irq.a4lg.com> Since RV32E and RV64E are ratified, RV64E is no longer invalid. So, this commit adds RV64E support for various parts. --- gdb/arch/riscv.c | 15 +++++++++++++-- gdb/arch/riscv.h | 2 +- gdb/features/Makefile | 1 + gdb/features/riscv/rv64e-xregs.c | 30 +++++++++++++++++++++++++++++ gdb/features/riscv/rv64e-xregs.xml | 31 ++++++++++++++++++++++++++++++ gdb/riscv-tdep.c | 9 +-------- 6 files changed, 77 insertions(+), 11 deletions(-) create mode 100644 gdb/features/riscv/rv64e-xregs.c create mode 100644 gdb/features/riscv/rv64e-xregs.xml diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c index 6f6fcb081e81..346fc1d0230d 100644 --- a/gdb/arch/riscv.c +++ b/gdb/arch/riscv.c @@ -25,6 +25,7 @@ #include "../features/riscv/32bit-fpu.c" #include "../features/riscv/64bit-fpu.c" #include "../features/riscv/rv32e-xregs.c" +#include "../features/riscv/rv64e-xregs.c" #ifndef GDBSERVER #define STATIC_IN_GDB static @@ -51,7 +52,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) arch_name.append (":rv32i"); } else if (features.xlen == 8) - arch_name.append (":rv64i"); + { + if (features.embedded) + arch_name.append (":rv64e"); + else + arch_name.append (":rv64i"); + } else if (features.xlen == 16) arch_name.append (":rv128i"); @@ -76,7 +82,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features) regnum = create_feature_riscv_32bit_cpu (tdesc.get (), regnum); } else if (features.xlen == 8) - regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum); + { + if (features.embedded) + regnum = create_feature_riscv_rv64e_xregs (tdesc.get (), regnum); + else + regnum = create_feature_riscv_64bit_cpu (tdesc.get (), regnum); + } /* For now we only support creating 32-bit or 64-bit f-registers. */ if (features.flen == 4) diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h index e1965da69ebb..abbac59aa09b 100644 --- a/gdb/arch/riscv.h +++ b/gdb/arch/riscv.h @@ -53,7 +53,7 @@ struct riscv_gdbarch_features vector size. */ int vlen = 0; - /* When true this target is RV32E. */ + /* When true this target is RV32E or RV64E. */ bool embedded = false; /* Track if the target description has an fcsr, fflags, and frm diff --git a/gdb/features/Makefile b/gdb/features/Makefile index 32341f718156..a2719d0cd813 100644 --- a/gdb/features/Makefile +++ b/gdb/features/Makefile @@ -238,6 +238,7 @@ FEATURE_XMLFILES = aarch64-core.xml \ loongarch/base64.xml \ loongarch/fpu.xml \ riscv/rv32e-xregs.xml \ + riscv/rv64e-xregs.xml \ riscv/32bit-cpu.xml \ riscv/32bit-fpu.xml \ riscv/64bit-cpu.xml \ diff --git a/gdb/features/riscv/rv64e-xregs.c b/gdb/features/riscv/rv64e-xregs.c new file mode 100644 index 000000000000..4346c3004ba8 --- /dev/null +++ b/gdb/features/riscv/rv64e-xregs.c @@ -0,0 +1,30 @@ +/* THIS FILE IS GENERATED. -*- buffer-read-only: t -*- vi:set ro: + Original: rv64e-xregs.xml */ + +#include "gdbsupport/tdesc.h" + +static int +create_feature_riscv_rv64e_xregs (struct target_desc *result, long regnum) +{ + struct tdesc_feature *feature; + + feature = tdesc_create_feature (result, "org.gnu.gdb.riscv.cpu"); + tdesc_create_reg (feature, "zero", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "ra", regnum++, 1, NULL, 64, "code_ptr"); + tdesc_create_reg (feature, "sp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "gp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "tp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "t0", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "t1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "t2", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "fp", regnum++, 1, NULL, 64, "data_ptr"); + tdesc_create_reg (feature, "s1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a0", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a1", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a2", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a3", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a4", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "a5", regnum++, 1, NULL, 64, "int"); + tdesc_create_reg (feature, "pc", regnum++, 1, NULL, 64, "code_ptr"); + return regnum; +} diff --git a/gdb/features/riscv/rv64e-xregs.xml b/gdb/features/riscv/rv64e-xregs.xml new file mode 100644 index 000000000000..103588fd7f2d --- /dev/null +++ b/gdb/features/riscv/rv64e-xregs.xml @@ -0,0 +1,31 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2018-2023 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!-- Register numbers are hard-coded in order to maintain backward + compatibility with older versions of tools that didn't use xml + register descriptions. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.riscv.cpu"> + <reg name="zero" bitsize="64" type="int" regnum="0"/> + <reg name="ra" bitsize="64" type="code_ptr"/> + <reg name="sp" bitsize="64" type="data_ptr"/> + <reg name="gp" bitsize="64" type="data_ptr"/> + <reg name="tp" bitsize="64" type="data_ptr"/> + <reg name="t0" bitsize="64" type="int"/> + <reg name="t1" bitsize="64" type="int"/> + <reg name="t2" bitsize="64" type="int"/> + <reg name="fp" bitsize="64" type="data_ptr"/> + <reg name="s1" bitsize="64" type="int"/> + <reg name="a0" bitsize="64" type="int"/> + <reg name="a1" bitsize="64" type="int"/> + <reg name="a2" bitsize="64" type="int"/> + <reg name="a3" bitsize="64" type="int"/> + <reg name="a4" bitsize="64" type="int"/> + <reg name="a5" bitsize="64" type="int"/> + <reg name="pc" bitsize="64" type="code_ptr"/> +</feature> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index ae18eb644527..b230ba634147 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -3847,14 +3847,7 @@ riscv_features_from_bfd (const bfd *abfd) features.flen = 4; if (e_flags & EF_RISCV_RVE) - { - if (features.xlen == 8) - { - warning (_("64-bit ELF with RV32E flag set! Assuming 32-bit")); - features.xlen = 4; - } - features.embedded = true; - } + features.embedded = true; } return features; -- 2.42.0 ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs 2023-09-05 9:08 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI ` (2 preceding siblings ...) 2023-09-05 9:08 ` [PATCH v3 3/3] RISC-V: Add RV64E support to GDB Tsukasa OI @ 2023-09-25 3:07 ` Nelson Chu 3 siblings, 0 replies; 9+ messages in thread From: Nelson Chu @ 2023-09-25 3:07 UTC (permalink / raw) To: Tsukasa OI Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Kito Cheng, binutils, gdb-patches [-- Attachment #1: Type: text/plain, Size: 698 bytes --] On Tue, Sep 5, 2023 at 5:08 PM Tsukasa OI <research_trasio@irq.a4lg.com> wrote: > Hi, > > PATCH v1 (only Binutils): > <https://sourceware.org/pipermail/binutils/2023-July/128583.html> > PATCH v2 (Binutils+GDB): > <https://sourceware.org/pipermail/binutils/2023-August/129314.html> > > Changes: v1 -> v2 > - Added GDB support > > Changes: v2 -> v3 > - Rebased against the latest master > (PATCH 1/3 related merge conflict is now resolved) > > > Related Project: > PATCH 1/3: Binutils > PATCH 2/3: Binutils > Looks good to me :-) > PATCH 3/3: GDB > I cannot approve anything about gdb, so this will need gdb experts to help. Thanks Nelson ^ permalink raw reply [flat|nested] 9+ messages in thread
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2023-08-31 3:21 ` [PATCH v2 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI
2023-08-31 3:21 ` [PATCH v2 1/3] RISC-V: Remove RV64E conflict Tsukasa OI
2023-08-31 3:21 ` [PATCH v2 2/3] RISC-V: Add "lp64e" ABI support Tsukasa OI
2023-08-31 3:21 ` [PATCH v2 3/3] RISC-V: Add RV64E support to GDB Tsukasa OI
2023-09-05 9:08 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Tsukasa OI
2023-09-05 9:08 ` [PATCH v3 1/3] RISC-V: Remove RV64E conflict Tsukasa OI
2023-09-05 9:08 ` [PATCH v3 2/3] RISC-V: Add "lp64e" ABI support Tsukasa OI
2023-09-05 9:08 ` [PATCH v3 3/3] RISC-V: Add RV64E support to GDB Tsukasa OI
2023-09-25 3:07 ` [PATCH v3 0/3] RISC-V: Add ratified 'E' base ISA support with draft ABIs Nelson Chu
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