[Bug gdb/29471] New: gdb 12.1 'i r' command doesn't recognise register NZCV under target aarch64

[Bug gdb/29471] New: gdb 12.1 'i r' command doesn't recognise register NZCV under target aarch64

[petemoore at gmx dot net]

https://sourceware.org/bugzilla/show_bug.cgi?id=29471

            Bug ID: 29471
           Summary: gdb 12.1 'i r' command doesn't recognise register NZCV
                    under target aarch64
           Product: gdb
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: gdb
          Assignee: unassigned at sourceware dot org
          Reporter: petemoore at gmx dot net
  Target Milestone: ---

In AArch64 state, there is no Current Program Status Register (CPSR). You can
access the different components of the traditional CPSR independently as the
following Process State fields:

N, Z, C, and V condition flags (NZCV).
Current register width (nRW).
Stack pointer selection bit (SPSel).
Interrupt disable flags (DAIF).
Current exception level (EL).
Single step process state bit (SS).
Illegal exception return state bit (IL).

See:
https://developer.arm.com/documentation/dui0801/a/Overview-of-AArch64-state/Process-State

However, when I display registers in gdb, nzcv is not shown, and cpsr is:

```
(gdb) i r
x0             0x43                67
x1             0xe23d402b356d3bce  -2144487293234365490
x2             0x5a4d387e567f030   406682446993027120
x3             0x5a                90
x4             0x27a2              10146
x5             0x5a                90
x6             0x43                67
x7             0x756e89b103df671c  8461852143242929948
x8             0x624d1246a62939a9  7083337883568388521
x9             0x1b1af900032c1cc8  1953147166867070152
x10            0x8bc19566de54593a  -8376249562883139270
x11            0x184366151d3c3a4a  1748353321220717130
x12            0x18edff72c0631cb3  1796372694709771443
x13            0x26ac09d83f16143a  2786613093811491898
x14            0x55342216197e994b  6139569670325180747
x15            0xe28fed9e950e9254  -2121215634106838444
x16            0xaf56554915dfd8ef  -5812364496687081233
x17            0xbac3e3a52a18a9b7  -4988893663681009225
x18            0x91077f6feafd18b   653153848687317387
x19            0x98a0474a818d0bdb  -7448875398344143909
x20            0xe05fa2ada09bcaba  -2278924019818575174
x21            0x608e95a84113f94   434853939013304212
x22            0xd56ed339042e92f3  -3067282054355971341
x23            0x3bb6d74d34f84b97  4302863220600228759
x24            0xd860f821d113d545  -2855009339627547323
x25            0x2a78b30673bda2f7  3060392787091235575
x26            0x30b04bd9c590e740  3508387508416210752
x27            0x98d07855f9e2b0c2  -7435310674128752446
x28            0x211a0             135584
x29            0x3bfffc50          1006632016
x30            0x230c              8972
sp             0x3bfffc50          0x3bfffc50
pc             0x2438              0x2438 <print_w0>
cpsr           0x200003cd          [ SP EL=3 F I A D BTYPE=0 C ]
fpsr           0x0                 [ ]
fpcr           0x0                 [ RMode=0 ]
```

Furthermore, if I try to inspect the nzcv register, I get an error:

```
(gdb) i r nzcv
Invalid register `nzcv'
```

This is gdb 12.1, built from source and configured with
`--target=aarch64-none-elf` running under ubuntu 20.04.

Many thanks.

-- 
You are receiving this mail because:
You are on the CC list for the bug.

[Bug gdb/29471] gdb 12.1 'i r' command doesn't recognise register NZCV under target aarch64-none-elf

[petemoore at gmx dot net]

https://sourceware.org/bugzilla/show_bug.cgi?id=29471

Pete Moore <petemoore at gmx dot net> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|gdb 12.1 'i r' command      |gdb 12.1 'i r' command
                   |doesn't recognise register  |doesn't recognise register
                   |NZCV under target aarch64   |NZCV under target
                   |                            |aarch64-none-elf

-- 
You are receiving this mail because:
You are on the CC list for the bug.

[Bug gdb/29471] gdb 12.1 'i r' command doesn't recognise register NZCV under target aarch64-none-elf

[luis.machado at arm dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=29471

Luis Machado <luis.machado at arm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
                 CC|                            |luis.machado at arm dot com
   Last reconfirmed|                            |2022-10-21
             Status|UNCONFIRMED                 |WAITING

--- Comment #1 from Luis Machado <luis.machado at arm dot com> ---
Hi Pete,

When dealing with bare metal, GDB gets its register set from the target. For
example, QEMU might not expose the Process State bits separately. It may be the
case that it packs everything into a synthetic CPSR register, as is shown in
your first post.

What debugging stub are you using for aarch64-none-elf? QEMU, openOCD etc?

-- 
You are receiving this mail because:
You are on the CC list for the bug.

[Bug gdb/29471] gdb 12.1 'i r' command doesn't recognise register NZCV under target aarch64-none-elf

[petemoore at gmx dot net]

https://sourceware.org/bugzilla/show_bug.cgi?id=29471

--- Comment #2 from Pete Moore <petemoore at gmx dot net> ---
Many thanks Luis!

In one shell, I am running Qemu 7.1.0 from homebrew on macOS, with:

```
$ qemu-system-aarch64 -s -S -M raspi3b -kernel [KERNEL-ELF-FILE] -serial null
-serial stdio
```

Then in a separate shell on my mac, I am running gdb under docker with:

```
$ docker run [...OPTIONS...] -ti [MY-DOCKER-IMAGE-CONTAINING-GDB]
/path/to/aarch64-none-elf-gdb [KERNEL-ELF-FILE]
(gdb) target extended-remote host.docker.internal:1234
...
```

It sounds like this is an issue with the Qemu gdb target then, and I should
raise this issue instead against Qemu 7.1.0 - is that correct?

Many thanks!
Pete

-- 
You are receiving this mail because:
You are on the CC list for the bug.

[Bug gdb/29471] gdb 12.1 'i r' command doesn't recognise register NZCV under target aarch64-none-elf

[luis.machado at arm dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=29471

--- Comment #3 from Luis Machado <luis.machado at arm dot com> ---
Hi Pete,

I don't think there is anything wrong with QEMU or GDB. You can find all the
bits you described in the CPSR.

The CPSR is described like so:

  <flags id="cpsr_flags" size="4">
    <!-- Stack Pointer.  -->
    <field name="SP" start="0" end="0"/>

    <!-- Exception Level.  -->
    <field name="EL" start="2" end="3"/>
    <!-- Execution state.  -->
    <field name="nRW" start="4" end="4"/>

    <!-- FIQ interrupt mask.  -->
    <field name="F" start="6" end="6"/>
    <!-- IRQ interrupt mask.  -->
    <field name="I" start="7" end="7"/>
    <!-- SError interrupt mask.  -->
    <field name="A" start="8" end="8"/>
    <!-- Debug exception mask.  -->
    <field name="D" start="9" end="9"/>

    <!-- ARMv8.5-A: Branch Target Identification BTYPE.  -->
    <field name="BTYPE" start="10" end="11"/>

    <!-- ARMv8.0-A: Speculative Store Bypass.  -->
    <field name="SSBS" start="12" end="12"/>

    <!-- Illegal Execution state.  -->
    <field name="IL" start="20" end="20"/>
    <!-- Software Step.  -->
    <field name="SS" start="21" end="21"/>
    <!-- ARMv8.1-A: Privileged Access Never.  -->
    <field name="PAN" start="22" end="22"/>
    <!-- ARMv8.2-A: User Access Override.  -->
    <field name="UAO" start="23" end="23"/>
    <!-- ARMv8.4-A: Data Independent Timing.  -->
    <field name="DIT" start="24" end="24"/>
    <!-- ARMv8.5-A: Tag Check Override.  -->
    <field name="TCO" start="25" end="25"/>

    <!-- Overflow Condition flag.  -->
    <field name="V" start="28" end="28"/>
    <!-- Carry Condition flag.  -->
    <field name="C" start="29" end="29"/>
    <!-- Zero Condition flag.  -->
    <field name="Z" start="30" end="30"/>
    <!-- Negative Condition flag.  -->
    <field name="N" start="31" end="31"/>
  </flags>
  <reg name="cpsr" bitsize="32" type="cpsr_flags"/>

For the 1-bit fields, GDB will show the field name if the bit is 1. Otherwise
nothing will be shown.

So in your example...

---
cpsr           0x200003cd          [ SP EL=3 F I A D BTYPE=0 C ]
---

You can see the various bits that are set. For fields with more than a single
bit, you will see the value, like BTYPE.

Does that clarify things?

-- 
You are receiving this mail because:
You are on the CC list for the bug.

[Bug gdb/29471] gdb 12.1 'i r' command doesn't recognise register NZCV under target aarch64-none-elf

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=29471

--- Comment #4 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Nick Clifton <nickc@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=fa6895ad35ebfa6a9e69808da0bae249d9b8a638

commit fa6895ad35ebfa6a9e69808da0bae249d9b8a638
Author: Nick Clifton <nickc@redhat.com>
Date:   Thu Nov 3 09:17:41 2022 +0000

    AVR Linker: Allow the start of the data region to specified on the command
line.

            PR 29471
            * scripttempl/avr.sc (__DATA_REGION_ORIGIN__): Define.  If a value
            has not been provided on the command line then use DATA_ORIGIN.
            (MEMORY): Use __DATA_REGION_ORIGIN__ as the start of the data
region.

-- 
You are receiving this mail because:
You are on the CC list for the bug.

[Bug gdb/29471] gdb 12.1 'i r' command doesn't recognise register NZCV under target aarch64-none-elf

[luis.machado at arm dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=29471

Luis Machado <luis.machado at arm dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |NOTABUG
             Status|WAITING                     |RESOLVED

--- Comment #5 from Luis Machado <luis.machado at arm dot com> ---
Please reopen if you see any other issues.

-- 
You are receiving this mail because:
You are on the CC list for the bug.