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From: "vapier at gentoo dot org" <sourceware-bugzilla@sourceware.org>
To: gdb-prs@sourceware.org
Subject: [Bug sim/29869] sim: align sim register numbers with gdb register numbers
Date: Mon, 25 Dec 2023 01:52:21 +0000	[thread overview]
Message-ID: <bug-29869-4717-InMmn0fbE5@http.sourceware.org/bugzilla/> (raw)
In-Reply-To: <bug-29869-4717@http.sourceware.org/bugzilla/>

https://sourceware.org/bugzilla/show_bug.cgi?id=29869

--- Comment #4 from Mike Frysinger <vapier at gentoo dot org> ---
on the sim side, the key is to start with CPU_REG_FETCH & CPU_REG_STORE.  those
set the callbacks for gdb to read/write registers via register number.

ports with sim headers:
aarch64 arm bfin cr16 d10v frv ft32 h8300 lm32 m32c ppc riscv rl78 rx sh

ports w/out gdb support so don't super care:
example-synacor mcore pru

ports that copy & paste register numbers between gdb & sim so they're the same:
avr (AVR_xxx_REGNUM)
bpf (BPF_Rxx)
iq2000 (xxx_REGNUM)
m32r (xxx_REGNUM) -- although it seems they aren't completely in sync
m68hc11 (xxx_REGNUM)
microblaze (NUM_REGS)
mn10300 (struct _state.regs & xxx_REGNUM)
moxie (struct moxie_regset.regs & xxx_REGNUM)
msp430 (struct msp430_cpu_state.regs & MSP430_xxx_REGNUM)
v850 (struct _v850_regs.regs & .sregs & E_xxx_REGNUM)

ports w/gdb port & w/out sim headers that i'm not sure if/how they work:
cris erc32(sparc) mips(many ISAs) or1k ppc

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  parent reply	other threads:[~2023-12-25  1:52 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-10 12:23 [Bug sim/29869] New: " vapier at gentoo dot org
2023-12-23 19:47 ` [Bug sim/29869] " tromey at sourceware dot org
2023-12-24  0:45 ` vapier at gentoo dot org
2023-12-24 20:11 ` tromey at sourceware dot org
2023-12-25  1:52 ` vapier at gentoo dot org [this message]
2023-12-29  1:35 ` tromey at sourceware dot org
2023-12-29  4:46 ` vapier at gentoo dot org
2023-12-31 22:44 ` tromey at sourceware dot org

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