[Bug sim/30494] New: ori x0, xn, imm decoded as incorrect instruction class

[Bug sim/30494] New: ori x0, xn, imm decoded as incorrect instruction class

[tommy_murphy at hotmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30494

            Bug ID: 30494
           Summary: ori x0, xn, imm decoded as incorrect instruction class
           Product: gdb
           Version: 12.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: sim
          Assignee: unassigned at sourceware dot org
          Reporter: tommy_murphy at hotmail dot com
                CC: vapier at gentoo dot org
  Target Milestone: ---

Originally discussed here:

https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1200

As far as I can see (and as outlined here:
https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1200#issuecomment-1451965016)
the ori x0, xn, imm instruction is getting decoded as the wrong class
(INSN_CLASS_ZBC_OR_ZBKC instead of INSN_CLASS_I) and the simulator terminates
with an UNHANDLED_EXTENSION message.

If any additional info is needed please let me know - thanks.

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[Bug sim/30494] riscv ori x0, xn, imm decoded as incorrect instruction class

[tommy_murphy at hotmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30494

Tommy Murphy <tommy_murphy at hotmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |riscv
            Summary|ori x0, xn, imm decoded as  |riscv ori x0, xn, imm
                   |incorrect instruction class |decoded as incorrect
                   |                            |instruction class
                URL|                            |https://github.com/riscv-co
                   |                            |llab/riscv-gnu-toolchain/is
                   |                            |sues/1200

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[Bug sim/30494] [RISCV] ori x0, xn, imm decoded as incorrect instruction class causing sim to terminate

[tommy_murphy at hotmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30494

Tommy Murphy <tommy_murphy at hotmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|riscv ori x0, xn, imm       |[RISCV] ori x0, xn, imm
                   |decoded as incorrect        |decoded as incorrect
                   |instruction class           |instruction class causing
                   |                            |sim to terminate

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[Bug sim/30494] [RISCV] ori x0, xn, imm decoded as incorrect instruction class causing sim to terminate

[tommy_murphy at hotmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30494

Tommy Murphy <tommy_murphy at hotmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |tommy_murphy at hotmail dot com

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[Bug sim/30494] [RISCV] ori x0, xn, imm decoded as incorrect instruction class causing sim to terminate

[tromey at sourceware dot org]

https://sourceware.org/bugzilla/show_bug.cgi?id=30494

Tom Tromey <tromey at sourceware dot org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |tromey at sourceware dot org

--- Comment #1 from Tom Tromey <tromey at sourceware dot org> ---
I suspect this is more of a libopcodes bug than a sim bug.
Not sure which component is right for libopcodes though.
I'd say the binutils product but I don't see a libopcodes component.

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[Bug sim/30494] [RISCV] ori x0, xn, imm decoded as incorrect instruction class causing sim to terminate

[tommy_murphy at hotmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30494

Tommy Murphy <tommy_murphy at hotmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |INVALID

--- Comment #2 from Tommy Murphy <tommy_murphy at hotmail dot com> ---
Hi Tom - thanks for the reply. Looks like libopcodes bugs should be logged
against binutils alright:

https://sourceware.org/bugzilla/buglist.cgi?bug_status=UNCONFIRMED&bug_status=NEW&bug_status=ASSIGNED&bug_status=SUSPENDED&bug_status=WAITING&bug_status=REOPENED&list_id=75317&product=binutils&query_format=advanced&short_desc=libopcodes&short_desc_type=allwordssubstr

I'll log it there instead and close this one. 

Thanks again.
Regards
Tommy

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[Bug sim/30494] [RISCV] ori x0, xn, imm decoded as incorrect instruction class causing sim to terminate

[tommy_murphy at hotmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=30494

--- Comment #3 from Tommy Murphy <tommy_murphy at hotmail dot com> ---
Logged against binutils/libopcodes here:

https://sourceware.org/bugzilla/show_bug.cgi?id=30495

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