* Fwd: [RFA] Fix for mcore simulator [not found] <1d854df9-b28c-41eb-af7c-e3a423885558@gmail.com> @ 2023-10-05 16:09 ` Jeff Law 2023-10-10 17:21 ` Tom Tromey 2023-10-10 21:35 ` Martin Simmons 0 siblings, 2 replies; 4+ messages in thread From: Jeff Law @ 2023-10-05 16:09 UTC (permalink / raw) To: gdb [-- Attachment #1: Type: text/plain, Size: 1395 bytes --] Wrongly sent to binutils initially... -------- Forwarded Message -------- Subject: [RFA] Fix for mcore simulator Date: Wed, 4 Oct 2023 16:09:35 -0600 From: Jeff Law <jeffreyalaw@gmail.com> To: Binutils <binutils@sourceware.org> I was looking for cases where a GCC patch under evaluation would cause test results to change. Quite surprisingly the mcore-elf port showed test differences. After a fair amount of digging my conclusion was the sequences before/after the patch should have been semantically the same. Of course if the code is supposed to behave the same, then that points to problems elsewhere (assembler, linker, simulator). Sure enough the mcore simulator was mis-handling the sign extension instructions. The simulator implementation of sextb is via paired shift-by-24 operations. Similarly the simulator implements sexth via paired shift-by-16 operations. The temporary holding the value was declared as a "long" thus this approach worked fine for hosts with a 32 bit wide long and failed miserably for hosts with a 64 bit wide long. This patch makes the shift count automatically adjust based on the size of the temporary. It includes a simple test for sextb and sexth. I have _not_ done a full audit of the mcore simulator for more 32->64 bit issues. This also fixes 443 execution tests in the GCC testsuite ;-) OK for the trunk? Thanks, Jeff [-- Attachment #2: mcore-sim.patch --] [-- Type: text/plain, Size: 1714 bytes --] diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 53cfdad050b..48d9ff8645a 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -641,8 +641,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) { long tmp; tmp = gr[RD]; - tmp <<= 24; - tmp >>= 24; + tmp <<= (sizeof (tmp) * 8) - 8; + tmp >>= (sizeof (tmp) * 8) - 8; gr[RD] = tmp; } break; @@ -653,8 +653,8 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) { long tmp; tmp = gr[RD]; - tmp <<= 16; - tmp >>= 16; + tmp <<= (sizeof (tmp) * 8) - 16; + tmp >>= (sizeof (tmp) * 8) - 16; gr[RD] = tmp; } break; diff --git a/sim/testsuite/mcore/sextb.s b/sim/testsuite/mcore/sextb.s new file mode 100644 index 00000000000..5500f7abe67 --- /dev/null +++ b/sim/testsuite/mcore/sextb.s @@ -0,0 +1,25 @@ +# check that sext.b/sext.h work correctly +# mach: mcore + +.include "testutils.inc" + + start + # Construct -120 using bgeni+addi+sext + bgeni r2, 7 + addi r2,8 + sextb r2 + + # Construct -120 using movi+not + movi r7,119 + not r7 + + # Compare them, they should be equal + cmpne r2,r7 + jbt .L1 + pass +.L1: + fail + + + + diff --git a/sim/testsuite/mcore/sexth.s b/sim/testsuite/mcore/sexth.s new file mode 100644 index 00000000000..97279c49ed4 --- /dev/null +++ b/sim/testsuite/mcore/sexth.s @@ -0,0 +1,27 @@ +# check that sext.b/sext.h work correctly +# mach: mcore + +.include "testutils.inc" + + start + # Construct -32760 using bgeni+addi+sext + bgeni r2, 15 + addi r2,8 + sexth r2 + + # Construct -32760 using bmask+subi+not + bmaski r7,15 + subi r7,8 // 32759 0x7ff7 + not r7 + + + # Compare them, they should be equal + cmpne r2,r7 + jbt .L1 + pass +.L1: + fail + + + + ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Fwd: [RFA] Fix for mcore simulator 2023-10-05 16:09 ` Fwd: [RFA] Fix for mcore simulator Jeff Law @ 2023-10-10 17:21 ` Tom Tromey 2023-10-10 21:35 ` Martin Simmons 1 sibling, 0 replies; 4+ messages in thread From: Tom Tromey @ 2023-10-10 17:21 UTC (permalink / raw) To: Jeff Law via Gdb; +Cc: Jeff Law >>>>> "Jeff" == Jeff Law via Gdb <gdb@sourceware.org> writes: Jeff> Wrongly sent to binutils initially... Thanks, this is ok. Tom ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Fwd: [RFA] Fix for mcore simulator 2023-10-05 16:09 ` Fwd: [RFA] Fix for mcore simulator Jeff Law 2023-10-10 17:21 ` Tom Tromey @ 2023-10-10 21:35 ` Martin Simmons 2023-10-11 16:49 ` Jeff Law 1 sibling, 1 reply; 4+ messages in thread From: Martin Simmons @ 2023-10-10 21:35 UTC (permalink / raw) To: Jeff Law; +Cc: gdb >>>>> On Thu, 5 Oct 2023 10:09:44 -0600, Jeff Law via Gdb said: > > Of course if the code is supposed to behave the same, then that points > to problems elsewhere (assembler, linker, simulator). Sure enough the > mcore simulator was mis-handling the sign extension instructions. The > simulator implementation of sextb is via paired shift-by-24 operations. > Similarly the simulator implements sexth via paired shift-by-16 operations. > > The temporary holding the value was declared as a "long" thus this > approach worked fine for hosts with a 32 bit wide long and failed > miserably for hosts with a 64 bit wide long. > > This patch makes the shift count automatically adjust based on the size > of the temporary. It includes a simple test for sextb and sexth. I > have _not_ done a full audit of the mcore simulator for more 32->64 bit > issues. The use of long seems bogus to me. Why not just declare tmp as int32_t? __Martin ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Fwd: [RFA] Fix for mcore simulator 2023-10-10 21:35 ` Martin Simmons @ 2023-10-11 16:49 ` Jeff Law 0 siblings, 0 replies; 4+ messages in thread From: Jeff Law @ 2023-10-11 16:49 UTC (permalink / raw) To: Martin Simmons; +Cc: gdb On 10/10/23 15:35, Martin Simmons wrote: >>>>>> On Thu, 5 Oct 2023 10:09:44 -0600, Jeff Law via Gdb said: >> >> Of course if the code is supposed to behave the same, then that points >> to problems elsewhere (assembler, linker, simulator). Sure enough the >> mcore simulator was mis-handling the sign extension instructions. The >> simulator implementation of sextb is via paired shift-by-24 operations. >> Similarly the simulator implements sexth via paired shift-by-16 operations. >> >> The temporary holding the value was declared as a "long" thus this >> approach worked fine for hosts with a 32 bit wide long and failed >> miserably for hosts with a 64 bit wide long. >> >> This patch makes the shift count automatically adjust based on the size >> of the temporary. It includes a simple test for sextb and sexth. I >> have _not_ done a full audit of the mcore simulator for more 32->64 bit >> issues. > > The use of long seems bogus to me. Why not just declare tmp as int32_t? That code likely predates any modernization efforts in gdbsim and binutils-gdb as a whole -- it's the old interp style simulator that was common in the 90s. I wouldn't lose any sleep if someone took up that task (modernizing that codebase) but my interest in mcore is essentially zero, so it won't be me. Jeff ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-10-11 16:49 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- [not found] <1d854df9-b28c-41eb-af7c-e3a423885558@gmail.com> 2023-10-05 16:09 ` Fwd: [RFA] Fix for mcore simulator Jeff Law 2023-10-10 17:21 ` Tom Tromey 2023-10-10 21:35 ` Martin Simmons 2023-10-11 16:49 ` Jeff Law
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