[Bug libc/28033] New: Need to check RTM_ALWAYS_ABORT for RTM

[Bug libc/28033] New: Need to check RTM_ALWAYS_ABORT for RTM

[hjl.tools at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

            Bug ID: 28033
           Summary: Need to check RTM_ALWAYS_ABORT for RTM
           Product: glibc
           Version: 2.34
            Status: NEW
          Severity: normal
          Priority: P2
         Component: libc
          Assignee: unassigned at sourceware dot org
          Reporter: hjl.tools at gmail dot com
                CC: drepper.fsp at gmail dot com
  Target Milestone: ---
            Target: i386,x86-64

From

https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated,
which is set to indicate to updated software that the loaded microcode is
forcing RTM abort.

We need to check RTM_ALWAYS_ABORT to verify that if RTM is usable.

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[Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

--- Comment #1 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by H.J. Lu <hjl@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=ea8e465a6b8d0f26c72bcbe453a854de3abf68ec

commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 30 10:47:06 2021 -0700

    x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]

    From

   
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

    * Intel TSX will be disabled by default.
    * The processor will force abort all Restricted Transactional Memory (RTM)
      transactions by default.
    * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be
enumerated,
      which is set to indicate to updated software that the loaded microcode is
      forcing RTM abort.
    * On processors that enumerate support for RTM, the CPUID enumeration bits
      for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
      be set by default after microcode update.
    * Workloads that were benefited from Intel TSX might experience a change
      in performance.
    * System software may use a new bit in Model-Specific Register (MSR) 0x10F
      TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
      Elision (HLE) and RTM bits to indicate to software that Intel TSX is
      disabled.

    1. Add RTM_ALWAYS_ABORT to CPUID features.
    2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.  This skips the
    string/tst-memchr-rtm etc. testcases on the affected processors, which
    always fail after a microcde update.
    3. Check RTM feature, instead of usability, against /proc/cpuinfo.

    This fixes BZ #28033.

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[Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM

[hjl.tools at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

H.J. Lu <hjl.tools at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
   Target Milestone|---                         |2.34
             Status|NEW                         |RESOLVED

--- Comment #2 from H.J. Lu <hjl.tools at gmail dot com> ---
Fixed for 2.34.

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[Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

--- Comment #3 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The release/2.33/master branch has been updated by H.J. Lu
<hjl@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=0a5f5e2dc1223c1defd6421c0cceb12883d5ad07

commit 0a5f5e2dc1223c1defd6421c0cceb12883d5ad07
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 30 10:47:06 2021 -0700

    x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]

    From

   
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

    * Intel TSX will be disabled by default.
    * The processor will force abort all Restricted Transactional Memory (RTM)
      transactions by default.
    * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be
enumerated,
      which is set to indicate to updated software that the loaded microcode is
      forcing RTM abort.
    * On processors that enumerate support for RTM, the CPUID enumeration bits
      for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
      be set by default after microcode update.
    * Workloads that were benefited from Intel TSX might experience a change
      in performance.
    * System software may use a new bit in Model-Specific Register (MSR) 0x10F
      TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
      Elision (HLE) and RTM bits to indicate to software that Intel TSX is
      disabled.

    1. Add RTM_ALWAYS_ABORT to CPUID features.
    2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.  This skips the
    string/tst-memchr-rtm etc. testcases on the affected processors, which
    always fail after a microcde update.
    3. Check RTM feature, instead of usability, against /proc/cpuinfo.

    This fixes BZ #28033.

    (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec)

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[Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

--- Comment #4 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The release/2.32/master branch has been updated by H.J. Lu
<hjl@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=77317b3b0df3170575e135be01e9554261c43b8a

commit 77317b3b0df3170575e135be01e9554261c43b8a
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 30 10:47:06 2021 -0700

    x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]

    From

   
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

    * Intel TSX will be disabled by default.
    * The processor will force abort all Restricted Transactional Memory (RTM)
      transactions by default.
    * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be
enumerated,
      which is set to indicate to updated software that the loaded microcode is
      forcing RTM abort.
    * On processors that enumerate support for RTM, the CPUID enumeration bits
      for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
      be set by default after microcode update.
    * Workloads that were benefited from Intel TSX might experience a change
      in performance.
    * System software may use a new bit in Model-Specific Register (MSR) 0x10F
      TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
      Elision (HLE) and RTM bits to indicate to software that Intel TSX is
      disabled.

    1. Add RTM_ALWAYS_ABORT to CPUID features.
    2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.  This skips the
    string/tst-memchr-rtm etc. testcases on the affected processors, which
    always fail after a microcde update.
    3. Check RTM feature, instead of usability, against /proc/cpuinfo.

    This fixes BZ #28033.

    (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec)

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[Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

--- Comment #5 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The release/2.31/master branch has been updated by H.J. Lu
<hjl@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=5b99f172b839da968bd7223f03a985503bccf485

commit 5b99f172b839da968bd7223f03a985503bccf485
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 30 10:47:06 2021 -0700

    x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]

    From

   
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

    * Intel TSX will be disabled by default.
    * The processor will force abort all Restricted Transactional Memory (RTM)
      transactions by default.
    * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be
enumerated,
      which is set to indicate to updated software that the loaded microcode is
      forcing RTM abort.
    * On processors that enumerate support for RTM, the CPUID enumeration bits
      for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
      be set by default after microcode update.
    * Workloads that were benefited from Intel TSX might experience a change
      in performance.
    * System software may use a new bit in Model-Specific Register (MSR) 0x10F
      TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
      Elision (HLE) and RTM bits to indicate to software that Intel TSX is
      disabled.

    1. Add RTM_ALWAYS_ABORT to CPUID features.
    2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.  This skips the
    string/tst-memchr-rtm etc. testcases on the affected processors, which
    always fail after a microcde update.
    3. Check RTM feature, instead of usability, against /proc/cpuinfo.

    This fixes BZ #28033.

    (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec)

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[Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

--- Comment #6 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The release/2.30/master branch has been updated by H.J. Lu
<hjl@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=071e2bdd850de9387b22b387f5f42e5c7d6668de

commit 071e2bdd850de9387b22b387f5f42e5c7d6668de
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 30 10:47:06 2021 -0700

    x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]

    From

   
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

    * Intel TSX will be disabled by default.
    * The processor will force abort all Restricted Transactional Memory (RTM)
      transactions by default.
    * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be
enumerated,
      which is set to indicate to updated software that the loaded microcode is
      forcing RTM abort.
    * On processors that enumerate support for RTM, the CPUID enumeration bits
      for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
      be set by default after microcode update.
    * Workloads that were benefited from Intel TSX might experience a change
      in performance.
    * System software may use a new bit in Model-Specific Register (MSR) 0x10F
      TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
      Elision (HLE) and RTM bits to indicate to software that Intel TSX is
      disabled.

    1. Add RTM_ALWAYS_ABORT to CPUID features.
    2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.  This skips the
    string/tst-memchr-rtm etc. testcases on the affected processors, which
    always fail after a microcde update.
    3. Check RTM feature, instead of usability, against /proc/cpuinfo.

    This fixes BZ #28033.

    (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec)

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[Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

--- Comment #7 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The release/2.29/master branch has been updated by H.J. Lu
<hjl@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=7aac95739a505aad7427d98bcf20396bba561672

commit 7aac95739a505aad7427d98bcf20396bba561672
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 30 10:47:06 2021 -0700

    x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]

    From

   
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

    * Intel TSX will be disabled by default.
    * The processor will force abort all Restricted Transactional Memory (RTM)
      transactions by default.
    * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be
enumerated,
      which is set to indicate to updated software that the loaded microcode is
      forcing RTM abort.
    * On processors that enumerate support for RTM, the CPUID enumeration bits
      for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
      be set by default after microcode update.
    * Workloads that were benefited from Intel TSX might experience a change
      in performance.
    * System software may use a new bit in Model-Specific Register (MSR) 0x10F
      TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
      Elision (HLE) and RTM bits to indicate to software that Intel TSX is
      disabled.

    1. Add RTM_ALWAYS_ABORT to CPUID features.
    2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.  This skips the
    string/tst-memchr-rtm etc. testcases on the affected processors, which
    always fail after a microcde update.
    3. Check RTM feature, instead of usability, against /proc/cpuinfo.

    This fixes BZ #28033.

    (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec)

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[Bug libc/28033] Need to check RTM_ALWAYS_ABORT for RTM

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=28033

--- Comment #8 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot gnu.org> ---
The release/2.28/master branch has been updated by H.J. Lu
<hjl@sourceware.org>:

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=277331ee2131f9972e4f7a7bbc78ed32920647e7

commit 277331ee2131f9972e4f7a7bbc78ed32920647e7
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Wed Jun 30 10:47:06 2021 -0700

    x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]

    From

   
https://www.intel.com/content/www/us/en/support/articles/000059422/processors.html

    * Intel TSX will be disabled by default.
    * The processor will force abort all Restricted Transactional Memory (RTM)
      transactions by default.
    * A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be
enumerated,
      which is set to indicate to updated software that the loaded microcode is
      forcing RTM abort.
    * On processors that enumerate support for RTM, the CPUID enumeration bits
      for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to
      be set by default after microcode update.
    * Workloads that were benefited from Intel TSX might experience a change
      in performance.
    * System software may use a new bit in Model-Specific Register (MSR) 0x10F
      TSX_FORCE_ABORT[TSX_CPUID_CLEAR] functionality to clear the Hardware Lock
      Elision (HLE) and RTM bits to indicate to software that Intel TSX is
      disabled.

    1. Add RTM_ALWAYS_ABORT to CPUID features.
    2. Set RTM usable only if RTM_ALWAYS_ABORT isn't set.  This skips the
    string/tst-memchr-rtm etc. testcases on the affected processors, which
    always fail after a microcde update.
    3. Check RTM feature, instead of usability, against /proc/cpuinfo.

    This fixes BZ #28033.

    (cherry picked from commit ea8e465a6b8d0f26c72bcbe453a854de3abf68ec)

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