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From: "danglin at gcc dot gnu.org" <sourceware-bugzilla@sourceware.org>
To: glibc-bugs@sourceware.org
Subject: [Bug libc/29537] [2.34 regression]: Alignment issue on m68k when using futexes on qemu-user
Date: Fri, 16 Sep 2022 15:39:15 +0000	[thread overview]
Message-ID: <bug-29537-131-TvcQtb883g@http.sourceware.org/bugzilla/> (raw)
In-Reply-To: <bug-29537-131@http.sourceware.org/bugzilla/>

https://sourceware.org/bugzilla/show_bug.cgi?id=29537

John David Anglin <danglin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |danglin at gcc dot gnu.org

--- Comment #8 from John David Anglin <danglin at gcc dot gnu.org> ---
(In reply to Carlos O'Donell from comment #3)
> > > Since __LOCK_ALIGNMENT is defined per architecture if required.  The HPPA
> > also requires a 16-byte alignment for locks, although it is just a
> > historical artifact to keep compatibility with old implementation.
> 
> If an architecture needs higher alignment for locks then I strongly suggest
> out-of-line locking in the kernel as we did for parisc. We have an array of
> locks that we use to scale the futex locking operations. We pick a lock
> based on the low-bit hash of the futex address, and we use that consistently
> in our kernel helper (kernel aided emulation of compare-and-swap) and inside
> the kernel. This yields a consistent behaviour on SMP where the userspace
> CAS uses the same set of lock words for the address as the kernel-side futex
> CAS. Those lock words are 16-byte aligned because only load-and-clear-word
> (ldcw) exists on parisc and requires the extra alignment for the hardware
> atomicity to hold.

I just want to say that the parisc CAS implementation is subtle and it took
years to get it right. Page faults need to be disabled around the CAS
operation. Some mechanism is needed to handle COW breaks in the kernel outside
the critical region. Fortunately, parisc has a stby,e instruction. When the
effective address addresses the leftmost byte of a word, it does not write to
the effective address but it triggers all the exceptions that a write would.
Thus, it can be used to trigger a COW break without actually writing to memory.

Having a 16-byte alignment for locks is somewhat problematic. Malloc data is
over aligned and this causes problems for some packages which check alignment.

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  parent reply	other threads:[~2022-09-16 15:39 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-30  7:30 [Bug libc/29537] New: " glaubitz at physik dot fu-berlin.de
2022-08-30  7:44 ` [Bug libc/29537] " glaubitz at physik dot fu-berlin.de
2022-08-30  7:49 ` dilfridge at gentoo dot org
2022-08-30  7:55 ` chewi at gentoo dot org
2022-08-30  9:15 ` glaubitz at physik dot fu-berlin.de
2022-08-30 13:18 ` adhemerval.zanella at linaro dot org
2022-08-30 14:16 ` carlos at redhat dot com
2022-08-30 14:33 ` schwab@linux-m68k.org
2022-08-30 14:35 ` adhemerval.zanella at linaro dot org
2022-08-30 15:01 ` carlos at redhat dot com
2022-08-30 15:58 ` sam at gentoo dot org
2022-09-02 10:31 ` dilfridge at gentoo dot org
2022-09-16 15:39 ` danglin at gcc dot gnu.org [this message]
2022-09-20 16:48 ` adhemerval.zanella at linaro dot org
2022-09-21  9:43 ` glaubitz at physik dot fu-berlin.de
2022-09-21 13:47 ` adhemerval.zanella at linaro dot org

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