[Bug libc/29537] [2.34 regression]: Alignment issue on m68k when using futexes on qemu-user

["adhemerval.zanella at linaro dot org" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=29537

--- Comment #5 from Adhemerval Zanella <adhemerval.zanella at linaro dot org> ---
(In reply to Carlos O'Donell from comment #3)
> (In reply to Adhemerval Zanella from comment #2)
> > It seems a real issue, but I am puzzled why we have not see any issue so
> > far. I take mostly runs were done in single-core, where hardware did not
> > enforce 32-bit alignment with atomic operations.
> > 
> > A better change would be to use:
> > 
> > diff --git a/sysdeps/nptl/libc-lockP.h b/sysdeps/nptl/libc-lockP.h
> > index d3a6837fd2..9efe962588 100644
> > --- a/sysdeps/nptl/libc-lockP.h
> > +++ b/sysdeps/nptl/libc-lockP.h
> > @@ -34,7 +34,7 @@
> >  #include <tls.h>
> > 
> >  /* Mutex type.  */
> > -typedef int __libc_lock_t;
> > +typedef int __libc_lock_t __LOCK_ALIGNMENT;
> >  typedef struct { pthread_mutex_t mutex; } __rtld_lock_recursive_t;
> >  typedef pthread_rwlock_t __libc_rwlock_t;
> 
> Does this impact any externally visible ABIs?
>  
> > Since __LOCK_ALIGNMENT is defined per architecture if required.  The HPPA
> > also requires a 16-byte alignment for locks, although it is just a
> > historical artifact to keep compatibility with old implementation.
> 
> If an architecture needs higher alignment for locks then I strongly suggest
> out-of-line locking in the kernel as we did for parisc. We have an array of
> locks that we use to scale the futex locking operations. We pick a lock
> based on the low-bit hash of the futex address, and we use that consistently
> in our kernel helper (kernel aided emulation of compare-and-swap) and inside
> the kernel. This yields a consistent behaviour on SMP where the userspace
> CAS uses the same set of lock words for the address as the kernel-side futex
> CAS. Those lock words are 16-byte aligned because only load-and-clear-word
> (ldcw) exists on parisc and requires the extra alignment for the hardware
> atomicity to hold.

I was not aware of HPPA limitation, it seems that we will need to propagate it
to internal locks as well.  

The m68k issues, afaiu, is different because int has a 2-byte alignment on
m68k:

$ cat test.c
_Static_assert (_Alignof (int) == 4, "_Alignof (int) != 4");
$ x86_64-linux-gnu-gcc test.c -c
$
/home/azanella/toolchain/install/compilers/m68k-linux-gnu/bin/m68k-glibc-linux-gnu-gcc
test.c -c
test.c:1:1: error: static assertion failed: "_Alignof (int) != 4"
    1 | _Static_assert (_Alignof (int) == 4, "_Alignof (int) != 4");
      | ^~~~~~~~~~~~~~

And futex syscall enforces 4-bytes alignments for the input addresses (as
Andreas noted).

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