[Bug libc/30643] Missing cache information on x86-64 under Intel TDX

["fweimer at redhat dot com" <sourceware-bugzilla@sourceware.org>]

https://sourceware.org/bugzilla/show_bug.cgi?id=30643

Florian Weimer <fweimer at redhat dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |fweimer at redhat dot com

--- Comment #1 from Florian Weimer <fweimer at redhat dot com> ---
Raised on libc-alpha and elsewhere:

Missing cache information on x86-64 under Intel TDX (glibc bug 30643)
<https://sourceware.org/pipermail/libc-alpha/2023-July/150115.html>

This quick hack produces more reasonable values:

# bash testrun.sh posix/getconf -a | grep CACHE
LEVEL1_ICACHE_SIZE                 32768
LEVEL1_ICACHE_ASSOC                
LEVEL1_ICACHE_LINESIZE             64
LEVEL1_DCACHE_SIZE                 49152
LEVEL1_DCACHE_ASSOC                12
LEVEL1_DCACHE_LINESIZE             64
LEVEL2_CACHE_SIZE                  2097152
LEVEL2_CACHE_ASSOC                 16
LEVEL2_CACHE_LINESIZE              64
LEVEL3_CACHE_SIZE                  110100480
LEVEL3_CACHE_ASSOC                 15
LEVEL3_CACHE_LINESIZE              64
LEVEL4_CACHE_SIZE                  0
LEVEL4_CACHE_ASSOC                 
LEVEL4_CACHE_LINESIZE              

diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
index c98fa57a..814a314b 100644
--- a/sysdeps/x86/dl-cacheinfo.h
+++ b/sysdeps/x86/dl-cacheinfo.h
@@ -271,6 +271,10 @@ handle_intel (int name, const struct cpu_features
*cpu_features)
       unsigned int edx;
       __cpuid (2, eax, ebx, ecx, edx);

+      if (eax == 0 && ebx == 0 && ecx == 0 && edx == 0)
+       /* Redirect to other information source for Intel TDX.  */
+       eax = 0xff;
+
       /* The low byte of EAX in the first round contain the number of
         rounds we have to make.  At least one, the one we are already
         doing.  */

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