[glibc] AArch64: Reset HWCAP2_AFP bits in FPCR for default fenv

[glibc] AArch64: Reset HWCAP2_AFP bits in FPCR for default fenv

[Szabolcs Nagy]

https://sourceware.org/git/gitweb.cgi?p=glibc.git;h=05844d18f7893bf96965f163c428214fd5ebe10a

commit 05844d18f7893bf96965f163c428214fd5ebe10a
Author: Tejas Belagod <Tejas.Belagod@arm.com>
Date:   Tue Jul 5 11:35:24 2022 +0100

    AArch64: Reset HWCAP2_AFP bits in FPCR for default fenv
    
    The AFP feature (Alternate floating-point behavior) was added in armv8.7 and
    introduced new FPCR bits.
    
    Currently, HWCAP2_AFP bits (bit 0, 1, 2) in FPCR are preserved when fenv is
    set to default environment.  This is a deviation from standard behaviour.
    Clear these bits when setting the fenv to default.
    
    There is no libc API to modify the new FPCR bits.  Restoring those bits matters
    if the user changed them directly.

Diff:
---
 sysdeps/aarch64/fpu/fpu_control.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sysdeps/aarch64/fpu/fpu_control.h b/sysdeps/aarch64/fpu/fpu_control.h
index 764ed5cdbb..429f4910e7 100644
--- a/sysdeps/aarch64/fpu/fpu_control.h
+++ b/sysdeps/aarch64/fpu/fpu_control.h
@@ -46,7 +46,7 @@
    contents. These two masks indicate which bits in each of FPCR and
    FPSR should not be changed.  */
 
-#define _FPU_RESERVED		0xfe0fe0ff
+#define _FPU_RESERVED		0xfe0fe0f8
 #define _FPU_FPSR_RESERVED	0x0fffffe0
 
 #define _FPU_DEFAULT		0x00000000