* [PATCH 2/2] S390: Use generic spinlock code.
2016-12-16 16:32 [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros Stefan Liebler
@ 2016-12-16 16:32 ` Stefan Liebler
2017-02-08 14:49 ` Stefan Liebler
2016-12-19 12:14 ` [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros Szabolcs Nagy
1 sibling, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2016-12-16 16:32 UTC (permalink / raw)
To: libc-alpha; +Cc: Stefan Liebler
This patch removes the s390 specific implementation of spinlock code
and is now using the generic one.
For pthread_spin_trylock an explicit load and test before executing
compare and swap instruction is done as it is an interlock update even
if the lock is already acquired.
ChangeLog:
* sysdeps/s390/nptl/pthread_spin_init.c: Delete File.
* sysdeps/s390/nptl/pthread_spin_unlock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_lock.c:
(SPIN_LOCK_READS_BETWEEN_CMPXCHG): New define.
Use generic spinlock code.
* sysdeps/s390/nptl/pthread_spin_trylock.c:
(SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG): New define.
Use generic spinlock code.
---
sysdeps/s390/nptl/pthread_spin_init.c | 19 -------------------
sysdeps/s390/nptl/pthread_spin_lock.c | 18 +++++-------------
sysdeps/s390/nptl/pthread_spin_trylock.c | 18 +++++-------------
sysdeps/s390/nptl/pthread_spin_unlock.c | 32 --------------------------------
4 files changed, 10 insertions(+), 77 deletions(-)
delete mode 100644 sysdeps/s390/nptl/pthread_spin_init.c
delete mode 100644 sysdeps/s390/nptl/pthread_spin_unlock.c
diff --git a/sysdeps/s390/nptl/pthread_spin_init.c b/sysdeps/s390/nptl/pthread_spin_init.c
deleted file mode 100644
index 7d3568f..0000000
--- a/sysdeps/s390/nptl/pthread_spin_init.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright (C) 2003-2016 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Not needed. pthread_spin_init is an alias for pthread_spin_unlock. */
diff --git a/sysdeps/s390/nptl/pthread_spin_lock.c b/sysdeps/s390/nptl/pthread_spin_lock.c
index def6a24..d99cd81 100644
--- a/sysdeps/s390/nptl/pthread_spin_lock.c
+++ b/sysdeps/s390/nptl/pthread_spin_lock.c
@@ -16,17 +16,9 @@
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
-#include "pthreadP.h"
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-int
-pthread_spin_lock (pthread_spinlock_t *lock)
-{
- int oldval;
-
- __asm__ __volatile__ ("0: lhi %0,0\n"
- " cs %0,%2,%1\n"
- " jl 0b"
- : "=&d" (oldval), "=Q" (*lock)
- : "d" (1), "m" (*lock) : "cc" );
- return 0;
-}
+/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
+ it will resolve to this very file. Using "sysdeps/.." as reference to the
+ top level directory does the job. */
+#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/s390/nptl/pthread_spin_trylock.c b/sysdeps/s390/nptl/pthread_spin_trylock.c
index 4c00e08..d7a2089 100644
--- a/sysdeps/s390/nptl/pthread_spin_trylock.c
+++ b/sysdeps/s390/nptl/pthread_spin_trylock.c
@@ -16,17 +16,9 @@
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
-#include <errno.h>
-#include "pthreadP.h"
+#define SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG 1
-int
-pthread_spin_trylock (pthread_spinlock_t *lock)
-{
- int old;
-
- __asm__ __volatile__ ("cs %0,%3,%1"
- : "=d" (old), "=Q" (*lock)
- : "0" (0), "d" (1), "m" (*lock) : "cc" );
-
- return old != 0 ? EBUSY : 0;
-}
+/* We can't use the normal "#include <nptl/pthread_spin_trylock.c>" because
+ it will resolve to this very file. Using "sysdeps/.." as reference to the
+ top level directory does the job. */
+#include <sysdeps/../nptl/pthread_spin_trylock.c>
diff --git a/sysdeps/s390/nptl/pthread_spin_unlock.c b/sysdeps/s390/nptl/pthread_spin_unlock.c
deleted file mode 100644
index 0dcc2d0..0000000
--- a/sysdeps/s390/nptl/pthread_spin_unlock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (C) 2003-2016 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Ugly hack to avoid the declaration of pthread_spin_init. */
-#define pthread_spin_init pthread_spin_init_XXX
-#include "pthreadP.h"
-#undef pthread_spin_init
-
-int
-pthread_spin_unlock (pthread_spinlock_t *lock)
-{
- __asm__ __volatile__ (" xc %O0(4,%R0),%0\n"
- " bcr 15,0"
- : "=Q" (*lock) : "m" (*lock) : "cc" );
- return 0;
-}
-strong_alias (pthread_spin_unlock, pthread_spin_init)
--
2.3.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
@ 2016-12-16 16:32 Stefan Liebler
2016-12-16 16:32 ` [PATCH 2/2] S390: Use generic spinlock code Stefan Liebler
2016-12-19 12:14 ` [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros Szabolcs Nagy
0 siblings, 2 replies; 63+ messages in thread
From: Stefan Liebler @ 2016-12-16 16:32 UTC (permalink / raw)
To: libc-alpha; +Cc: Stefan Liebler
This patch optimizes the generic spinlock code.
The type pthread_spinlock_t is a typedef to volatile int on all archs.
Passing a volatile pointer to the atomic macros can lead to extra stores
and loads to stack if such a macro creates a temporary variable by using
__typeof (*(mem)). Thus the patch passes a int pointer to the atomic macros.
The atomic macros are replaced by the C11 like atomic macros and thus
the code is aligned to it.
I've added a glibc_likely hint to the first atomic exchange in
pthread_spin_lock in order to return immediately to caller if lock is free.
Without the hint, there is an additional jump if lock is free.
I've added the atomic_spin_nop macro within the loop of plain reads.
The plain reads are realized by dereferencing the volatile pointer
as the for-loop was optimized out with atomic_load_relaxed.
For pthread_spin_trylock, a machine-specific version can define
SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG to 1 if an explicit test if
lock is free is optimal.
ChangeLog:
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros and pass int pointers instead of
volatile int pointers.
* nptl/pthread_spin_trylock.c
(pthread_spin_trylock): Likewise. Use an explicit test if lock
is free, if new SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG macro
is set to one.
(SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG): New define.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
---
nptl/pthread_spin_init.c | 4 +++-
nptl/pthread_spin_lock.c | 54 +++++++++++++++++++++++++++++++++++----------
nptl/pthread_spin_trylock.c | 29 ++++++++++++++++++++++--
nptl/pthread_spin_unlock.c | 6 +++--
4 files changed, 76 insertions(+), 17 deletions(-)
diff --git a/nptl/pthread_spin_init.c b/nptl/pthread_spin_init.c
index 8ed4772..65d05b8 100644
--- a/nptl/pthread_spin_init.c
+++ b/nptl/pthread_spin_init.c
@@ -22,6 +22,8 @@
int
pthread_spin_init (pthread_spinlock_t *lock, int pshared)
{
- *lock = 0;
+ /* The atomic_store_relaxed is enough as we only initialize the spinlock here
+ and we are not in a critical region. */
+ atomic_store_relaxed (lock, 0);
return 0;
}
diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
index fb9bcc1..adbc9d7 100644
--- a/nptl/pthread_spin_lock.c
+++ b/nptl/pthread_spin_lock.c
@@ -21,7 +21,7 @@
/* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
to the number of plain reads that it's optimal to spin on between uses
- of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
+ of atomic_compare_exchange_weak_acquire. If spinning forever is optimal
then use -1. If no plain reads here would ever be optimal, use 0. */
#ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
# warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
@@ -29,18 +29,27 @@
#endif
int
-pthread_spin_lock (pthread_spinlock_t *lock)
+pthread_spin_lock (pthread_spinlock_t *lock_volatile)
{
+ /* The type pthread_spinlock_t is a typedef to volatile int on all archs.
+ Passing a volatile pointer to the atomic macros can lead to extra stores
+ and loads to stack if such a macro creates a temporary variable by using
+ __typeof (*(mem)). */
+ int *lock = (int *) lock_volatile;
+
/* atomic_exchange usually takes less instructions than
atomic_compare_and_exchange. On the other hand,
atomic_compare_and_exchange potentially generates less bus traffic
when the lock is locked.
We assume that the first try mostly will be successful, and we use
atomic_exchange. For the subsequent tries we use
- atomic_compare_and_exchange. */
- if (atomic_exchange_acq (lock, 1) == 0)
+ atomic_compare_and_exchange.
+ We need acquire memory order here as we need to see if another thread has
+ locked / unlocked this spinlock. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
return 0;
+ int val;
do
{
/* The lock is contended and we need to wait. Going straight back
@@ -50,20 +59,41 @@ pthread_spin_lock (pthread_spinlock_t *lock)
On the other hand, we do want to update memory state on the local core
once in a while to avoid spinning indefinitely until some event that
will happen to update local memory as a side-effect. */
- if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
+
+#if SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0
+ /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG plain reads between the
+ atomic compare and exchanges. */
+ int wait;
+ for (wait = 0; wait < SPIN_LOCK_READS_BETWEEN_CMPXCHG; wait ++)
{
- int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
+ atomic_spin_nop ();
- while (*lock != 0 && wait > 0)
- --wait;
+ /* Use a plain read every round. */
+ val = *lock_volatile;
+ if (val == 0)
+ break;
}
- else
+
+ /* Set expected value to zero for the next compare and exchange. */
+ val = 0;
+
+#else /* SPIN_LOCK_READS_BETWEEN_CMPXCHG < 0 */
+ /* Use plain reads until spinlock is free and then try a further atomic
+ compare and exchange the next time. */
+ do
{
- while (*lock != 0)
- ;
+ atomic_spin_nop ();
+
+ /* Use a plain read every round. */
+ val = *lock_volatile;
}
+ while (val != 0);
+
+#endif
+ /* We need acquire memory order here for the same reason as mentioned
+ for the first try to lock the spinlock. */
}
- while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
+ while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
return 0;
}
diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
index 4e1a96c..8e9c76f 100644
--- a/nptl/pthread_spin_trylock.c
+++ b/nptl/pthread_spin_trylock.c
@@ -20,8 +20,33 @@
#include <atomic.h>
#include "pthreadP.h"
+/* A machine-specific version can define
+ SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG to 1 if an explicit test if
+ lock is free is optimal. */
+#ifndef SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG
+# define SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG 0
+#endif
+
int
-pthread_spin_trylock (pthread_spinlock_t *lock)
+pthread_spin_trylock (pthread_spinlock_t *lock_volatile)
{
- return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
+ /* See comment in pthread_spin_lock.c. */
+ int *lock = (int *) lock_volatile;
+
+ /* We need acquire memory order here as we need to see if another
+ thread has locked / unlocked this spinlock. */
+#if SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG == 1
+ /* Load and test the spinlock and only try to lock the spinlock if it is
+ free. */
+ int val = atomic_load_relaxed (lock);
+ if (__glibc_likely (val == 0
+ && atomic_compare_exchange_weak_acquire (lock, &val, 1)))
+ return 0;
+#else
+ /* Set spinlock to locked and test if we have locked it. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
+ return 0;
+#endif
+
+ return EBUSY;
}
diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
index d4b63ac..014f295 100644
--- a/nptl/pthread_spin_unlock.c
+++ b/nptl/pthread_spin_unlock.c
@@ -23,7 +23,9 @@
int
pthread_spin_unlock (pthread_spinlock_t *lock)
{
- atomic_full_barrier ();
- *lock = 0;
+ /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
+ or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
+ pthread_spin_trylock. */
+ atomic_store_release (lock, 0);
return 0;
}
--
2.3.0
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2016-12-16 16:32 [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros Stefan Liebler
2016-12-16 16:32 ` [PATCH 2/2] S390: Use generic spinlock code Stefan Liebler
@ 2016-12-19 12:14 ` Szabolcs Nagy
2017-02-08 14:49 ` Stefan Liebler
1 sibling, 1 reply; 63+ messages in thread
From: Szabolcs Nagy @ 2016-12-19 12:14 UTC (permalink / raw)
To: Stefan Liebler, libc-alpha; +Cc: nd
On 16/12/16 16:31, Stefan Liebler wrote:
> Passing a volatile pointer to the atomic macros can lead to extra stores
> and loads to stack if such a macro creates a temporary variable by using
> __typeof (*(mem)). Thus the patch passes a int pointer to the atomic macros.
the resolution of
http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm
says that the type of a cast expression is unqualified, so
__typeof ((__typeof (*(mem)))*(mem)) tmp = *(mem);
would have the right type.. seems to work since gcc-5
https://godbolt.org/g/eS0X5b
(looks beautiful.)
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2016-12-19 12:14 ` [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros Szabolcs Nagy
@ 2017-02-08 14:49 ` Stefan Liebler
2017-02-13 20:29 ` Torvald Riegel
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-02-08 14:49 UTC (permalink / raw)
To: libc-alpha
[-- Attachment #1: Type: text/plain, Size: 1539 bytes --]
On 12/19/2016 01:14 PM, Szabolcs Nagy wrote:
> On 16/12/16 16:31, Stefan Liebler wrote:
>> Passing a volatile pointer to the atomic macros can lead to extra stores
>> and loads to stack if such a macro creates a temporary variable by using
>> __typeof (*(mem)). Thus the patch passes a int pointer to the atomic macros.
>
> the resolution of
> http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm
> says that the type of a cast expression is unqualified, so
>
> __typeof ((__typeof (*(mem)))*(mem)) tmp = *(mem);
>
> would have the right type.. seems to work since gcc-5
>
> https://godbolt.org/g/eS0X5b
>
> (looks beautiful.)
>
Thanks for this.
I've adjusted the needed atomic-macros in include/atomic.h and use the
typeof-construct "__typeof ((__typeof (*(mem)))*(mem)) tmp;".
Now we can pass the volatile int pointers to the atomic-macros.
See the updated patch.
Okay to commit?
Bye.
Stefan
ChangeLog:
* include/atomic.h:
(__atomic_val_bysize): Cast type to omit volatile qualifier.
(atomic_exchange_acq): Likewise.
(atomic_load_relaxed): Likewise.
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros.
* nptl/pthread_spin_trylock.c
(pthread_spin_trylock): Likewise. Use an explicit test if lock
is free, if new SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG macro
is set to one.
(SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG): New define.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
[-- Attachment #2: 20170208_generic_spinlock.patch --]
[-- Type: text/x-patch, Size: 8792 bytes --]
commit cc80b947c9c355e83f464fa7135e3ce9db045be8
Author: Stefan Liebler <stli@linux.vnet.ibm.com>
Date: Wed Feb 8 15:24:14 2017 +0100
Optimize generic spinlock code and use C11 like atomic macros.
This patch optimizes the generic spinlock code.
The type pthread_spinlock_t is a typedef to volatile int on all archs.
Passing a volatile pointer to the atomic macros can lead to extra stores
and loads to stack if such a macro creates a temporary variable by using
"__typeof (*(mem)) tmp;". Thus, those macros which are used by spinlock code -
atomic_exchange_acquire, atomic_load_relaxed,
atomic_compare_exchange_weak_acquire - have to be adjusted.
According to the comment from Szabolcs Nagy, the type of a cast expression is
unqualified (see http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm):
__typeof ((__typeof (*(mem)) *(mem)) tmp;
This patch adjusts those macros in include/atomic.h.
The atomic macros are replaced by the C11 like atomic macros and thus
the code is aligned to it. The issue with passed volatile int pointers
applies to the C11 like atomic macros as well as the ones used before.
I've added a glibc_likely hint to the first atomic exchange in
pthread_spin_lock in order to return immediately to the caller if the lock is
free. Without the hint, there is an additional jump if the lock is free.
I've added the atomic_spin_nop macro within the loop of plain reads.
The plain reads are also realized by C11 like atomic_load_relaxed macro.
For pthread_spin_trylock, a machine-specific version can define
SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG to 1 if an explicit test if
lock is free is optimal.
ChangeLog:
* include/atomic.h:
(__atomic_val_bysize): Cast type to omit volatile qualifier.
(atomic_exchange_acq): Likewise.
(atomic_load_relaxed): Likewise.
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros.
* nptl/pthread_spin_trylock.c
(pthread_spin_trylock): Likewise. Use an explicit test if lock
is free, if new SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG macro
is set to one.
(SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG): New define.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
diff --git a/include/atomic.h b/include/atomic.h
index 7f32640..770db4a 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -54,7 +54,7 @@
and following args. */
#define __atomic_val_bysize(pre, post, mem, ...) \
({ \
- __typeof (*mem) __atg1_result; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
if (sizeof (*mem) == 1) \
__atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
else if (sizeof (*mem) == 2) \
@@ -162,9 +162,9 @@
/* Store NEWVALUE in *MEM and return the old value. */
#ifndef atomic_exchange_acq
# define atomic_exchange_acq(mem, newvalue) \
- ({ __typeof (*(mem)) __atg5_oldval; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
__typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
\
do \
__atg5_oldval = *__atg5_memp; \
@@ -668,7 +668,7 @@ void __atomic_link_error (void);
# ifndef atomic_load_relaxed
# define atomic_load_relaxed(mem) \
- ({ __typeof (*(mem)) __atg100_val; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
__asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
__atg100_val; })
# endif
diff --git a/nptl/pthread_spin_init.c b/nptl/pthread_spin_init.c
index 01dec5e..bca3590 100644
--- a/nptl/pthread_spin_init.c
+++ b/nptl/pthread_spin_init.c
@@ -22,6 +22,8 @@
int
pthread_spin_init (pthread_spinlock_t *lock, int pshared)
{
- *lock = 0;
+ /* The atomic_store_relaxed is enough as we only initialize the spinlock here
+ and we are not in a critical region. */
+ atomic_store_relaxed (lock, 0);
return 0;
}
diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
index 4d03b78..4107b5e 100644
--- a/nptl/pthread_spin_lock.c
+++ b/nptl/pthread_spin_lock.c
@@ -21,7 +21,7 @@
/* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
to the number of plain reads that it's optimal to spin on between uses
- of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
+ of atomic_compare_exchange_weak_acquire. If spinning forever is optimal
then use -1. If no plain reads here would ever be optimal, use 0. */
#ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
# warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
@@ -37,10 +37,13 @@ pthread_spin_lock (pthread_spinlock_t *lock)
when the lock is locked.
We assume that the first try mostly will be successful, and we use
atomic_exchange. For the subsequent tries we use
- atomic_compare_and_exchange. */
- if (atomic_exchange_acq (lock, 1) == 0)
+ atomic_compare_and_exchange.
+ We need acquire memory order here as we need to see if another thread has
+ locked / unlocked this spinlock. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
return 0;
+ int val;
do
{
/* The lock is contended and we need to wait. Going straight back
@@ -50,20 +53,39 @@ pthread_spin_lock (pthread_spinlock_t *lock)
On the other hand, we do want to update memory state on the local core
once in a while to avoid spinning indefinitely until some event that
will happen to update local memory as a side-effect. */
- if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
+
+#if SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0
+ /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG plain reads between the
+ atomic compare and exchanges. */
+ int wait;
+ for (wait = 0; wait < SPIN_LOCK_READS_BETWEEN_CMPXCHG; wait ++)
{
- int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
+ atomic_spin_nop ();
- while (*lock != 0 && wait > 0)
- --wait;
+ val = atomic_load_relaxed (lock);
+ if (val == 0)
+ break;
}
- else
+
+ /* Set expected value to zero for the next compare and exchange. */
+ val = 0;
+
+#else /* SPIN_LOCK_READS_BETWEEN_CMPXCHG < 0 */
+ /* Use plain reads until spinlock is free and then try a further atomic
+ compare and exchange the next time. */
+ do
{
- while (*lock != 0)
- ;
+ atomic_spin_nop ();
+
+ val = atomic_load_relaxed (lock);
}
+ while (val != 0);
+
+#endif
+ /* We need acquire memory order here for the same reason as mentioned
+ for the first try to lock the spinlock. */
}
- while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
+ while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
return 0;
}
diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
index 593bba3..942a38f 100644
--- a/nptl/pthread_spin_trylock.c
+++ b/nptl/pthread_spin_trylock.c
@@ -20,8 +20,29 @@
#include <atomic.h>
#include "pthreadP.h"
+/* A machine-specific version can define
+ SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG to 1 if an explicit test if
+ lock is free is optimal. */
+#ifndef SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG
+# define SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG 0
+#endif
+
int
pthread_spin_trylock (pthread_spinlock_t *lock)
{
- return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
+ /* We need acquire memory order here as we need to see if another
+ thread has locked / unlocked this spinlock. */
+#if SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG == 1
+ /* Load and test the spinlock and only try to lock the spinlock if it is
+ free. */
+ int val = atomic_load_relaxed (lock);
+ if (__glibc_likely (val == 0 && atomic_exchange_acquire (lock, 1) == 0))
+ return 0;
+#else
+ /* Set spinlock to locked and test if we have locked it. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
+ return 0;
+#endif
+
+ return EBUSY;
}
diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
index 5fd73e5..f83b696 100644
--- a/nptl/pthread_spin_unlock.c
+++ b/nptl/pthread_spin_unlock.c
@@ -23,7 +23,9 @@
int
pthread_spin_unlock (pthread_spinlock_t *lock)
{
- atomic_full_barrier ();
- *lock = 0;
+ /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
+ or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
+ pthread_spin_trylock. */
+ atomic_store_release (lock, 0);
return 0;
}
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 2/2] S390: Use generic spinlock code.
2016-12-16 16:32 ` [PATCH 2/2] S390: Use generic spinlock code Stefan Liebler
@ 2017-02-08 14:49 ` Stefan Liebler
2017-02-13 20:39 ` Torvald Riegel
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-02-08 14:49 UTC (permalink / raw)
To: libc-alpha
[-- Attachment #1: Type: text/plain, Size: 781 bytes --]
This is an updated version of the patch, which adjusts the s390 specific
atomic-macros in the same way as in include/atomic.h.
Thus passing a volatile int pointer is fine, too.
Okay to commit?
Bye.
Stefan
ChangeLog:
* sysdeps/s390/atomic-machine.h:
(__arch_compare_and_exchange_val_32_acq):
Cast type to omit volatile qualifier.
(__arch_compare_and_exchange_val_64_acq): Likewise.
(atomic_exchange_acq): Likewise.
* sysdeps/s390/nptl/pthread_spin_init.c: Delete File.
* sysdeps/s390/nptl/pthread_spin_unlock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_lock.c:
(SPIN_LOCK_READS_BETWEEN_CMPXCHG): New define.
Use generic spinlock code.
* sysdeps/s390/nptl/pthread_spin_trylock.c:
(SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG): New define.
Use generic spinlock code.
[-- Attachment #2: 20170208_s390_spinlock.patch --]
[-- Type: text/x-patch, Size: 7921 bytes --]
commit 472bccee286f2f40522b8f670c9b54b7ef58425c
Author: Stefan Liebler <stli@linux.vnet.ibm.com>
Date: Wed Feb 8 15:24:14 2017 +0100
S390: Use generic spinlock code.
This patch removes the s390 specific implementation of spinlock code
and is now using the generic one.
For pthread_spin_trylock an explicit load and test before executing
compare and swap instruction is done as it is an interlock update even
if the lock is already acquired.
The macros in s390 specific atomic-machine.h are aligned in order to
omit the storing to and loading from stack.
ChangeLog:
* sysdeps/s390/atomic-machine.h:
(__arch_compare_and_exchange_val_32_acq):
Cast type to omit volatile qualifier.
(__arch_compare_and_exchange_val_64_acq): Likewise.
(atomic_exchange_acq): Likewise.
* sysdeps/s390/nptl/pthread_spin_init.c: Delete File.
* sysdeps/s390/nptl/pthread_spin_unlock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_lock.c:
(SPIN_LOCK_READS_BETWEEN_CMPXCHG): New define.
Use generic spinlock code.
* sysdeps/s390/nptl/pthread_spin_trylock.c:
(SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG): New define.
Use generic spinlock code.
diff --git a/sysdeps/s390/atomic-machine.h b/sysdeps/s390/atomic-machine.h
index 211d3d6..d98c836 100644
--- a/sysdeps/s390/atomic-machine.h
+++ b/sysdeps/s390/atomic-machine.h
@@ -54,7 +54,7 @@ typedef uintmax_t uatomic_max_t;
#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ __typeof (mem) __archmem = (mem); \
- __typeof (*mem) __archold = (oldval); \
+ __typeof ((__typeof (*(mem))) *(mem)) __archold = (oldval); \
__asm__ __volatile__ ("cs %0,%2,%1" \
: "+d" (__archold), "=Q" (*__archmem) \
: "d" (newval), "m" (*__archmem) : "cc", "memory" ); \
@@ -64,7 +64,7 @@ typedef uintmax_t uatomic_max_t;
# define __HAVE_64B_ATOMICS 1
# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
({ __typeof (mem) __archmem = (mem); \
- __typeof (*mem) __archold = (oldval); \
+ __typeof ((__typeof (*(mem))) *(mem)) __archold = (oldval); \
__asm__ __volatile__ ("csg %0,%2,%1" \
: "+d" (__archold), "=Q" (*__archmem) \
: "d" ((long) (newval)), "m" (*__archmem) : "cc", "memory" ); \
@@ -86,8 +86,8 @@ typedef uintmax_t uatomic_max_t;
#ifdef __s390x__
# define atomic_exchange_acq(mem, newvalue) \
({ __typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_oldval = *__atg5_memp; \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval = *__atg5_memp; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
if (sizeof (*mem) == 4) \
__asm__ __volatile__ ("0: cs %0,%2,%1\n" \
" jl 0b" \
@@ -106,8 +106,8 @@ typedef uintmax_t uatomic_max_t;
#else
# define atomic_exchange_acq(mem, newvalue) \
({ __typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_oldval = *__atg5_memp; \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval = *__atg5_memp; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
if (sizeof (*mem) == 4) \
__asm__ __volatile__ ("0: cs %0,%2,%1\n" \
" jl 0b" \
diff --git a/sysdeps/s390/nptl/pthread_spin_init.c b/sysdeps/s390/nptl/pthread_spin_init.c
deleted file mode 100644
index d826871..0000000
--- a/sysdeps/s390/nptl/pthread_spin_init.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Not needed. pthread_spin_init is an alias for pthread_spin_unlock. */
diff --git a/sysdeps/s390/nptl/pthread_spin_lock.c b/sysdeps/s390/nptl/pthread_spin_lock.c
index 7349940..39d2926 100644
--- a/sysdeps/s390/nptl/pthread_spin_lock.c
+++ b/sysdeps/s390/nptl/pthread_spin_lock.c
@@ -16,17 +16,9 @@
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
-#include "pthreadP.h"
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-int
-pthread_spin_lock (pthread_spinlock_t *lock)
-{
- int oldval;
-
- __asm__ __volatile__ ("0: lhi %0,0\n"
- " cs %0,%2,%1\n"
- " jl 0b"
- : "=&d" (oldval), "=Q" (*lock)
- : "d" (1), "m" (*lock) : "cc" );
- return 0;
-}
+/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
+ it will resolve to this very file. Using "sysdeps/.." as reference to the
+ top level directory does the job. */
+#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/s390/nptl/pthread_spin_trylock.c b/sysdeps/s390/nptl/pthread_spin_trylock.c
index 0e848da..f3937b5 100644
--- a/sysdeps/s390/nptl/pthread_spin_trylock.c
+++ b/sysdeps/s390/nptl/pthread_spin_trylock.c
@@ -16,17 +16,9 @@
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
-#include <errno.h>
-#include "pthreadP.h"
+#define SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG 1
-int
-pthread_spin_trylock (pthread_spinlock_t *lock)
-{
- int old;
-
- __asm__ __volatile__ ("cs %0,%3,%1"
- : "=d" (old), "=Q" (*lock)
- : "0" (0), "d" (1), "m" (*lock) : "cc" );
-
- return old != 0 ? EBUSY : 0;
-}
+/* We can't use the normal "#include <nptl/pthread_spin_trylock.c>" because
+ it will resolve to this very file. Using "sysdeps/.." as reference to the
+ top level directory does the job. */
+#include <sysdeps/../nptl/pthread_spin_trylock.c>
diff --git a/sysdeps/s390/nptl/pthread_spin_unlock.c b/sysdeps/s390/nptl/pthread_spin_unlock.c
deleted file mode 100644
index 54e7378..0000000
--- a/sysdeps/s390/nptl/pthread_spin_unlock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Ugly hack to avoid the declaration of pthread_spin_init. */
-#define pthread_spin_init pthread_spin_init_XXX
-#include "pthreadP.h"
-#undef pthread_spin_init
-
-int
-pthread_spin_unlock (pthread_spinlock_t *lock)
-{
- __asm__ __volatile__ (" xc %O0(4,%R0),%0\n"
- " bcr 15,0"
- : "=Q" (*lock) : "m" (*lock) : "cc" );
- return 0;
-}
-strong_alias (pthread_spin_unlock, pthread_spin_init)
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-08 14:49 ` Stefan Liebler
@ 2017-02-13 20:29 ` Torvald Riegel
2017-02-15 9:36 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-02-13 20:29 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
Thanks for working on this. Detailed comments below.
Generally, I think we need to keep working on optimizing this (this can
happen in follow-up patches). For example, we should have
microbenchmarks for the exchange vs. CAS choice.
Also, some of the tuning knobs such as
SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG apply to atomics in general and
not just the spinlock. I'd prefer if these where in a state in which we
could add them as property that's part of the atomics interface.
On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
> diff --git a/include/atomic.h b/include/atomic.h
> index 7f32640..770db4a 100644
> --- a/include/atomic.h
>
> +++ b/include/atomic.h
>
> @@ -54,7 +54,7 @@
> and following args. */
> #define __atomic_val_bysize(pre, post, mem, ...) \
> ({ \
> - __typeof (*mem) __atg1_result; \
>
> + __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
>
> if (sizeof (*mem) == 1) \
> __atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
> else if (sizeof (*mem) == 2) \
> @@ -162,9 +162,9 @@
> /* Store NEWVALUE in *MEM and return the old value. */
> #ifndef atomic_exchange_acq
> # define atomic_exchange_acq(mem, newvalue) \
> - ({ __typeof (*(mem)) __atg5_oldval; \
>
> + ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
>
> __typeof (mem) __atg5_memp = (mem); \
> - __typeof (*(mem)) __atg5_value = (newvalue); \
>
> + __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
>
> \
> do \
> __atg5_oldval = *__atg5_memp; \
> @@ -668,7 +668,7 @@ void __atomic_link_error (void);
>
> # ifndef atomic_load_relaxed
> # define atomic_load_relaxed(mem) \
> - ({ __typeof (*(mem)) __atg100_val; \
>
> + ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
>
> __asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
> __atg100_val; })
> # endif
You could keep these changes, but it's a bit odd because you only apply
them for the functions you needed them for. I think it would be better
to just remove the volatile qualification in the caller (ie, cast lock
to nonvolatile in pthread_spin_lock etc.
> diff --git a/nptl/pthread_spin_init.c b/nptl/pthread_spin_init.c
> index 01dec5e..bca3590 100644
> --- a/nptl/pthread_spin_init.c
>
> +++ b/nptl/pthread_spin_init.c
>
> @@ -22,6 +22,8 @@
> int
> pthread_spin_init (pthread_spinlock_t *lock, int pshared)
> {
> - *lock = 0;
>
> + /* The atomic_store_relaxed is enough as we only initialize the spinlock here
>
> + and we are not in a critical region. */
I would change the comment to:
/* Relaxed MO is fine because this is an initializing store. */
>
> + atomic_store_relaxed (lock, 0);
>
> return 0;
> }
> diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
> index 4d03b78..4107b5e 100644
> --- a/nptl/pthread_spin_lock.c
>
> +++ b/nptl/pthread_spin_lock.c
>
> @@ -21,7 +21,7 @@
>
> /* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
> to the number of plain reads that it's optimal to spin on between uses
> - of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
>
> + of atomic_compare_exchange_weak_acquire. If spinning forever is optimal
, at the end of this line.
> then use -1. If no plain reads here would ever be optimal, use 0. */
> #ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
> # warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
> @@ -37,10 +37,13 @@ pthread_spin_lock (pthread_spinlock_t *lock)
> when the lock is locked.
> We assume that the first try mostly will be successful, and we use
> atomic_exchange. For the subsequent tries we use
> - atomic_compare_and_exchange. */
>
> - if (atomic_exchange_acq (lock, 1) == 0)
>
> + atomic_compare_and_exchange.
>
> + We need acquire memory order here as we need to see if another thread has
>
> + locked / unlocked this spinlock. */
Please change to:
We use acquire MO to synchronize-with the release MO store in
pthread_spin_unlock, and thus ensure that prior critical sections
happen-before this critical section.
>
> + if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
>
> return 0;
>
> + int val;
>
> do
> {
> /* The lock is contended and we need to wait. Going straight back
> @@ -50,20 +53,39 @@ pthread_spin_lock (pthread_spinlock_t *lock)
> On the other hand, we do want to update memory state on the local core
> once in a while to avoid spinning indefinitely until some event that
> will happen to update local memory as a side-effect. */
> - if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
>
> +
>
> +#if SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0
>
> + /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG plain reads between the
>
> + atomic compare and exchanges. */
>
> + int wait;
>
> + for (wait = 0; wait < SPIN_LOCK_READS_BETWEEN_CMPXCHG; wait ++)
>
> {
> - int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
>
> + atomic_spin_nop ();
>
>
> - while (*lock != 0 && wait > 0)
>
> - --wait;
>
> + val = atomic_load_relaxed (lock);
>
> + if (val == 0)
>
> + break;
>
> }
> - else
>
> +
>
> + /* Set expected value to zero for the next compare and exchange. */
>
> + val = 0;
>
> +
>
> +#else /* SPIN_LOCK_READS_BETWEEN_CMPXCHG < 0 */
>
> + /* Use plain reads until spinlock is free and then try a further atomic
> + compare and exchange the next time. */
Please change to:
Use relaxed-MO reads until we observe the lock to not be acquired
anymore.
> + do
>
> {
> - while (*lock != 0)
>
> - ;
>
> + atomic_spin_nop ();
>
> +
>
> + val = atomic_load_relaxed (lock);
>
> }
> + while (val != 0);
>
> +
>
> +#endif
>
> + /* We need acquire memory order here for the same reason as mentioned
>
> + for the first try to lock the spinlock. */
>
> }
> - while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
>
> + while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
>
>
> return 0;
> }
> diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
> index 593bba3..942a38f 100644
> --- a/nptl/pthread_spin_trylock.c
>
> +++ b/nptl/pthread_spin_trylock.c
>
> @@ -20,8 +20,29 @@
> #include <atomic.h>
> #include "pthreadP.h"
>
> +/* A machine-specific version can define
>
> + SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG to 1 if an explicit test if
>
> + lock is free is optimal. */
>
> +#ifndef SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG
>
> +# define SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG 0
>
> +#endif
A while ago we tried hard to remove all code that would fail silently
when a macro had a typo in the name, for example. We still have a few
of them left (e.g., in the atomics), but I think this here doesn't
warrant an exception.
Also, the name does not match the description. What are you really
trying to parametrize here? Do you want to do test-and-test-and-set vs.
test-and-set? Or do you want to make some statement about how CAS vs.
exchange behave in terms of runtime costs / effect on caches? Or do you
want to have a flag that says that exchange is implemented through a CAS
loop anyway, and thus it's not worth trying an exchange if we actually
want to bail out when the value is not equal to the expected value?
>
> +
>
> int
> pthread_spin_trylock (pthread_spinlock_t *lock)
> {
> - return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
>
> + /* We need acquire memory order here as we need to see if another
>
> + thread has locked / unlocked this spinlock. */
See above. Please fix the comment in a similar way.
>
> +#if SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG == 1
>
> + /* Load and test the spinlock and only try to lock the spinlock if it is
>
> + free. */
>
> + int val = atomic_load_relaxed (lock);
>
> + if (__glibc_likely (val == 0 && atomic_exchange_acquire (lock, 1) == 0))
I think that's not quite the same as a choice between CAS and exchange.
Doing a load first could be helpful for *both* CAS and exchange. OTOH,
if we assume that trylock will succeed most of the time, then the load
is unnecessary and might be more costly (eg, if it causes the state of
the cache line to change twice).
>
> + return 0;
>
> +#else
>
> + /* Set spinlock to locked and test if we have locked it. */
Just say that we try to acquire the lock, which succeeds if the lock had
not been acquired.
> + if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
>
> + return 0;
>
> +#endif
>
> +
>
> + return EBUSY;
>
> }
> diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
> index 5fd73e5..f83b696 100644
> --- a/nptl/pthread_spin_unlock.c
>
> +++ b/nptl/pthread_spin_unlock.c
>
> @@ -23,7 +23,9 @@
> int
> pthread_spin_unlock (pthread_spinlock_t *lock)
> {
> - atomic_full_barrier ();
>
> - *lock = 0;
>
> + /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
>
> + or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
>
> + pthread_spin_trylock. */
>
> + atomic_store_release (lock, 0);
>
> return 0;
> }
I agree with this change. However, depending on how one interprets
POSIX' memory model, one may expect lock releases to be sequentially
consistent. Nonetheless, IMO, glibc should use only release MO.
But we need to announce this change. Some of us have been considering
an additional section in the manual were we specify where we deviate
from POSIX; this change might be the first we're listing there (though
to be fair, this is a deviation only on some architectures because on
others such as powerpc I think, we've been using release MO forever).
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 2/2] S390: Use generic spinlock code.
2017-02-08 14:49 ` Stefan Liebler
@ 2017-02-13 20:39 ` Torvald Riegel
2017-02-15 16:26 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-02-13 20:39 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
> This is an updated version of the patch, which adjusts the s390 specific
> atomic-macros in the same way as in include/atomic.h.
> Thus passing a volatile int pointer is fine, too.
The general direction of this is okay.
Some of my comments for patch 1/2 apply here as well (eg, volatile vs.
atomics).
What I don't like is the choice of 1000 for
SPIN_LOCK_READS_BETWEEN_CMPXCHG. Have you run benchmarks to come up
with this value, or is it a guess? Why isn't it documented how you end
up with this number?
We can keep these with a choice such as this, but then we need to have a
FIXME comment in the code, explaining that this is just an arbitrary
choice.
I would guess that just spinning forever is sufficient, and that we
don't need to throw in a CAS every now and then; using randomized
exponential back-off might be more important. This is something that we
would be in a better position to answer if you'd provide a
microbenchmark for this choice too.
At the end of 2016, I've posted a draft of a microbenchmark for rwlocks.
Maybe you can use this as a start and run a few experiments?
Also, I'm not quite sure whether this number is really
spinlock-specific, and I would like to find a better place for these.
IMO, they should be in some header that contains default tuning
parameters for synchronization code, which is provided by each
architecture that uses the generic spinlock; we'd have no #ifdef for the
tuning parameters, so we'd catch typos in those headers.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-13 20:29 ` Torvald Riegel
@ 2017-02-15 9:36 ` Stefan Liebler
2017-02-18 16:57 ` Torvald Riegel
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-02-15 9:36 UTC (permalink / raw)
To: libc-alpha
[-- Attachment #1: Type: text/plain, Size: 15168 bytes --]
On 02/13/2017 09:29 PM, Torvald Riegel wrote:
> Thanks for working on this. Detailed comments below.
>
> Generally, I think we need to keep working on optimizing this (this can
> happen in follow-up patches). For example, we should have
> microbenchmarks for the exchange vs. CAS choice.
>
> Also, some of the tuning knobs such as
> SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG apply to atomics in general and
> not just the spinlock. I'd prefer if these where in a state in which we
> could add them as property that's part of the atomics interface.
>
> On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
>> diff --git a/include/atomic.h b/include/atomic.h
>> index 7f32640..770db4a 100644
>> --- a/include/atomic.h
>>
>> +++ b/include/atomic.h
>>
>> @@ -54,7 +54,7 @@
>> and following args. */
>> #define __atomic_val_bysize(pre, post, mem, ...) \
>> ({ \
>> - __typeof (*mem) __atg1_result; \
>>
>> + __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
>>
>> if (sizeof (*mem) == 1) \
>> __atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
>> else if (sizeof (*mem) == 2) \
>> @@ -162,9 +162,9 @@
>> /* Store NEWVALUE in *MEM and return the old value. */
>> #ifndef atomic_exchange_acq
>> # define atomic_exchange_acq(mem, newvalue) \
>> - ({ __typeof (*(mem)) __atg5_oldval; \
>>
>> + ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
>>
>> __typeof (mem) __atg5_memp = (mem); \
>> - __typeof (*(mem)) __atg5_value = (newvalue); \
>>
>> + __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
>>
>> \
>> do \
>> __atg5_oldval = *__atg5_memp; \
>> @@ -668,7 +668,7 @@ void __atomic_link_error (void);
>>
>> # ifndef atomic_load_relaxed
>> # define atomic_load_relaxed(mem) \
>> - ({ __typeof (*(mem)) __atg100_val; \
>>
>> + ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
>>
>> __asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
>> __atg100_val; })
>> # endif
>
> You could keep these changes, but it's a bit odd because you only apply
> them for the functions you needed them for. I think it would be better
> to just remove the volatile qualification in the caller (ie, cast lock
> to nonvolatile in pthread_spin_lock etc.
>
Yes, I've only applied them for the functions needed in spinlock-code.
Removing volatile from type pthread_spinlock_t is no option and
casting the volatile pointer to a non-volatile pointer is undefined.
See comment from Florian:
On 12/16/2016 09:12 PM, Florian Weimer wrote:
> That's undefined:
>
> “If an attempt is made to refer to an object defined with a
> volatile-qualified type through use of an lvalue with
> non-volatile-qualified type, the behavior is undefined.â€
>
> But we cannot drop the volatile qualifier from the definition of
> pthread_spinlock_t because it would change the C++ mangling of
> pthread_spinlock_t * and similar types.
>> diff --git a/nptl/pthread_spin_init.c b/nptl/pthread_spin_init.c
>> index 01dec5e..bca3590 100644
>> --- a/nptl/pthread_spin_init.c
>>
>> +++ b/nptl/pthread_spin_init.c
>>
>> @@ -22,6 +22,8 @@
>> int
>> pthread_spin_init (pthread_spinlock_t *lock, int pshared)
>> {
>> - *lock = 0;
>>
>> + /* The atomic_store_relaxed is enough as we only initialize the spinlock here
>>
>> + and we are not in a critical region. */
>
> I would change the comment to:
> /* Relaxed MO is fine because this is an initializing store. */
Okay.
>
>>
>> + atomic_store_relaxed (lock, 0);
>>
>> return 0;
>> }
>> diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
>> index 4d03b78..4107b5e 100644
>> --- a/nptl/pthread_spin_lock.c
>>
>> +++ b/nptl/pthread_spin_lock.c
>>
>> @@ -21,7 +21,7 @@
>>
>> /* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
>> to the number of plain reads that it's optimal to spin on between uses
>> - of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
>>
>> + of atomic_compare_exchange_weak_acquire. If spinning forever is optimal
>
> , at the end of this line.
>
Okay
>> then use -1. If no plain reads here would ever be optimal, use 0. */
>> #ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
>> # warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
>> @@ -37,10 +37,13 @@ pthread_spin_lock (pthread_spinlock_t *lock)
>> when the lock is locked.
>> We assume that the first try mostly will be successful, and we use
>> atomic_exchange. For the subsequent tries we use
>> - atomic_compare_and_exchange. */
>>
>> - if (atomic_exchange_acq (lock, 1) == 0)
>>
>> + atomic_compare_and_exchange.
>>
>> + We need acquire memory order here as we need to see if another thread has
>>
>> + locked / unlocked this spinlock. */
>
> Please change to:
> We use acquire MO to synchronize-with the release MO store in
> pthread_spin_unlock, and thus ensure that prior critical sections
> happen-before this critical section.
>
Okay.
>>
>> + if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
>>
>> return 0;
>>
>> + int val;
>>
>> do
>> {
>> /* The lock is contended and we need to wait. Going straight back
>> @@ -50,20 +53,39 @@ pthread_spin_lock (pthread_spinlock_t *lock)
>> On the other hand, we do want to update memory state on the local core
>> once in a while to avoid spinning indefinitely until some event that
>> will happen to update local memory as a side-effect. */
>> - if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
>>
>> +
>>
>> +#if SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0
>>
>> + /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG plain reads between the
>>
>> + atomic compare and exchanges. */
>>
Also changed this comment to:
/* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG relaxed MO reads between
the atomic compare and exchanges. */
>> + int wait;
>>
>> + for (wait = 0; wait < SPIN_LOCK_READS_BETWEEN_CMPXCHG; wait ++)
>>
>> {
>> - int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
>>
>> + atomic_spin_nop ();
>>
>>
>> - while (*lock != 0 && wait > 0)
>>
>> - --wait;
>>
>> + val = atomic_load_relaxed (lock);
>>
>> + if (val == 0)
>>
>> + break;
>>
>> }
>> - else
>>
>> +
>>
>> + /* Set expected value to zero for the next compare and exchange. */
>>
>> + val = 0;
>>
>> +
>>
>> +#else /* SPIN_LOCK_READS_BETWEEN_CMPXCHG < 0 */
>>
>> + /* Use plain reads until spinlock is free and then try a further atomic
>
>> + compare and exchange the next time. */
>
>
> Please change to:
> Use relaxed-MO reads until we observe the lock to not be acquired
> anymore.
>
Okay.
>
>> + do
>>
>> {
>> - while (*lock != 0)
>>
>> - ;
>>
>> + atomic_spin_nop ();
>>
>> +
>>
>> + val = atomic_load_relaxed (lock);
>>
>> }
>> + while (val != 0);
>>
>> +
>>
>> +#endif
>>
>> + /* We need acquire memory order here for the same reason as mentioned
>>
>> + for the first try to lock the spinlock. */
>>
>> }
>> - while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
>>
>> + while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
>>
>>
>> return 0;
>> }
>> diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
>> index 593bba3..942a38f 100644
>> --- a/nptl/pthread_spin_trylock.c
>>
>> +++ b/nptl/pthread_spin_trylock.c
>>
>> @@ -20,8 +20,29 @@
>> #include <atomic.h>
>> #include "pthreadP.h"
>>
>> +/* A machine-specific version can define
>>
>> + SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG to 1 if an explicit test if
>>
>> + lock is free is optimal. */
>>
>> +#ifndef SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG
>>
>> +# define SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG 0
>>
>> +#endif
>
> A while ago we tried hard to remove all code that would fail silently
> when a macro had a typo in the name, for example. We still have a few
> of them left (e.g., in the atomics), but I think this here doesn't
> warrant an exception.
>
Okay. You're right.
In comment of patch 2/2, you've mentioned a header where an architecture
shall define those parameters.
Thus I've added the file nptl/pthread_spin_parameters.h.
It includes the description of the macros and it emits a warning
if one architecture tries to use generic spinlock implementation without
the definition of those macros.
Furthermore I've added pthread_spin_parameters.h files for the
architectures using the generic spinlock implementation
with definition of those macros.
The pthread_spin_lock.c files for those architectures are no longer
required.
I've added a compiler error in nptl/pthread_spin_trylock.c
if the macro is not defined to zero or one.
If some arch has an empty pthread_spin_parameters.h file or a file
without the definition of those macros and the include_next directive,
the pthread_spin_lock.c / pthread_spin_trylock.c will emit a Wundef warning.
> Also, the name does not match the description. What are you really
> trying to parametrize here? Do you want to do test-and-test-and-set vs.
> test-and-set? Or do you want to make some statement about how CAS vs.
> exchange behave in terms of runtime costs / effect on caches? Or do you
> want to have a flag that says that exchange is implemented through a CAS
> loop anyway, and thus it's not worth trying an exchange if we actually
> want to bail out when the value is not equal to the expected value?
>
See below.
>>
>> +
>>
>> int
>> pthread_spin_trylock (pthread_spinlock_t *lock)
>> {
>> - return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
>>
>> + /* We need acquire memory order here as we need to see if another
>>
>> + thread has locked / unlocked this spinlock. */
>
> See above. Please fix the comment in a similar way.
>
Changed comment to:
/* We use acquire MO to synchronize-with the release MO store in
pthread_spin_unlock, and thus ensure that prior critical sections
happen-before this critical section. */
>>
>> +#if SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG == 1
>>
>> + /* Load and test the spinlock and only try to lock the spinlock if it is
>>
>> + free. */
>>
>> + int val = atomic_load_relaxed (lock);
>>
>> + if (__glibc_likely (val == 0 && atomic_exchange_acquire (lock, 1) == 0))
>
> I think that's not quite the same as a choice between CAS and exchange.
Yes. You are right.
> Doing a load first could be helpful for *both* CAS and exchange. OTOH,
> if we assume that trylock will succeed most of the time, then the load
> is unnecessary and might be more costly (eg, if it causes the state of
> the cache line to change twice).
>
E.g. on s390, there exists no instruction which atomically exchanges the
value. Instead a CAS loop is used. The CAS instruction locks the
cache-line exclusively whether the value in memory equals the expected
old-value or not. Therefore the value is loaded and compared before
using the CAS instruction.
If no other CPU has accessed the lock-value, the load will cause
the state of the cache line to exclusive.
If the lock is not acquired, the subsequent CAS instruction does not
need to change the state of the cache line.
If another CPU has accessed the lock-value e.g. by acquiring the lock,
the load will cause the state of the cache line either to read-only
or exclusive. This depends on the other CPU - whether it has already
stored a new value or not.
As this behaviour depends on the architecture, the architecture has to
decide whether it should load and test the lock-value before the
atomic-macro.
I've changed the name of the macro-define to
SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG.
>>
>> + return 0;
>>
>> +#else
>>
>> + /* Set spinlock to locked and test if we have locked it. */
>
> Just say that we try to acquire the lock, which succeeds if the lock had
> not been acquired.
Okay.
>
>> + if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
>>
>> + return 0;
>>
>> +#endif
>>
>> +
>>
>> + return EBUSY;
>>
>> }
>> diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
>> index 5fd73e5..f83b696 100644
>> --- a/nptl/pthread_spin_unlock.c
>>
>> +++ b/nptl/pthread_spin_unlock.c
>>
>> @@ -23,7 +23,9 @@
>> int
>> pthread_spin_unlock (pthread_spinlock_t *lock)
>> {
>> - atomic_full_barrier ();
>>
>> - *lock = 0;
>>
>> + /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
>>
>> + or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
>>
>> + pthread_spin_trylock. */
>>
>> + atomic_store_release (lock, 0);
>>
>> return 0;
>> }
>
> I agree with this change. However, depending on how one interprets
> POSIX' memory model, one may expect lock releases to be sequentially
> consistent. Nonetheless, IMO, glibc should use only release MO.
>
> But we need to announce this change. Some of us have been considering
> an additional section in the manual were we specify where we deviate
> from POSIX; this change might be the first we're listing there (though
> to be fair, this is a deviation only on some architectures because on
> others such as powerpc I think, we've been using release MO forever).
>
>
As not all architectures use the generic spinlock implementation, what
about a NEWS entry like:
* The new generic spinlock implementation uses C11 like atomics.
The pthread_spin_unlock implementation is now using release
memory order instead of sequentially consistent memory order.
Here is an updated version of patch 1/2.
(Patch 2/2 has to be aligned due to these changes, too)
Thanks.
Stefan
ChangeLog:
* NEWS: Mention new spinlock implementation.
* include/atomic.h:
(__atomic_val_bysize): Cast type to omit volatile qualifier.
(atomic_exchange_acq): Likewise.
(atomic_load_relaxed): Likewise.
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros.
* nptl/pthread_spin_trylock.c
(pthread_spin_trylock): Likewise. Use an explicit load and
test if lock is free before exchange, if new macro
SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG macro is set to one.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
* nptl/pthread_spin_parameters.h: New File.
* sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/aarch64/nptl/pthread_spin_parameters.h: New File.
* sysdeps/arm/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/arm/nptl/pthread_spin_parameters.h: New File.
* sysdeps/hppa/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/hppa/nptl/pthread_spin_parameters.h: New File.
* sysdeps/m68k/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/m68k/nptl/pthread_spin_parameters.h: New File.
* sysdeps/microblaze/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/microblaze/nptl/pthread_spin_parameters.h: New File.
* sysdeps/mips/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/mips/nptl/pthread_spin_parameters.h: New File.
* sysdeps/nios2/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/nios2/nptl/pthread_spin_parameters.h: New File.
[-- Attachment #2: 20170215_generic_spinlock.patch --]
[-- Type: text/x-patch, Size: 30865 bytes --]
commit 2110f18d944bcb018f57d35b1efe19b9b5f78b1a
Author: Stefan Liebler <stli@linux.vnet.ibm.com>
Date: Wed Feb 15 10:19:27 2017 +0100
Optimize generic spinlock code and use C11 like atomic macros.
This patch optimizes the generic spinlock code.
The type pthread_spinlock_t is a typedef to volatile int on all archs.
Passing a volatile pointer to the atomic macros can lead to extra stores
and loads to stack if such a macro creates a temporary variable by using
"__typeof (*(mem)) tmp;". Thus, those macros which are used by spinlock code -
atomic_exchange_acquire, atomic_load_relaxed,
atomic_compare_exchange_weak_acquire - have to be adjusted.
According to the comment from Szabolcs Nagy, the type of a cast expression is
unqualified (see http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm):
__typeof ((__typeof (*(mem)) *(mem)) tmp;
This patch adjusts those macros in include/atomic.h.
The atomic macros are replaced by the C11 like atomic macros and thus
the code is aligned to it. The pthread_spin_unlock implementation is now
using release memory order instead of sequentially consistent memory order.
The issue with passed volatile int pointers applies to the C11 like atomic
macros as well as the ones used before.
I've added a glibc_likely hint to the first atomic exchange in
pthread_spin_lock in order to return immediately to the caller if the lock is
free. Without the hint, there is an additional jump if the lock is free.
I've added the atomic_spin_nop macro within the loop of plain reads.
The plain reads are also realized by C11 like atomic_load_relaxed macro.
For pthread_spin_trylock, a machine-specific version can define
SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG to 1 if an explicit test if
lock is free is optimal.
An architecture which wants to use the generic spinlock implementation
has to create the file pthread_spin_parameters.h with the definition of
the following parameter macros instead of creating a wrapper file which
includes nptl/pthread_spin_lock.c:
SPIN_LOCK_READS_BETWEEN_CMPXCHG
SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG
ChangeLog:
* NEWS: Mention new spinlock implementation.
* include/atomic.h:
(__atomic_val_bysize): Cast type to omit volatile qualifier.
(atomic_exchange_acq): Likewise.
(atomic_load_relaxed): Likewise.
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros.
* nptl/pthread_spin_trylock.c
(pthread_spin_trylock): Likewise. Use an explicit load and
test if lock is free before exchange, if new macro
SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG macro is set to one.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
* nptl/pthread_spin_parameters.h: New File.
* sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/aarch64/nptl/pthread_spin_parameters.h: New File.
* sysdeps/arm/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/arm/nptl/pthread_spin_parameters.h: New File.
* sysdeps/hppa/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/hppa/nptl/pthread_spin_parameters.h: New File.
* sysdeps/m68k/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/m68k/nptl/pthread_spin_parameters.h: New File.
* sysdeps/microblaze/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/microblaze/nptl/pthread_spin_parameters.h: New File.
* sysdeps/mips/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/mips/nptl/pthread_spin_parameters.h: New File.
* sysdeps/nios2/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/nios2/nptl/pthread_spin_parameters.h: New File.
diff --git a/NEWS b/NEWS
index b5a401c..b85b734 100644
--- a/NEWS
+++ b/NEWS
@@ -7,7 +7,9 @@ using `glibc' in the "product" field.
\f
Version 2.26
-[Add important changes here]
+* The new generic spinlock implementation uses C11 like atomics.
+ The pthread_spin_unlock implementation is now using release
+ memory order instead of sequentially consistent memory order.
Security related changes:
diff --git a/include/atomic.h b/include/atomic.h
index 7f32640..770db4a 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -54,7 +54,7 @@
and following args. */
#define __atomic_val_bysize(pre, post, mem, ...) \
({ \
- __typeof (*mem) __atg1_result; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
if (sizeof (*mem) == 1) \
__atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
else if (sizeof (*mem) == 2) \
@@ -162,9 +162,9 @@
/* Store NEWVALUE in *MEM and return the old value. */
#ifndef atomic_exchange_acq
# define atomic_exchange_acq(mem, newvalue) \
- ({ __typeof (*(mem)) __atg5_oldval; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
__typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
\
do \
__atg5_oldval = *__atg5_memp; \
@@ -668,7 +668,7 @@ void __atomic_link_error (void);
# ifndef atomic_load_relaxed
# define atomic_load_relaxed(mem) \
- ({ __typeof (*(mem)) __atg100_val; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
__asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
__atg100_val; })
# endif
diff --git a/nptl/pthread_spin_init.c b/nptl/pthread_spin_init.c
index 01dec5e..fe30913 100644
--- a/nptl/pthread_spin_init.c
+++ b/nptl/pthread_spin_init.c
@@ -22,6 +22,7 @@
int
pthread_spin_init (pthread_spinlock_t *lock, int pshared)
{
- *lock = 0;
+ /* Relaxed MO is fine because this is an initializing store. */
+ atomic_store_relaxed (lock, 0);
return 0;
}
diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
index 4d03b78..65d34a3 100644
--- a/nptl/pthread_spin_lock.c
+++ b/nptl/pthread_spin_lock.c
@@ -18,15 +18,7 @@
#include <atomic.h>
#include "pthreadP.h"
-
-/* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
- to the number of plain reads that it's optimal to spin on between uses
- of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
- then use -1. If no plain reads here would ever be optimal, use 0. */
-#ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
-# warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
-# define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-#endif
+#include <pthread_spin_parameters.h>
int
pthread_spin_lock (pthread_spinlock_t *lock)
@@ -37,10 +29,14 @@ pthread_spin_lock (pthread_spinlock_t *lock)
when the lock is locked.
We assume that the first try mostly will be successful, and we use
atomic_exchange. For the subsequent tries we use
- atomic_compare_and_exchange. */
- if (atomic_exchange_acq (lock, 1) == 0)
+ atomic_compare_and_exchange.
+ We use acquire MO to synchronize-with the release MO store in
+ pthread_spin_unlock, and thus ensure that prior critical sections
+ happen-before this critical section. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
return 0;
+ int val;
do
{
/* The lock is contended and we need to wait. Going straight back
@@ -50,20 +46,39 @@ pthread_spin_lock (pthread_spinlock_t *lock)
On the other hand, we do want to update memory state on the local core
once in a while to avoid spinning indefinitely until some event that
will happen to update local memory as a side-effect. */
- if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
+
+#if SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0
+ /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG relaxed MO reads between
+ the atomic compare and exchanges. */
+ int wait;
+ for (wait = 0; wait < SPIN_LOCK_READS_BETWEEN_CMPXCHG; wait ++)
{
- int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
+ atomic_spin_nop ();
- while (*lock != 0 && wait > 0)
- --wait;
+ val = atomic_load_relaxed (lock);
+ if (val == 0)
+ break;
}
- else
+
+ /* Set expected value to zero for the next compare and exchange. */
+ val = 0;
+
+#else /* SPIN_LOCK_READS_BETWEEN_CMPXCHG < 0 */
+ /* Use relaxed MO reads until we observe the lock to not be acquired
+ anymore. */
+ do
{
- while (*lock != 0)
- ;
+ atomic_spin_nop ();
+
+ val = atomic_load_relaxed (lock);
}
+ while (val != 0);
+
+#endif
+ /* We need acquire memory order here for the same reason as mentioned
+ for the first try to lock the spinlock. */
}
- while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
+ while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
return 0;
}
diff --git a/nptl/pthread_spin_parameters.h b/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..6cde482
--- /dev/null
+++ b/nptl/pthread_spin_parameters.h
@@ -0,0 +1,35 @@
+/* Parameters for generic pthread_spinlock_t implementation. Generic version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+/* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
+ to the number of plain reads that it's optimal to spin on between uses
+ of atomic_compare_exchange_weak_acquire. If spinning forever is optimal,
+ then use -1. If no plain reads here would ever be optimal, use 0. */
+#ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
+# warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
+# define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+#endif
+
+/* A machine-specific version can define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG
+ to 1 if an explicit load and test if lock is not acquired before executing
+ atomic_exchange_acquire is optimal. Define to 0 to execute
+ atomic_exchange_acquire without an additional load and test. */
+#ifndef SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG
+# warning machine-dependent file should define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG
+# define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 0
+#endif
diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
index 593bba3..1e22843 100644
--- a/nptl/pthread_spin_trylock.c
+++ b/nptl/pthread_spin_trylock.c
@@ -19,9 +19,28 @@
#include <errno.h>
#include <atomic.h>
#include "pthreadP.h"
+#include <pthread_spin_parameters.h>
int
pthread_spin_trylock (pthread_spinlock_t *lock)
{
- return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
+ /* We use acquire MO to synchronize-with the release MO store in
+ pthread_spin_unlock, and thus ensure that prior critical sections
+ happen-before this critical section. */
+#if SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG == 1
+ /* Load and test the spinlock and only try to acquire the lock if it has
+ not been acquired. */
+ int val = atomic_load_relaxed (lock);
+ if (__glibc_likely (val == 0 && atomic_exchange_acquire (lock, 1) == 0))
+ return 0;
+#elif SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG == 0
+ /* Try to acquire the lock, which succeeds if the lock had not been
+ acquired. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
+ return 0;
+#else
+# error SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG has to be defined to 0 or 1
+#endif
+
+ return EBUSY;
}
diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
index 5fd73e5..f83b696 100644
--- a/nptl/pthread_spin_unlock.c
+++ b/nptl/pthread_spin_unlock.c
@@ -23,7 +23,9 @@
int
pthread_spin_unlock (pthread_spinlock_t *lock)
{
- atomic_full_barrier ();
- *lock = 0;
+ /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
+ or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
+ pthread_spin_trylock. */
+ atomic_store_release (lock, 0);
return 0;
}
diff --git a/sysdeps/aarch64/nptl/pthread_spin_lock.c b/sysdeps/aarch64/nptl/pthread_spin_lock.c
deleted file mode 100644
index fcfcb40..0000000
--- a/sysdeps/aarch64/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
-
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public License as
- published by the Free Software Foundation; either version 2.1 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/aarch64/nptl/pthread_spin_parameters.h b/sysdeps/aarch64/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..5fd319c
--- /dev/null
+++ b/sysdeps/aarch64/nptl/pthread_spin_parameters.h
@@ -0,0 +1,22 @@
+/* Parameters for generic pthread_spinlock_t implementation. aarch64 version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 0
+
+#include_next <pthread_spin_parameters.h>
diff --git a/sysdeps/arm/nptl/pthread_spin_lock.c b/sysdeps/arm/nptl/pthread_spin_lock.c
deleted file mode 100644
index 037b3b8..0000000
--- a/sysdeps/arm/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/arm/nptl/pthread_spin_parameters.h b/sysdeps/arm/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..3f8285a
--- /dev/null
+++ b/sysdeps/arm/nptl/pthread_spin_parameters.h
@@ -0,0 +1,22 @@
+/* Parameters for generic pthread_spinlock_t implementation. arm version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 0
+
+#include_next <pthread_spin_parameters.h>
diff --git a/sysdeps/hppa/nptl/pthread_spin_lock.c b/sysdeps/hppa/nptl/pthread_spin_lock.c
deleted file mode 100644
index 14f36a6..0000000
--- a/sysdeps/hppa/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2005-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/hppa/nptl/pthread_spin_parameters.h b/sysdeps/hppa/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..ebeb162
--- /dev/null
+++ b/sysdeps/hppa/nptl/pthread_spin_parameters.h
@@ -0,0 +1,22 @@
+/* Parameters for generic pthread_spinlock_t implementation. hppa version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 0
+
+#include_next <pthread_spin_parameters.h>
diff --git a/sysdeps/m68k/nptl/pthread_spin_lock.c b/sysdeps/m68k/nptl/pthread_spin_lock.c
deleted file mode 100644
index 62795f4..0000000
--- a/sysdeps/m68k/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2010-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Maxim Kuvyrkov <maxim@codesourcery.com>, 2010.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/m68k/nptl/pthread_spin_parameters.h b/sysdeps/m68k/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..b7b8581
--- /dev/null
+++ b/sysdeps/m68k/nptl/pthread_spin_parameters.h
@@ -0,0 +1,22 @@
+/* Parameters for generic pthread_spinlock_t implementation. m68k version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 0
+
+#include_next <pthread_spin_parameters.h>
diff --git a/sysdeps/microblaze/nptl/pthread_spin_lock.c b/sysdeps/microblaze/nptl/pthread_spin_lock.c
deleted file mode 100644
index fcfcb40..0000000
--- a/sysdeps/microblaze/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
-
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public License as
- published by the Free Software Foundation; either version 2.1 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/microblaze/nptl/pthread_spin_parameters.h b/sysdeps/microblaze/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..ef5827b
--- /dev/null
+++ b/sysdeps/microblaze/nptl/pthread_spin_parameters.h
@@ -0,0 +1,23 @@
+/* Parameters for generic pthread_spinlock_t implementation.
+ microblaze version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 0
+
+#include_next <pthread_spin_parameters.h>
diff --git a/sysdeps/mips/nptl/pthread_spin_lock.c b/sysdeps/mips/nptl/pthread_spin_lock.c
deleted file mode 100644
index 19d87a5..0000000
--- a/sysdeps/mips/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2012-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/mips/nptl/pthread_spin_parameters.h b/sysdeps/mips/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..4f03890
--- /dev/null
+++ b/sysdeps/mips/nptl/pthread_spin_parameters.h
@@ -0,0 +1,22 @@
+/* Parameters for generic pthread_spinlock_t implementation. mips version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 0
+
+#include_next <pthread_spin_parameters.h>
diff --git a/sysdeps/nios2/nptl/pthread_spin_lock.c b/sysdeps/nios2/nptl/pthread_spin_lock.c
deleted file mode 100644
index b203469..0000000
--- a/sysdeps/nios2/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* pthread spin-lock implementation for Nios II.
- Copyright (C) 2005-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/nios2/nptl/pthread_spin_parameters.h b/sysdeps/nios2/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..237edb3
--- /dev/null
+++ b/sysdeps/nios2/nptl/pthread_spin_parameters.h
@@ -0,0 +1,22 @@
+/* Parameters for generic pthread_spinlock_t implementation. nios2 version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 0
+
+#include_next <pthread_spin_parameters.h>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 2/2] S390: Use generic spinlock code.
2017-02-13 20:39 ` Torvald Riegel
@ 2017-02-15 16:26 ` Stefan Liebler
2017-02-18 17:05 ` Torvald Riegel
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-02-15 16:26 UTC (permalink / raw)
To: libc-alpha
[-- Attachment #1: Type: text/plain, Size: 3238 bytes --]
On 02/13/2017 09:39 PM, Torvald Riegel wrote:
> On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
>> This is an updated version of the patch, which adjusts the s390 specific
>> atomic-macros in the same way as in include/atomic.h.
>> Thus passing a volatile int pointer is fine, too.
>
> The general direction of this is okay.
> Some of my comments for patch 1/2 apply here as well (eg, volatile vs.
> atomics).
>
See answer in patch 1/2.
> What I don't like is the choice of 1000 for
> SPIN_LOCK_READS_BETWEEN_CMPXCHG. Have you run benchmarks to come up
> with this value, or is it a guess? Why isn't it documented how you end
> up with this number?
> We can keep these with a choice such as this, but then we need to have a
> FIXME comment in the code, explaining that this is just an arbitrary
> choice.
>
> I would guess that just spinning forever is sufficient, and that we
> don't need to throw in a CAS every now and then; using randomized
> exponential back-off might be more important. This is something that we
> would be in a better position to answer if you'd provide a
> microbenchmark for this choice too.
> At the end of 2016, I've posted a draft of a microbenchmark for rwlocks.
> Maybe you can use this as a start and run a few experiments?
>
I've run own benchmarks in the same manner as your mentioned
microbenchmark for rwlocks below.
You are right, I can't recognize a real difference between
#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
and
#define SPIN_LOCK_READS_BETWEEN_CMPXCHG -1
As it does not hurt, I prefer to use a CAS every 1000 plain reads.
A CAS is not necessary on current CPUs but from architecture
perspective, it is more correct if there is such a serialization
instruction.
There is a difference between
#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 0
and one of the others.
The same applies to
#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 1
It does not hurt if the lock is free, but there is a difference if the
lock is already acquired and trylock is called often.
I've saw your microbenchmark-post and added some notes.
I added a FIXME comment to re-evaluate the choice once we have the
appropriate microbenchmarks.
> Also, I'm not quite sure whether this number is really
> spinlock-specific, and I would like to find a better place for these.
> IMO, they should be in some header that contains default tuning
> parameters for synchronization code, which is provided by each
> architecture that uses the generic spinlock; we'd have no #ifdef for the
> tuning parameters, so we'd catch typos in those headers.
>
See pthread_spin_parameters.h in updated patch 1/2.
I've attached an updated patch due to the changes in patch 1/2 and added
comments to the macro definitions.
Bye.
Stefan
ChangeLog:
* sysdeps/s390/atomic-machine.h:
(__arch_compare_and_exchange_val_32_acq):
Cast type to omit volatile qualifier.
(__arch_compare_and_exchange_val_64_acq): Likewise.
(atomic_exchange_acq): Likewise.
* sysdeps/s390/nptl/pthread_spin_init.c: Delete File.
* sysdeps/s390/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_trylock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_unlock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_parameters.h: New File.
[-- Attachment #2: 20170215_s390_spinlock.patch --]
[-- Type: text/x-patch, Size: 10729 bytes --]
commit 6dc9da4a9c99524d5d6deb841811f1a8cc37c5b2
Author: Stefan Liebler <stli@linux.vnet.ibm.com>
Date: Wed Feb 15 17:22:38 2017 +0100
S390: Use generic spinlock code.
This patch removes the s390 specific implementation of spinlock code
and is now using the generic one.
For pthread_spin_trylock an explicit load and test before executing
compare and swap instruction is done as it is an interlock update even
if the lock is already acquired.
The macros in s390 specific atomic-machine.h are aligned in order to
omit the storing to and loading from stack.
ChangeLog:
* sysdeps/s390/atomic-machine.h:
(__arch_compare_and_exchange_val_32_acq):
Cast type to omit volatile qualifier.
(__arch_compare_and_exchange_val_64_acq): Likewise.
(atomic_exchange_acq): Likewise.
* sysdeps/s390/nptl/pthread_spin_init.c: Delete File.
* sysdeps/s390/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_trylock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_unlock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_parameters.h: New File.
diff --git a/sysdeps/s390/atomic-machine.h b/sysdeps/s390/atomic-machine.h
index 211d3d6..d98c836 100644
--- a/sysdeps/s390/atomic-machine.h
+++ b/sysdeps/s390/atomic-machine.h
@@ -54,7 +54,7 @@ typedef uintmax_t uatomic_max_t;
#define __arch_compare_and_exchange_val_32_acq(mem, newval, oldval) \
({ __typeof (mem) __archmem = (mem); \
- __typeof (*mem) __archold = (oldval); \
+ __typeof ((__typeof (*(mem))) *(mem)) __archold = (oldval); \
__asm__ __volatile__ ("cs %0,%2,%1" \
: "+d" (__archold), "=Q" (*__archmem) \
: "d" (newval), "m" (*__archmem) : "cc", "memory" ); \
@@ -64,7 +64,7 @@ typedef uintmax_t uatomic_max_t;
# define __HAVE_64B_ATOMICS 1
# define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \
({ __typeof (mem) __archmem = (mem); \
- __typeof (*mem) __archold = (oldval); \
+ __typeof ((__typeof (*(mem))) *(mem)) __archold = (oldval); \
__asm__ __volatile__ ("csg %0,%2,%1" \
: "+d" (__archold), "=Q" (*__archmem) \
: "d" ((long) (newval)), "m" (*__archmem) : "cc", "memory" ); \
@@ -86,8 +86,8 @@ typedef uintmax_t uatomic_max_t;
#ifdef __s390x__
# define atomic_exchange_acq(mem, newvalue) \
({ __typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_oldval = *__atg5_memp; \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval = *__atg5_memp; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
if (sizeof (*mem) == 4) \
__asm__ __volatile__ ("0: cs %0,%2,%1\n" \
" jl 0b" \
@@ -106,8 +106,8 @@ typedef uintmax_t uatomic_max_t;
#else
# define atomic_exchange_acq(mem, newvalue) \
({ __typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_oldval = *__atg5_memp; \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval = *__atg5_memp; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
if (sizeof (*mem) == 4) \
__asm__ __volatile__ ("0: cs %0,%2,%1\n" \
" jl 0b" \
diff --git a/sysdeps/s390/nptl/pthread_spin_init.c b/sysdeps/s390/nptl/pthread_spin_init.c
deleted file mode 100644
index d826871..0000000
--- a/sysdeps/s390/nptl/pthread_spin_init.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Not needed. pthread_spin_init is an alias for pthread_spin_unlock. */
diff --git a/sysdeps/s390/nptl/pthread_spin_lock.c b/sysdeps/s390/nptl/pthread_spin_lock.c
deleted file mode 100644
index 7349940..0000000
--- a/sysdeps/s390/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#include "pthreadP.h"
-
-int
-pthread_spin_lock (pthread_spinlock_t *lock)
-{
- int oldval;
-
- __asm__ __volatile__ ("0: lhi %0,0\n"
- " cs %0,%2,%1\n"
- " jl 0b"
- : "=&d" (oldval), "=Q" (*lock)
- : "d" (1), "m" (*lock) : "cc" );
- return 0;
-}
diff --git a/sysdeps/s390/nptl/pthread_spin_parameters.h b/sysdeps/s390/nptl/pthread_spin_parameters.h
new file mode 100644
index 0000000..b2ff166
--- /dev/null
+++ b/sysdeps/s390/nptl/pthread_spin_parameters.h
@@ -0,0 +1,36 @@
+/* Parameters for generic pthread_spinlock_t implementation. s390 version.
+ Copyright (C) 2017 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <http://www.gnu.org/licenses/>. */
+
+/* FIXME: Re-evaluate the defines below once we have an appropriate
+ microbenchmark.
+ See e.g. "RFC: shared-memory synchronization benchmarking in glibc"
+ (https://sourceware.org/ml/libc-alpha/2017-01/msg00168.html) */
+
+/* An own benchmark shows no difference between defining to '1000'
+ and '-1', but a positive result compared to '0' as a CAS instruction
+ would be used in a loop, which should be avoided on s390 due to cache-line
+ ping-pong. */
+#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
+
+/* An own benchmark showed a positive result if defined to '1'
+ and trylock is called often by different CPUs.
+ If the lock is not acquired and no other CPU is trying to
+ acquire the lock, then the additional load does not hurt. */
+#define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 1
+
+#include_next <pthread_spin_parameters.h>
diff --git a/sysdeps/s390/nptl/pthread_spin_trylock.c b/sysdeps/s390/nptl/pthread_spin_trylock.c
deleted file mode 100644
index 0e848da..0000000
--- a/sysdeps/s390/nptl/pthread_spin_trylock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#include <errno.h>
-#include "pthreadP.h"
-
-int
-pthread_spin_trylock (pthread_spinlock_t *lock)
-{
- int old;
-
- __asm__ __volatile__ ("cs %0,%3,%1"
- : "=d" (old), "=Q" (*lock)
- : "0" (0), "d" (1), "m" (*lock) : "cc" );
-
- return old != 0 ? EBUSY : 0;
-}
diff --git a/sysdeps/s390/nptl/pthread_spin_unlock.c b/sysdeps/s390/nptl/pthread_spin_unlock.c
deleted file mode 100644
index 54e7378..0000000
--- a/sysdeps/s390/nptl/pthread_spin_unlock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Ugly hack to avoid the declaration of pthread_spin_init. */
-#define pthread_spin_init pthread_spin_init_XXX
-#include "pthreadP.h"
-#undef pthread_spin_init
-
-int
-pthread_spin_unlock (pthread_spinlock_t *lock)
-{
- __asm__ __volatile__ (" xc %O0(4,%R0),%0\n"
- " bcr 15,0"
- : "=Q" (*lock) : "m" (*lock) : "cc" );
- return 0;
-}
-strong_alias (pthread_spin_unlock, pthread_spin_init)
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-15 9:36 ` Stefan Liebler
@ 2017-02-18 16:57 ` Torvald Riegel
2017-02-19 9:20 ` Florian Weimer
2017-02-20 12:15 ` Stefan Liebler
0 siblings, 2 replies; 63+ messages in thread
From: Torvald Riegel @ 2017-02-18 16:57 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha, Florian Weimer
On Wed, 2017-02-15 at 10:35 +0100, Stefan Liebler wrote:
> On 02/13/2017 09:29 PM, Torvald Riegel wrote:
> > Thanks for working on this. Detailed comments below.
> >
> > Generally, I think we need to keep working on optimizing this (this can
> > happen in follow-up patches). For example, we should have
> > microbenchmarks for the exchange vs. CAS choice.
> >
> > Also, some of the tuning knobs such as
> > SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG apply to atomics in general and
> > not just the spinlock. I'd prefer if these where in a state in which we
> > could add them as property that's part of the atomics interface.
> >
> > On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
> >> diff --git a/include/atomic.h b/include/atomic.h
> >> index 7f32640..770db4a 100644
> >> --- a/include/atomic.h
> >>
> >> +++ b/include/atomic.h
> >>
> >> @@ -54,7 +54,7 @@
> >> and following args. */
> >> #define __atomic_val_bysize(pre, post, mem, ...) \
> >> ({ \
> >> - __typeof (*mem) __atg1_result; \
> >>
> >> + __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
> >>
> >> if (sizeof (*mem) == 1) \
> >> __atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
> >> else if (sizeof (*mem) == 2) \
> >> @@ -162,9 +162,9 @@
> >> /* Store NEWVALUE in *MEM and return the old value. */
> >> #ifndef atomic_exchange_acq
> >> # define atomic_exchange_acq(mem, newvalue) \
> >> - ({ __typeof (*(mem)) __atg5_oldval; \
> >>
> >> + ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
> >>
> >> __typeof (mem) __atg5_memp = (mem); \
> >> - __typeof (*(mem)) __atg5_value = (newvalue); \
> >>
> >> + __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
> >>
> >> \
> >> do \
> >> __atg5_oldval = *__atg5_memp; \
> >> @@ -668,7 +668,7 @@ void __atomic_link_error (void);
> >>
> >> # ifndef atomic_load_relaxed
> >> # define atomic_load_relaxed(mem) \
> >> - ({ __typeof (*(mem)) __atg100_val; \
> >>
> >> + ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
> >>
> >> __asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
> >> __atg100_val; })
> >> # endif
> >
> > You could keep these changes, but it's a bit odd because you only apply
> > them for the functions you needed them for. I think it would be better
> > to just remove the volatile qualification in the caller (ie, cast lock
> > to nonvolatile in pthread_spin_lock etc.
> >
> Yes, I've only applied them for the functions needed in spinlock-code.
> Removing volatile from type pthread_spinlock_t is no option and
> casting the volatile pointer to a non-volatile pointer is undefined.
> See comment from Florian:
> On 12/16/2016 09:12 PM, Florian Weimer wrote:
> > That's undefined:
> >
> > “If an attempt is made to refer to an object defined with a
> > volatile-qualified type through use of an lvalue with
> > non-volatile-qualified type, the behavior is undefined.â€
> >
> > But we cannot drop the volatile qualifier from the definition of
> > pthread_spinlock_t because it would change the C++ mangling of
> > pthread_spinlock_t * and similar types.
Generally, I wouldn't agree with Florian's comment. However, all we are
interested in is the storage behind the volatile-qualified type. Users
aren't allowed the object through other means than the pthread_spin*
functions, so if we cast everywhere, we'll never have any
volatile-qualified accesses. I believe none of the architectures we
support makes weaker requirements on alignment for volatile-qualified
than for non-volatile-qualified types, so I can't see any problem in
practice with the cast.
> >>
> >> + if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
> >>
> >> return 0;
> >>
> >> + int val;
> >>
> >> do
> >> {
> >> /* The lock is contended and we need to wait. Going straight back
> >> @@ -50,20 +53,39 @@ pthread_spin_lock (pthread_spinlock_t *lock)
> >> On the other hand, we do want to update memory state on the local core
> >> once in a while to avoid spinning indefinitely until some event that
> >> will happen to update local memory as a side-effect. */
> >> - if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
> >>
> >> +
> >>
> >> +#if SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0
> >>
> >> + /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG plain reads between the
> >>
> >> + atomic compare and exchanges. */
> >>
> Also changed this comment to:
> /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG relaxed MO reads between
> the atomic compare and exchanges. */
Thanks.
> > A while ago we tried hard to remove all code that would fail silently
> > when a macro had a typo in the name, for example. We still have a few
> > of them left (e.g., in the atomics), but I think this here doesn't
> > warrant an exception.
> >
> Okay. You're right.
>
> In comment of patch 2/2, you've mentioned a header where an architecture
> shall define those parameters.
> Thus I've added the file nptl/pthread_spin_parameters.h.
I think the stub version should be in sysdeps/ but the wiki is missing
this information (default ENOTSUP location):
https://sourceware.org/glibc/wiki/Style_and_Conventions#Proper_sysdeps_Location
I think we should just get rid of SPIN_LOCK_READS_BETWEEN_CMPXCHG, and
make some choice for SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG. There is
no technical reason for throwing in a CAS every now and then, and so far
we have no evidence that it can improve performance (if that would be
the case, we'd need to think harder about that, because we have
spin-waiting loops elsewhere that don't want to modify the value after
waiting for a change of the value).
With that applied you don't have to solve the header problem in this
patch.
I'll write a separate email with suggestions about how to refactor the
spinlock code project-wide. Also, some more comments on the tuning
parameters below.
I'm still a bit undecided about how to deal with other arch's
pthread_spin_lock.c files that just set SPIN_LOCK_READS_BETWEEN_CMPXCHG
and then include the generic pthread_spin_lock.c. Maybe it's best if we
just remove them in this patch of yours.
> >>
> >> +#if SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG == 1
> >>
> >> + /* Load and test the spinlock and only try to lock the spinlock if it is
> >>
> >> + free. */
> >>
> >> + int val = atomic_load_relaxed (lock);
> >>
> >> + if (__glibc_likely (val == 0 && atomic_exchange_acquire (lock, 1) == 0))
> >
> > I think that's not quite the same as a choice between CAS and exchange.
> Yes. You are right.
> > Doing a load first could be helpful for *both* CAS and exchange. OTOH,
> > if we assume that trylock will succeed most of the time, then the load
> > is unnecessary and might be more costly (eg, if it causes the state of
> > the cache line to change twice).
> >
> E.g. on s390, there exists no instruction which atomically exchanges the
> value. Instead a CAS loop is used. The CAS instruction locks the
> cache-line exclusively whether the value in memory equals the expected
> old-value or not. Therefore the value is loaded and compared before
> using the CAS instruction.
> If no other CPU has accessed the lock-value, the load will cause
> the state of the cache line to exclusive.
> If the lock is not acquired, the subsequent CAS instruction does not
> need to change the state of the cache line.
> If another CPU has accessed the lock-value e.g. by acquiring the lock,
> the load will cause the state of the cache line either to read-only
> or exclusive. This depends on the other CPU - whether it has already
> stored a new value or not.
>
> As this behaviour depends on the architecture, the architecture has to
> decide whether it should load and test the lock-value before the
> atomic-macro.
I agree that the there are architecture-specific properties of atomic
operations that have a significant effect on performance. For s390, you
list the following points:
* atomic exchange (I suppose all atomic read-modify-write ops?) are
implemented through CAS.
* CAS always brings the cache line into an exclusive state.
(Is the second point correct? I'm not quite sure I understood you
correctly: for example, you write that a load move a cache line to an
exclusive state, which seems odd).
These properties are specific to the architecture, but they are not
specific to the synchronization code (eg, to spinlocks). Thus, I think
such settings should be in the atomics headers (i.e., in
atomic-machine.h).
This should probably be a separate patch. I would propose the following
macros (both are bool):
/* Nonzero iff all atomic read-modify-write operations (e.g., atomic
exchange) are implemented using a CAS loop. */
#define ATOMIC_RMW_USES_CAS 1
/* Nonzero iff CAS always assumes it will store, and thus has cache
performance effects similar to a store (e.g., it always puts the
respective cacheline into an exclusive state, even if the comparison
against the expected value fails). */
ATOMIC_CAS_ALWAYS_PREPARES_FOR_STORE 1
I'm not sure whether there are architectures for which the second macro
would not be true. It would be good to investigate this, maybe we don't
need to add this at all.
For the spin lock specifically, we have the following possibilities:
1) If we assume that trylock will most likely succeed in practice:
* We just do an exchange. The properties above don't matter.
2) If we want to bias towards cases where trylock succeeds, but don't
rule out contention:
* If exchange not a CAS loop, and exchange is faster than CAS, do an
exchange.
* If exchange is a CAS loop, use a weak CAS and not an exchange so we
bail out after the first failed attempt to change the state.
3) If we expect contention to be likely:
* If CAS always brings the cache line into an exclusive state, then load
first. Then do 2).
Do we have consensus yet on whether we assume 2 or 3 (I don't think 1
buys us anything over 2)?
> >> diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
> >> index 5fd73e5..f83b696 100644
> >> --- a/nptl/pthread_spin_unlock.c
> >>
> >> +++ b/nptl/pthread_spin_unlock.c
> >>
> >> @@ -23,7 +23,9 @@
> >> int
> >> pthread_spin_unlock (pthread_spinlock_t *lock)
> >> {
> >> - atomic_full_barrier ();
> >>
> >> - *lock = 0;
> >>
> >> + /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
> >>
> >> + or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
> >>
> >> + pthread_spin_trylock. */
> >>
> >> + atomic_store_release (lock, 0);
> >>
> >> return 0;
> >> }
> >
> > I agree with this change. However, depending on how one interprets
> > POSIX' memory model, one may expect lock releases to be sequentially
> > consistent. Nonetheless, IMO, glibc should use only release MO.
> >
> > But we need to announce this change. Some of us have been considering
> > an additional section in the manual were we specify where we deviate
> > from POSIX; this change might be the first we're listing there (though
> > to be fair, this is a deviation only on some architectures because on
> > others such as powerpc I think, we've been using release MO forever).
> >
> >
> As not all architectures use the generic spinlock implementation, what
> about a NEWS entry like:
>
> * The new generic spinlock implementation uses C11 like atomics.
> The pthread_spin_unlock implementation is now using release
> memory order instead of sequentially consistent memory order.
That's a good start, but I think we need to be more specific. We also
don't need to say that we use C11-like atomics because that's an
implementation detail.
I'd add something like this instead:
The synchronization that pthread_spin_unlock performs has been changed
to now be equivalent to a C11 atomic store with release memory order to
the spin lock's memory location. This ensures correct synchronization
for the spin lock's operations and critical sections protected by a spin
lock. Previously, several (but not all) architectures used stronger
synchronization (e.g., containing what is often called a full barrier).
This change can improve performance, but may affect odd fringe uses of
spin locks that depend on the previous behavior (e.g., using spin locks
as atomic variables to try to implement Dekker's mutual exclusion
algorithm).
This should highlight the potential change for the weird (ab)uses of
spin locks but also makes it clear that this won't affect correctness of
all the common code.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 2/2] S390: Use generic spinlock code.
2017-02-15 16:26 ` Stefan Liebler
@ 2017-02-18 17:05 ` Torvald Riegel
2017-03-14 15:55 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-02-18 17:05 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Wed, 2017-02-15 at 17:26 +0100, Stefan Liebler wrote:
> On 02/13/2017 09:39 PM, Torvald Riegel wrote:
> > On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
> >> This is an updated version of the patch, which adjusts the s390 specific
> >> atomic-macros in the same way as in include/atomic.h.
> >> Thus passing a volatile int pointer is fine, too.
> >
> > The general direction of this is okay.
> > Some of my comments for patch 1/2 apply here as well (eg, volatile vs.
> > atomics).
> >
> See answer in patch 1/2.
>
> > What I don't like is the choice of 1000 for
> > SPIN_LOCK_READS_BETWEEN_CMPXCHG. Have you run benchmarks to come up
> > with this value, or is it a guess? Why isn't it documented how you end
> > up with this number?
> > We can keep these with a choice such as this, but then we need to have a
> > FIXME comment in the code, explaining that this is just an arbitrary
> > choice.
> >
> > I would guess that just spinning forever is sufficient, and that we
> > don't need to throw in a CAS every now and then; using randomized
> > exponential back-off might be more important. This is something that we
> > would be in a better position to answer if you'd provide a
> > microbenchmark for this choice too.
> > At the end of 2016, I've posted a draft of a microbenchmark for rwlocks.
> > Maybe you can use this as a start and run a few experiments?
> >
> I've run own benchmarks in the same manner as your mentioned
> microbenchmark for rwlocks below.
> You are right, I can't recognize a real difference between
> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
> and
> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG -1
>
> As it does not hurt, I prefer to use a CAS every 1000 plain reads.
> A CAS is not necessary on current CPUs but from architecture
> perspective, it is more correct if there is such a serialization
> instruction.
What do you mean by "more correct"? I'm not aware of an architecture
that would not ensure that stores on one CPU will eventually become
visible to other CPUs.
Thus, as I wrote in my review of patch 1/2, I think we should just
remove the occassional CAS (ie, just do the equivalent of the -1
setting, always).
> There is a difference between
> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG 0
> and one of the others.
Right. We do want to spin if the lock is acquired by another thread.
What we should do in a future patch is to experiment with the back-off
between loads. tile already has some code for this, which we at least
need to integrate at some point.
> The same applies to
> #define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 1
> It does not hurt if the lock is free, but there is a difference if the
> lock is already acquired and trylock is called often.
Yes. I've replied to this point in the 1/2 patch thread.
> I've saw your microbenchmark-post and added some notes.
Thanks. I'll get to them later.
> I added a FIXME comment to re-evaluate the choice once we have the
> appropriate microbenchmarks.
>
> > Also, I'm not quite sure whether this number is really
> > spinlock-specific, and I would like to find a better place for these.
> > IMO, they should be in some header that contains default tuning
> > parameters for synchronization code, which is provided by each
> > architecture that uses the generic spinlock; we'd have no #ifdef for the
> > tuning parameters, so we'd catch typos in those headers.
> >
> See pthread_spin_parameters.h in updated patch 1/2.
I suggest that we'll work towards consensus on patch 1/2 first. I
believe once that is done, patch 2/2 would likely just remove s390 code.
Thanks for continuing the work on this. I know we have some back and
forth here in terms of overall direction, but I also think we're making
progress and are continually improving the changes.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-18 16:57 ` Torvald Riegel
@ 2017-02-19 9:20 ` Florian Weimer
2017-02-20 13:11 ` Torvald Riegel
2017-02-20 12:15 ` Stefan Liebler
1 sibling, 1 reply; 63+ messages in thread
From: Florian Weimer @ 2017-02-19 9:20 UTC (permalink / raw)
To: Torvald Riegel; +Cc: Stefan Liebler, libc-alpha
* Torvald Riegel:
>> On 12/16/2016 09:12 PM, Florian Weimer wrote:
>> > That's undefined:
>> >
>> > “If an attempt is made to refer to an object defined with a
>> > volatile-qualified type through use of an lvalue with
>> > non-volatile-qualified type, the behavior is undefined.”
>> >
>> > But we cannot drop the volatile qualifier from the definition of
>> > pthread_spinlock_t because it would change the C++ mangling of
>> > pthread_spinlock_t * and similar types.
>
> Generally, I wouldn't agree with Florian's comment. However, all we are
> interested in is the storage behind the volatile-qualified type. Users
> aren't allowed the object through other means than the pthread_spin*
> functions, so if we cast everywhere, we'll never have any
> volatile-qualified accesses.
The spinlock is defined with the volatile qualifier. This means that
accesses without the qualifier are undefined.
> I believe none of the architectures we
> support makes weaker requirements on alignment for volatile-qualified
> than for non-volatile-qualified types, so I can't see any problem in
> practice with the cast.
We also need separate compilation or some other optimization barrier.
If GCC can prove that code accesses a volatile object in this matter,
it can assume that the code never executes and eliminate it (and its
surrounding code).
We could talk to the GCC folks and ask for a suitable GCC extension.
Like you said, there shouldn't be any ABI concerns which would make
this difficult.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-18 16:57 ` Torvald Riegel
2017-02-19 9:20 ` Florian Weimer
@ 2017-02-20 12:15 ` Stefan Liebler
2017-02-20 13:51 ` Torvald Riegel
1 sibling, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-02-20 12:15 UTC (permalink / raw)
To: libc-alpha
On 02/18/2017 05:57 PM, Torvald Riegel wrote:
> On Wed, 2017-02-15 at 10:35 +0100, Stefan Liebler wrote:
>> On 02/13/2017 09:29 PM, Torvald Riegel wrote:
>>> Thanks for working on this. Detailed comments below.
>>>
>>> Generally, I think we need to keep working on optimizing this (this can
>>> happen in follow-up patches). For example, we should have
>>> microbenchmarks for the exchange vs. CAS choice.
>>>
>>> Also, some of the tuning knobs such as
>>> SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG apply to atomics in general and
>>> not just the spinlock. I'd prefer if these where in a state in which we
>>> could add them as property that's part of the atomics interface.
>>>
>>> On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
>>>> diff --git a/include/atomic.h b/include/atomic.h
>>>> index 7f32640..770db4a 100644
>>>> --- a/include/atomic.h
>>>>
>>>> +++ b/include/atomic.h
>>>>
>>>> @@ -54,7 +54,7 @@
>>>> and following args. */
>>>> #define __atomic_val_bysize(pre, post, mem, ...) \
>>>> ({ \
>>>> - __typeof (*mem) __atg1_result; \
>>>>
>>>> + __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
>>>>
>>>> if (sizeof (*mem) == 1) \
>>>> __atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
>>>> else if (sizeof (*mem) == 2) \
>>>> @@ -162,9 +162,9 @@
>>>> /* Store NEWVALUE in *MEM and return the old value. */
>>>> #ifndef atomic_exchange_acq
>>>> # define atomic_exchange_acq(mem, newvalue) \
>>>> - ({ __typeof (*(mem)) __atg5_oldval; \
>>>>
>>>> + ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
>>>>
>>>> __typeof (mem) __atg5_memp = (mem); \
>>>> - __typeof (*(mem)) __atg5_value = (newvalue); \
>>>>
>>>> + __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
>>>>
>>>> \
>>>> do \
>>>> __atg5_oldval = *__atg5_memp; \
>>>> @@ -668,7 +668,7 @@ void __atomic_link_error (void);
>>>>
>>>> # ifndef atomic_load_relaxed
>>>> # define atomic_load_relaxed(mem) \
>>>> - ({ __typeof (*(mem)) __atg100_val; \
>>>>
>>>> + ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
>>>>
>>>> __asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
>>>> __atg100_val; })
>>>> # endif
>>>
>>> You could keep these changes, but it's a bit odd because you only apply
>>> them for the functions you needed them for. I think it would be better
>>> to just remove the volatile qualification in the caller (ie, cast lock
>>> to nonvolatile in pthread_spin_lock etc.
>>>
>> Yes, I've only applied them for the functions needed in spinlock-code.
>> Removing volatile from type pthread_spinlock_t is no option and
>> casting the volatile pointer to a non-volatile pointer is undefined.
>> See comment from Florian:
>> On 12/16/2016 09:12 PM, Florian Weimer wrote:
>>> That's undefined:
>>>
>>> “If an attempt is made to refer to an object defined with a
>>> volatile-qualified type through use of an lvalue with
>>> non-volatile-qualified type, the behavior is undefined.â€
>>>
>>> But we cannot drop the volatile qualifier from the definition of
>>> pthread_spinlock_t because it would change the C++ mangling of
>>> pthread_spinlock_t * and similar types.
>
> Generally, I wouldn't agree with Florian's comment. However, all we are
> interested in is the storage behind the volatile-qualified type. Users
> aren't allowed the object through other means than the pthread_spin*
> functions, so if we cast everywhere, we'll never have any
> volatile-qualified accesses. I believe none of the architectures we
> support makes weaker requirements on alignment for volatile-qualified
> than for non-volatile-qualified types, so I can't see any problem in
> practice with the cast.
>
>
>>>>
>>>> + if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
>>>>
>>>> return 0;
>>>>
>>>> + int val;
>>>>
>>>> do
>>>> {
>>>> /* The lock is contended and we need to wait. Going straight back
>>>> @@ -50,20 +53,39 @@ pthread_spin_lock (pthread_spinlock_t *lock)
>>>> On the other hand, we do want to update memory state on the local core
>>>> once in a while to avoid spinning indefinitely until some event that
>>>> will happen to update local memory as a side-effect. */
>>>> - if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
>>>>
>>>> +
>>>>
>>>> +#if SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0
>>>>
>>>> + /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG plain reads between the
>>>>
>>>> + atomic compare and exchanges. */
>>>>
>> Also changed this comment to:
>> /* Use at most SPIN_LOCK_READS_BETWEEN_CMPXCHG relaxed MO reads between
>> the atomic compare and exchanges. */
>
> Thanks.
>
>>> A while ago we tried hard to remove all code that would fail silently
>>> when a macro had a typo in the name, for example. We still have a few
>>> of them left (e.g., in the atomics), but I think this here doesn't
>>> warrant an exception.
>>>
>> Okay. You're right.
>>
>> In comment of patch 2/2, you've mentioned a header where an architecture
>> shall define those parameters.
>> Thus I've added the file nptl/pthread_spin_parameters.h.
>
> I think the stub version should be in sysdeps/ but the wiki is missing
> this information (default ENOTSUP location):
> https://sourceware.org/glibc/wiki/Style_and_Conventions#Proper_sysdeps_Location
In case we need a new header, shall we move it to sysdeps/nptl/ ?
>
> I think we should just get rid of SPIN_LOCK_READS_BETWEEN_CMPXCHG, and
> make some choice for SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG. There is
> no technical reason for throwing in a CAS every now and then, and so far
> we have no evidence that it can improve performance (if that would be
> the case, we'd need to think harder about that, because we have
> spin-waiting loops elsewhere that don't want to modify the value after
> waiting for a change of the value).
Okay. For s390 we don't need a CAS every now and then.
>
> With that applied you don't have to solve the header problem in this
> patch.
>
> I'll write a separate email with suggestions about how to refactor the
> spinlock code project-wide. Also, some more comments on the tuning
> parameters below.
>
> I'm still a bit undecided about how to deal with other arch's
> pthread_spin_lock.c files that just set SPIN_LOCK_READS_BETWEEN_CMPXCHG
> and then include the generic pthread_spin_lock.c. Maybe it's best if we
> just remove them in this patch of yours.
>
I think the archs currently using the generic implementation have just
copied the default value to get rid of the warning "machine-dependent
file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG". But this is only an
assumption.
In general removing those "wrapper"-pthread_spin_lock.c files and using
information from a header like the proposed pthread_spin_parameters.h or
atomic-machine.h is a good approach.
>>>>
>>>> +#if SPIN_TRYLOCK_USE_CMPXCHG_INSTEAD_OF_XCHG == 1
>>>>
>>>> + /* Load and test the spinlock and only try to lock the spinlock if it is
>>>>
>>>> + free. */
>>>>
>>>> + int val = atomic_load_relaxed (lock);
>>>>
>>>> + if (__glibc_likely (val == 0 && atomic_exchange_acquire (lock, 1) == 0))
>>>
>>> I think that's not quite the same as a choice between CAS and exchange.
>> Yes. You are right.
>>> Doing a load first could be helpful for *both* CAS and exchange. OTOH,
>>> if we assume that trylock will succeed most of the time, then the load
>>> is unnecessary and might be more costly (eg, if it causes the state of
>>> the cache line to change twice).
>>>
>> E.g. on s390, there exists no instruction which atomically exchanges the
>> value. Instead a CAS loop is used. The CAS instruction locks the
>> cache-line exclusively whether the value in memory equals the expected
>> old-value or not. Therefore the value is loaded and compared before
>> using the CAS instruction.
>> If no other CPU has accessed the lock-value, the load will cause
>> the state of the cache line to exclusive.
>> If the lock is not acquired, the subsequent CAS instruction does not
>> need to change the state of the cache line.
>> If another CPU has accessed the lock-value e.g. by acquiring the lock,
>> the load will cause the state of the cache line either to read-only
>> or exclusive. This depends on the other CPU - whether it has already
>> stored a new value or not.
>>
>> As this behaviour depends on the architecture, the architecture has to
>> decide whether it should load and test the lock-value before the
>> atomic-macro.
>
> I agree that the there are architecture-specific properties of atomic
> operations that have a significant effect on performance. For s390, you
> list the following points:
> * atomic exchange (I suppose all atomic read-modify-write ops?) are
> implemented through CAS.
atomic exchange is implemented by a CAS loop due to lack of an exchange
instruction. For exchanging to a "0", s390 can use the load-and-and
instruction instead of a CAS loop (See my atomic-machine.h patch; For
gcc, we plan to emit such a load-and-and instruction for builtin
__atomic_exchange_n in future;). This also saves one register usage
compared to the CAS loop.
Exchanging to "0" is e.g. used for lll_unlock macro or in
malloc_consolidate.
Starting with z196 zarch CPUs, the following instructions which are used
by the appropriate __atomic_fetch_xyz builtins instead of a CAS loop:
load-and-add, load-and-and, load-and-exclusive-or, load-and-or.
As information:
I will update my atomic-machine.h patch to use at least some of the C11
atomic builtins or all depending on gcc version.
As additional information:
E.g. RHEL 7 / SLES 12 are using z196 as architecture baseline level.
A 64bit s390x glibc build always use zarch instructions.
A 31bit s390 glibc build does not use zarch instructions by default, but
somebody can build glibc with gcc -mzarch option.
The latter means, that a CAS loop is used for a default 31bit s390 build.
> * CAS always brings the cache line into an exclusive state.
Yes that's true.
>
> (Is the second point correct? I'm not quite sure I understood you
> correctly: for example, you write that a load move a cache line to an
> exclusive state, which seems odd).
Not in all cases, but in the case if no other CPU accesses this cache
line. Otherwise it is read-only.
>
> These properties are specific to the architecture, but they are not
> specific to the synchronization code (eg, to spinlocks). Thus, I think
> such settings should be in the atomics headers (i.e., in
> atomic-machine.h).
> This should probably be a separate patch. I would propose the following
> macros (both are bool):
> /* Nonzero iff all atomic read-modify-write operations (e.g., atomic
> exchange) are implemented using a CAS loop. */
> #define ATOMIC_RMW_USES_CAS 1
Is one macro enough to describe all read-modify-write operations in
include/atomic.h?
Please also see my comment above.
> /* Nonzero iff CAS always assumes it will store, and thus has cache
> performance effects similar to a store (e.g., it always puts the
> respective cacheline into an exclusive state, even if the comparison
> against the expected value fails). */
> ATOMIC_CAS_ALWAYS_PREPARES_FOR_STORE 1
>
> I'm not sure whether there are architectures for which the second macro
> would not be true. It would be good to investigate this, maybe we don't
> need to add this at all.
>
We plan that in future gcc will emit e.g. a load-and-test instruction in
front of the CAS instruction if the old-value is a constant zero.
>
>
> For the spin lock specifically, we have the following possibilities:
>
> 1) If we assume that trylock will most likely succeed in practice:
> * We just do an exchange. The properties above don't matter.
>
> 2) If we want to bias towards cases where trylock succeeds, but don't
> rule out contention:
> * If exchange not a CAS loop, and exchange is faster than CAS, do an
> exchange.
> * If exchange is a CAS loop, use a weak CAS and not an exchange so we
> bail out after the first failed attempt to change the state.
>
> 3) If we expect contention to be likely:
> * If CAS always brings the cache line into an exclusive state, then load
> first. Then do 2).
>
> Do we have consensus yet on whether we assume 2 or 3 (I don't think 1
> buys us anything over 2)?
>
Yes. Sounds good.
>
>>>> diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
>>>> index 5fd73e5..f83b696 100644
>>>> --- a/nptl/pthread_spin_unlock.c
>>>>
>>>> +++ b/nptl/pthread_spin_unlock.c
>>>>
>>>> @@ -23,7 +23,9 @@
>>>> int
>>>> pthread_spin_unlock (pthread_spinlock_t *lock)
>>>> {
>>>> - atomic_full_barrier ();
>>>>
>>>> - *lock = 0;
>>>>
>>>> + /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
>>>>
>>>> + or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
>>>>
>>>> + pthread_spin_trylock. */
>>>>
>>>> + atomic_store_release (lock, 0);
>>>>
>>>> return 0;
>>>> }
>>>
>>> I agree with this change. However, depending on how one interprets
>>> POSIX' memory model, one may expect lock releases to be sequentially
>>> consistent. Nonetheless, IMO, glibc should use only release MO.
>>>
>>> But we need to announce this change. Some of us have been considering
>>> an additional section in the manual were we specify where we deviate
>>> from POSIX; this change might be the first we're listing there (though
>>> to be fair, this is a deviation only on some architectures because on
>>> others such as powerpc I think, we've been using release MO forever).
>>>
>>>
>> As not all architectures use the generic spinlock implementation, what
>> about a NEWS entry like:
>>
>> * The new generic spinlock implementation uses C11 like atomics.
>> The pthread_spin_unlock implementation is now using release
>> memory order instead of sequentially consistent memory order.
>
> That's a good start, but I think we need to be more specific. We also
> don't need to say that we use C11-like atomics because that's an
> implementation detail.
>
> I'd add something like this instead:
>
> The synchronization that pthread_spin_unlock performs has been changed
> to now be equivalent to a C11 atomic store with release memory order to
> the spin lock's memory location. This ensures correct synchronization
> for the spin lock's operations and critical sections protected by a spin
> lock. Previously, several (but not all) architectures used stronger
> synchronization (e.g., containing what is often called a full barrier).
> This change can improve performance, but may affect odd fringe uses of
> spin locks that depend on the previous behavior (e.g., using spin locks
> as atomic variables to try to implement Dekker's mutual exclusion
> algorithm).
>
> This should highlight the potential change for the weird (ab)uses of
> spin locks but also makes it clear that this won't affect correctness of
> all the common code.
>
Okay. The next patch-iteration will use the text above.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-19 9:20 ` Florian Weimer
@ 2017-02-20 13:11 ` Torvald Riegel
2017-02-26 7:55 ` Florian Weimer
0 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-02-20 13:11 UTC (permalink / raw)
To: Florian Weimer; +Cc: Stefan Liebler, libc-alpha
On Sun, 2017-02-19 at 10:20 +0100, Florian Weimer wrote:
> * Torvald Riegel:
>
> >> On 12/16/2016 09:12 PM, Florian Weimer wrote:
> >> > That's undefined:
> >> >
> >> > “If an attempt is made to refer to an object defined with a
> >> > volatile-qualified type through use of an lvalue with
> >> > non-volatile-qualified type, the behavior is undefined.â€
> >> >
> >> > But we cannot drop the volatile qualifier from the definition of
> >> > pthread_spinlock_t because it would change the C++ mangling of
> >> > pthread_spinlock_t * and similar types.
> >
> > Generally, I wouldn't agree with Florian's comment. However, all we are
> > interested in is the storage behind the volatile-qualified type. Users
> > aren't allowed the object through other means than the pthread_spin*
> > functions, so if we cast everywhere, we'll never have any
> > volatile-qualified accesses.
>
> The spinlock is defined with the volatile qualifier. This means that
> accesses without the qualifier are undefined.
The footnote for 6.7.3p6 (footnote 133, N1570) reads:
This applies to those objects that behave as if they were defined with
qualified types, even if they are
never actually defined as objects in the program (such as an object at a
memory-mapped input/output
address).
I don't remember whether footnotes are normative, but this doesn't apply
in our case.
> > I believe none of the architectures we
> > support makes weaker requirements on alignment for volatile-qualified
> > than for non-volatile-qualified types, so I can't see any problem in
> > practice with the cast.
>
> We also need separate compilation or some other optimization barrier.
Also consider 2.14.2 in
https://www.cl.cam.ac.uk/~pes20/cerberus/notes30-full.pdf
This states that one can cast between a union and the pointers to
individual parts of a union. If the spinlock's underlying type and the
volatile-qualified type both have the same size+alignment, then the
union will have the same size and alignment too.
In our virtual union, we only ever use the non-volatile member (users
are not allowed to acccess spinlocks other than through pthread_spin_*
functions, which don't use volatile-qualified accesses). But we pass
the pointer to the volatile member around as handle to the spinlock.
Thus, I'm not concerned about the cast from volatile-qualified to
non-volatile-qualified in this particular case.
Maybe its best to just change pthread_spinlock_t from volatile int to
int. The generic spinlock uses only atomic ops with Stefan's changes,
so that's okay for at least the archs that use the generic code; for all
others, we could either keep them as is or change it and confirm that
the custom code they use doesn't rely on the volatile.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-20 12:15 ` Stefan Liebler
@ 2017-02-20 13:51 ` Torvald Riegel
2017-03-14 15:55 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-02-20 13:51 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Mon, 2017-02-20 at 13:15 +0100, Stefan Liebler wrote:
> >>> A while ago we tried hard to remove all code that would fail silently
> >>> when a macro had a typo in the name, for example. We still have a few
> >>> of them left (e.g., in the atomics), but I think this here doesn't
> >>> warrant an exception.
> >>>
> >> Okay. You're right.
> >>
> >> In comment of patch 2/2, you've mentioned a header where an architecture
> >> shall define those parameters.
> >> Thus I've added the file nptl/pthread_spin_parameters.h.
> >
> > I think the stub version should be in sysdeps/ but the wiki is missing
> > this information (default ENOTSUP location):
> > https://sourceware.org/glibc/wiki/Style_and_Conventions#Proper_sysdeps_Location
> In case we need a new header, shall we move it to sysdeps/nptl/ ?
I would guess that this would be the right place for a stub / generic
variant of such a header, but I'm not quite sure.
> >
> > I'm still a bit undecided about how to deal with other arch's
> > pthread_spin_lock.c files that just set SPIN_LOCK_READS_BETWEEN_CMPXCHG
> > and then include the generic pthread_spin_lock.c. Maybe it's best if we
> > just remove them in this patch of yours.
> >
> I think the archs currently using the generic implementation have just
> copied the default value to get rid of the warning "machine-dependent
> file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG". But this is only an
> assumption.
> In general removing those "wrapper"-pthread_spin_lock.c files and using
> information from a header like the proposed pthread_spin_parameters.h or
> atomic-machine.h is a good approach.
Okay. So let's do that.
> > I agree that the there are architecture-specific properties of atomic
> > operations that have a significant effect on performance. For s390, you
> > list the following points:
> > * atomic exchange (I suppose all atomic read-modify-write ops?) are
> > implemented through CAS.
> atomic exchange is implemented by a CAS loop due to lack of an exchange
> instruction. For exchanging to a "0", s390 can use the load-and-and
> instruction instead of a CAS loop (See my atomic-machine.h patch; For
> gcc, we plan to emit such a load-and-and instruction for builtin
> __atomic_exchange_n in future;). This also saves one register usage
> compared to the CAS loop.
> Exchanging to "0" is e.g. used for lll_unlock macro or in
> malloc_consolidate.
I guess this may then be yet another property atomic-machine.h could
expose: Whether an atomic fetch-and-and exists and is not implemented
throough a CAS loop. Something like lll_unlock would then do an
exchange or fetch-and-and, and if that fails, a CAS loop.
> Starting with z196 zarch CPUs, the following instructions which are used
> by the appropriate __atomic_fetch_xyz builtins instead of a CAS loop:
> load-and-add, load-and-and, load-and-exclusive-or, load-and-or.
> As information:
> I will update my atomic-machine.h patch to use at least some of the C11
> atomic builtins or all depending on gcc version.
Thanks.
> > These properties are specific to the architecture, but they are not
> > specific to the synchronization code (eg, to spinlocks). Thus, I think
> > such settings should be in the atomics headers (i.e., in
> > atomic-machine.h).
> > This should probably be a separate patch. I would propose the following
> > macros (both are bool):
> > /* Nonzero iff all atomic read-modify-write operations (e.g., atomic
> > exchange) are implemented using a CAS loop. */
> > #define ATOMIC_RMW_USES_CAS 1
> Is one macro enough to describe all read-modify-write operations in
> include/atomic.h?
> Please also see my comment above.
Yes, it may not be enough (e.g., you say that s390 may have fetch_and
but not an exchange, but other archs may just have an exchange but no
custom fetch_and).
So maybe we should add ATOMIC_EXCHANGE_USES_CAS and
ATOMIC_FETCH_AND_USES_CAS for now, and add further ones on demand?
> > /* Nonzero iff CAS always assumes it will store, and thus has cache
> > performance effects similar to a store (e.g., it always puts the
> > respective cacheline into an exclusive state, even if the comparison
> > against the expected value fails). */
> > ATOMIC_CAS_ALWAYS_PREPARES_FOR_STORE 1
> >
> > I'm not sure whether there are architectures for which the second macro
> > would not be true. It would be good to investigate this, maybe we don't
> > need to add this at all.
> >
> We plan that in future gcc will emit e.g. a load-and-test instruction in
> front of the CAS instruction if the old-value is a constant zero.
That can be useful, but what I outlined would be about a more generic
case. If you are going to solve this for your arch in gcc, you might
not need to address this in this patch.
> >
> >
> > For the spin lock specifically, we have the following possibilities:
> >
> > 1) If we assume that trylock will most likely succeed in practice:
> > * We just do an exchange. The properties above don't matter.
> >
> > 2) If we want to bias towards cases where trylock succeeds, but don't
> > rule out contention:
> > * If exchange not a CAS loop, and exchange is faster than CAS, do an
> > exchange.
> > * If exchange is a CAS loop, use a weak CAS and not an exchange so we
> > bail out after the first failed attempt to change the state.
> >
> > 3) If we expect contention to be likely:
> > * If CAS always brings the cache line into an exclusive state, then load
> > first. Then do 2).
> >
> > Do we have consensus yet on whether we assume 2 or 3 (I don't think 1
> > buys us anything over 2)?
> >
> Yes. Sounds good.
I read this as stating that you agree that 1) doesn't need to be
considered. But we still to choose between 2) and 3) :)
I'm not quite sure what to favor because some of the code out there that
uses trylock just uses it to prevent deadlock (e.g., when trying to
acquire multiple locks at once), whereas other code uses spin_trylock to
implement their own back-off and bounded spinning.
I lean towards assuming that lock acquisitons, including the former use
case for trylock, are supposed to succeed in the common case. That is,
I would pick 2), but I have no data to back this up.
Either way, whatever we choose, we should document polish the cases 1-3
above and the reasoning behind our choice for one of them, and add it as
a comment to the spinlock code.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-20 13:11 ` Torvald Riegel
@ 2017-02-26 7:55 ` Florian Weimer
2017-02-26 20:06 ` Torvald Riegel
0 siblings, 1 reply; 63+ messages in thread
From: Florian Weimer @ 2017-02-26 7:55 UTC (permalink / raw)
To: Torvald Riegel; +Cc: Stefan Liebler, libc-alpha
* Torvald Riegel:
> On Sun, 2017-02-19 at 10:20 +0100, Florian Weimer wrote:
>> * Torvald Riegel:
>>
>> >> On 12/16/2016 09:12 PM, Florian Weimer wrote:
>> >> > That's undefined:
>> >> >
>> >> > “If an attempt is made to refer to an object defined with a
>> >> > volatile-qualified type through use of an lvalue with
>> >> > non-volatile-qualified type, the behavior is undefined.”
>> >> >
>> >> > But we cannot drop the volatile qualifier from the definition of
>> >> > pthread_spinlock_t because it would change the C++ mangling of
>> >> > pthread_spinlock_t * and similar types.
>> >
>> > Generally, I wouldn't agree with Florian's comment. However, all we are
>> > interested in is the storage behind the volatile-qualified type. Users
>> > aren't allowed the object through other means than the pthread_spin*
>> > functions, so if we cast everywhere, we'll never have any
>> > volatile-qualified accesses.
>>
>> The spinlock is defined with the volatile qualifier. This means that
>> accesses without the qualifier are undefined.
>
> The footnote for 6.7.3p6 (footnote 133, N1570) reads:
> This applies to those objects that behave as if they were defined with
> qualified types, even if they are
> never actually defined as objects in the program (such as an object at a
> memory-mapped input/output
> address).
>
> I don't remember whether footnotes are normative,
They are not.
> but this doesn't apply in our case.
I think it's a clarification intended to *extend* the scope of the
paragraph to objects not defined using C language elments. It's not
intended to restrict this paragraph to such objects only. The
footnote is not particularly meaningful anyway because it discusses
certain vendor extensions whose behavior is not described by the
standard.
(And on GNU, objects created by mmap or dlopen are not implicitly
volatile.)
>> > I believe none of the architectures we
>> > support makes weaker requirements on alignment for volatile-qualified
>> > than for non-volatile-qualified types, so I can't see any problem in
>> > practice with the cast.
>>
>> We also need separate compilation or some other optimization barrier.
>
> Also consider 2.14.2 in
> https://www.cl.cam.ac.uk/~pes20/cerberus/notes30-full.pdf
Not sure how this applies here. There's no volatile qualifier in
there.
> This states that one can cast between a union and the pointers to
> individual parts of a union. If the spinlock's underlying type and the
> volatile-qualified type both have the same size+alignment, then the
> union will have the same size and alignment too.
> In our virtual union, we only ever use the non-volatile member (users
> are not allowed to acccess spinlocks other than through pthread_spin_*
> functions, which don't use volatile-qualified accesses). But we pass
> the pointer to the volatile member around as handle to the spinlock.
We also need to cover the case when a spinlock is defined like this:
static pthread_spinlock_t lock;
And I don't see a way to get rid of the volatile there without a
compiler extension.
We cannot introduce an union here because …
> Maybe its best to just change pthread_spinlock_t from volatile int to
> int.
… like this, it would change the C++ name mangling of anything related
to pthread_spinlock_t. It is defined as a typedef, so the mangling
uses the definition to refer to the type, not the name, according to
the language rules, where typedef does not create a new type, and
typedefs with the same definition can be used interchangeably.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-26 7:55 ` Florian Weimer
@ 2017-02-26 20:06 ` Torvald Riegel
2017-02-26 20:29 ` Florian Weimer
0 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-02-26 20:06 UTC (permalink / raw)
To: Florian Weimer; +Cc: Stefan Liebler, libc-alpha
On Sun, 2017-02-26 at 08:55 +0100, Florian Weimer wrote:
> * Torvald Riegel:
>
> > On Sun, 2017-02-19 at 10:20 +0100, Florian Weimer wrote:
> >> * Torvald Riegel:
> >>
> >> >> On 12/16/2016 09:12 PM, Florian Weimer wrote:
> >> >> > That's undefined:
> >> >> >
> >> >> > “If an attempt is made to refer to an object defined with a
> >> >> > volatile-qualified type through use of an lvalue with
> >> >> > non-volatile-qualified type, the behavior is undefined.â€
> >> >> >
> >> >> > But we cannot drop the volatile qualifier from the definition of
> >> >> > pthread_spinlock_t because it would change the C++ mangling of
> >> >> > pthread_spinlock_t * and similar types.
> >> >
> >> > Generally, I wouldn't agree with Florian's comment. However, all we are
> >> > interested in is the storage behind the volatile-qualified type. Users
> >> > aren't allowed the object through other means than the pthread_spin*
> >> > functions, so if we cast everywhere, we'll never have any
> >> > volatile-qualified accesses.
> >>
> >> The spinlock is defined with the volatile qualifier. This means that
> >> accesses without the qualifier are undefined.
> >
> > The footnote for 6.7.3p6 (footnote 133, N1570) reads:
> > This applies to those objects that behave as if they were defined with
> > qualified types, even if they are
> > never actually defined as objects in the program (such as an object at a
> > memory-mapped input/output
> > address).
> >
> > I don't remember whether footnotes are normative,
>
> They are not.
>
> > but this doesn't apply in our case.
>
> I think it's a clarification intended to *extend* the scope of the
> paragraph to objects not defined using C language elments.
I don't read it that way, and I think it is intended to explain the
intention of this paragraph.
> It's not
> intended to restrict this paragraph to such objects only. The
> footnote is not particularly meaningful anyway because it discusses
> certain vendor extensions whose behavior is not described by the
> standard.
>
> (And on GNU, objects created by mmap or dlopen are not implicitly
> volatile.)
>
> >> > I believe none of the architectures we
> >> > support makes weaker requirements on alignment for volatile-qualified
> >> > than for non-volatile-qualified types, so I can't see any problem in
> >> > practice with the cast.
> >>
> >> We also need separate compilation or some other optimization barrier.
> >
> > Also consider 2.14.2 in
> > https://www.cl.cam.ac.uk/~pes20/cerberus/notes30-full.pdf
>
> Not sure how this applies here. There's no volatile qualifier in
> there.
But it makes a statement about pointers being interchangeable and, at
least as I read it, compatible. So we can transform this into a
question about unions.
> > This states that one can cast between a union and the pointers to
> > individual parts of a union. If the spinlock's underlying type and the
> > volatile-qualified type both have the same size+alignment, then the
> > union will have the same size and alignment too.
> > In our virtual union, we only ever use the non-volatile member (users
> > are not allowed to acccess spinlocks other than through pthread_spin_*
> > functions, which don't use volatile-qualified accesses). But we pass
> > the pointer to the volatile member around as handle to the spinlock.
>
> We also need to cover the case when a spinlock is defined like this:
>
> static pthread_spinlock_t lock;
>
> And I don't see a way to get rid of the volatile there without a
> compiler extension.
>
> We cannot introduce an union here because …
>
> > Maybe its best to just change pthread_spinlock_t from volatile int to
> > int.
>
> … like this, it would change the C++ name mangling of anything related
> to pthread_spinlock_t. It is defined as a typedef, so the mangling
> uses the definition to refer to the type, not the name, according to
> the language rules, where typedef does not create a new type, and
> typedefs with the same definition can be used interchangeably.
I'm not saying that we should change the definition to a union. What
2.14.2 in the document cited above states is that the pointers to the
union and the individual parts are interchangeable. So we can use a
pointer to a part (ie, non-volatile) interchangeably with the pointer to
the union that we use internally.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-26 20:06 ` Torvald Riegel
@ 2017-02-26 20:29 ` Florian Weimer
2017-02-26 20:35 ` Torvald Riegel
0 siblings, 1 reply; 63+ messages in thread
From: Florian Weimer @ 2017-02-26 20:29 UTC (permalink / raw)
To: Torvald Riegel; +Cc: Stefan Liebler, libc-alpha
* Torvald Riegel:
>> … like this, it would change the C++ name mangling of anything related
>> to pthread_spinlock_t. It is defined as a typedef, so the mangling
>> uses the definition to refer to the type, not the name, according to
>> the language rules, where typedef does not create a new type, and
>> typedefs with the same definition can be used interchangeably.
>
> I'm not saying that we should change the definition to a union. What
> 2.14.2 in the document cited above states is that the pointers to the
> union and the individual parts are interchangeable. So we can use a
> pointer to a part (ie, non-volatile) interchangeably with the pointer to
> the union that we use internally.
The relevant quote from that document (C memory object and value
semantics: the space of de facto and ISO standards) is:
| The standard says: 6.7.2.1p16 “The size of a union is
| sufficient to contain the largest of its members. The value of
| at most one of the members can be stored in a union object
| at any time. *A pointer to a union object, suitably converted,*
| *points to each of its members (or if a member is a bit-field,*
| *then to the unit in which it resides), and vice versa.*” (bold
| emphasis added).
So I think this is only valid if you actually start with a union
object. A plain top-level definition of a volatile int is not a union
member, so this rule does not apply (in the “vice versa” part).
I think it would be much simpler to ask for a GCC extension which
would allow us to use non-volatile access on a volatile object in a
well-defined fashion.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-26 20:29 ` Florian Weimer
@ 2017-02-26 20:35 ` Torvald Riegel
2017-02-27 17:57 ` Szabolcs Nagy
0 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-02-26 20:35 UTC (permalink / raw)
To: Florian Weimer; +Cc: Stefan Liebler, libc-alpha
On Sun, 2017-02-26 at 21:29 +0100, Florian Weimer wrote:
> * Torvald Riegel:
>
> >> … like this, it would change the C++ name mangling of anything related
> >> to pthread_spinlock_t. It is defined as a typedef, so the mangling
> >> uses the definition to refer to the type, not the name, according to
> >> the language rules, where typedef does not create a new type, and
> >> typedefs with the same definition can be used interchangeably.
> >
> > I'm not saying that we should change the definition to a union. What
> > 2.14.2 in the document cited above states is that the pointers to the
> > union and the individual parts are interchangeable. So we can use a
> > pointer to a part (ie, non-volatile) interchangeably with the pointer to
> > the union that we use internally.
>
> The relevant quote from that document (C memory object and value
> semantics: the space of de facto and ISO standards) is:
>
> | The standard says: 6.7.2.1p16 “The size of a union is
> | sufficient to contain the largest of its members. The value of
> | at most one of the members can be stored in a union object
> | at any time. *A pointer to a union object, suitably converted,*
> | *points to each of its members (or if a member is a bit-field,*
> | *then to the unit in which it resides), and vice versa.*†(bold
> | emphasis added).
>
> So I think this is only valid if you actually start with a union
> object. A plain top-level definition of a volatile int is not a union
> member, so this rule does not apply (in the “vice versa†part).
Then we'll have to agree to disagree. What do others think about this
question?
> I think it would be much simpler to ask for a GCC extension which
> would allow us to use non-volatile access on a volatile object in a
> well-defined fashion.
I guess such an "extension" could simply be GCC promising that casts
between volatile-qualified T and non-volatile-qualified T are okay if
the object is only accessed using one of the two.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-26 20:35 ` Torvald Riegel
@ 2017-02-27 17:57 ` Szabolcs Nagy
2017-02-28 7:15 ` Torvald Riegel
0 siblings, 1 reply; 63+ messages in thread
From: Szabolcs Nagy @ 2017-02-27 17:57 UTC (permalink / raw)
To: Torvald Riegel, Florian Weimer; +Cc: nd, Stefan Liebler, libc-alpha
On 26/02/17 20:35, Torvald Riegel wrote:
> On Sun, 2017-02-26 at 21:29 +0100, Florian Weimer wrote:
>> * Torvald Riegel:
>>
>>>> … like this, it would change the C++ name mangling of anything related
>>>> to pthread_spinlock_t. It is defined as a typedef, so the mangling
>>>> uses the definition to refer to the type, not the name, according to
>>>> the language rules, where typedef does not create a new type, and
>>>> typedefs with the same definition can be used interchangeably.
>>>
>>> I'm not saying that we should change the definition to a union. What
>>> 2.14.2 in the document cited above states is that the pointers to the
>>> union and the individual parts are interchangeable. So we can use a
>>> pointer to a part (ie, non-volatile) interchangeably with the pointer to
>>> the union that we use internally.
>>
>> The relevant quote from that document (C memory object and value
>> semantics: the space of de facto and ISO standards) is:
>>
>> | The standard says: 6.7.2.1p16 “The size of a union is
>> | sufficient to contain the largest of its members. The value of
>> | at most one of the members can be stored in a union object
>> | at any time. *A pointer to a union object, suitably converted,*
>> | *points to each of its members (or if a member is a bit-field,*
>> | *then to the unit in which it resides), and vice versa.*†(bold
>> | emphasis added).
>>
>> So I think this is only valid if you actually start with a union
>> object. A plain top-level definition of a volatile int is not a union
>> member, so this rule does not apply (in the “vice versa†part).
>
> Then we'll have to agree to disagree. What do others think about this
> question?
i think the standard says that
volatile int x;
*(int*)&x;
is undefined and i think
int r = *p;
can be transformed by the compiler to
int r = *p;
*p = r;
if p has type int* (with a conflicting write the
original code would be undefined, without a
conflicting write the transformed code behaves
the same way on targets where the write is atomic),
but this is not valid if p is volatile int*.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-27 17:57 ` Szabolcs Nagy
@ 2017-02-28 7:15 ` Torvald Riegel
2017-03-14 15:55 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-02-28 7:15 UTC (permalink / raw)
To: Szabolcs Nagy; +Cc: Florian Weimer, nd, Stefan Liebler, libc-alpha
On Mon, 2017-02-27 at 17:57 +0000, Szabolcs Nagy wrote:
> On 26/02/17 20:35, Torvald Riegel wrote:
> > On Sun, 2017-02-26 at 21:29 +0100, Florian Weimer wrote:
> >> * Torvald Riegel:
> >>
> >>>> … like this, it would change the C++ name mangling of anything related
> >>>> to pthread_spinlock_t. It is defined as a typedef, so the mangling
> >>>> uses the definition to refer to the type, not the name, according to
> >>>> the language rules, where typedef does not create a new type, and
> >>>> typedefs with the same definition can be used interchangeably.
> >>>
> >>> I'm not saying that we should change the definition to a union. What
> >>> 2.14.2 in the document cited above states is that the pointers to the
> >>> union and the individual parts are interchangeable. So we can use a
> >>> pointer to a part (ie, non-volatile) interchangeably with the pointer to
> >>> the union that we use internally.
> >>
> >> The relevant quote from that document (C memory object and value
> >> semantics: the space of de facto and ISO standards) is:
> >>
> >> | The standard says: 6.7.2.1p16 “The size of a union is
> >> | sufficient to contain the largest of its members. The value of
> >> | at most one of the members can be stored in a union object
> >> | at any time. *A pointer to a union object, suitably converted,*
> >> | *points to each of its members (or if a member is a bit-field,*
> >> | *then to the unit in which it resides), and vice versa.*†(bold
> >> | emphasis added).
> >>
> >> So I think this is only valid if you actually start with a union
> >> object. A plain top-level definition of a volatile int is not a union
> >> member, so this rule does not apply (in the “vice versa†part).
> >
> > Then we'll have to agree to disagree. What do others think about this
> > question?
>
> i think the standard says that
>
> volatile int x;
> *(int*)&x;
>
> is undefined and i think
>
> int r = *p;
At least on the architectures that already use the __atomic builtins, we
never perform such an access -- everything goes through __atomic*. On
other architectures, we already use plain, non-volatile accesses to
emulate real atomics (eg, see atomic_store_relaxed). ISTM that we
wouldn't be making things worse in the sense that we already make
assumptions about what the compiler would do or would not (e.g., the
compiler does not store to *p again as in your third example).
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 2/2] S390: Use generic spinlock code.
2017-02-18 17:05 ` Torvald Riegel
@ 2017-03-14 15:55 ` Stefan Liebler
2017-03-21 15:43 ` Stefan Liebler
2017-04-06 12:27 ` Torvald Riegel
0 siblings, 2 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-03-14 15:55 UTC (permalink / raw)
To: libc-alpha
[-- Attachment #1: Type: text/plain, Size: 3966 bytes --]
On 02/18/2017 06:05 PM, Torvald Riegel wrote:
> On Wed, 2017-02-15 at 17:26 +0100, Stefan Liebler wrote:
>> On 02/13/2017 09:39 PM, Torvald Riegel wrote:
>>> On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
>>>> This is an updated version of the patch, which adjusts the s390 specific
>>>> atomic-macros in the same way as in include/atomic.h.
>>>> Thus passing a volatile int pointer is fine, too.
>>>
>>> The general direction of this is okay.
>>> Some of my comments for patch 1/2 apply here as well (eg, volatile vs.
>>> atomics).
>>>
>> See answer in patch 1/2.
>>
>>> What I don't like is the choice of 1000 for
>>> SPIN_LOCK_READS_BETWEEN_CMPXCHG. Have you run benchmarks to come up
>>> with this value, or is it a guess? Why isn't it documented how you end
>>> up with this number?
>>> We can keep these with a choice such as this, but then we need to have a
>>> FIXME comment in the code, explaining that this is just an arbitrary
>>> choice.
>>>
>>> I would guess that just spinning forever is sufficient, and that we
>>> don't need to throw in a CAS every now and then; using randomized
>>> exponential back-off might be more important. This is something that we
>>> would be in a better position to answer if you'd provide a
>>> microbenchmark for this choice too.
>>> At the end of 2016, I've posted a draft of a microbenchmark for rwlocks.
>>> Maybe you can use this as a start and run a few experiments?
>> >
>> I've run own benchmarks in the same manner as your mentioned
>> microbenchmark for rwlocks below.
>> You are right, I can't recognize a real difference between
>> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
>> and
>> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG -1
>>
>> As it does not hurt, I prefer to use a CAS every 1000 plain reads.
>> A CAS is not necessary on current CPUs but from architecture
>> perspective, it is more correct if there is such a serialization
>> instruction.
>
> What do you mean by "more correct"? I'm not aware of an architecture
> that would not ensure that stores on one CPU will eventually become
> visible to other CPUs.
>
> Thus, as I wrote in my review of patch 1/2, I think we should just
> remove the occassional CAS (ie, just do the equivalent of the -1
> setting, always).
>
>> There is a difference between
>> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG 0
>> and one of the others.
>
> Right. We do want to spin if the lock is acquired by another thread.
> What we should do in a future patch is to experiment with the back-off
> between loads. tile already has some code for this, which we at least
> need to integrate at some point.
>
>> The same applies to
>> #define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 1
>> It does not hurt if the lock is free, but there is a difference if the
>> lock is already acquired and trylock is called often.
>
> Yes. I've replied to this point in the 1/2 patch thread.
>
>> I've saw your microbenchmark-post and added some notes.
>
> Thanks. I'll get to them later.
>
>> I added a FIXME comment to re-evaluate the choice once we have the
>> appropriate microbenchmarks.
>>
>>> Also, I'm not quite sure whether this number is really
>>> spinlock-specific, and I would like to find a better place for these.
>>> IMO, they should be in some header that contains default tuning
>>> parameters for synchronization code, which is provided by each
>>> architecture that uses the generic spinlock; we'd have no #ifdef for the
>>> tuning parameters, so we'd catch typos in those headers.
>>>
>> See pthread_spin_parameters.h in updated patch 1/2.
>
> I suggest that we'll work towards consensus on patch 1/2 first. I
> believe once that is done, patch 2/2 would likely just remove s390 code.
>
I've attached an updated patch which just removes the s390 code.
> Thanks for continuing the work on this. I know we have some back and
> forth here in terms of overall direction, but I also think we're making
> progress and are continually improving the changes.
>
[-- Attachment #2: 0002-S390-Use-generic-spinlock-code.patch --]
[-- Type: text/x-patch, Size: 6526 bytes --]
From 78888be8fab0f3e988360c77240d8aa08fcc980c Mon Sep 17 00:00:00 2001
From: Stefan Liebler <stli@linux.vnet.ibm.com>
Date: Tue, 14 Mar 2017 14:10:05 +0100
Subject: [PATCH 2/2] S390: Use generic spinlock code.
This patch removes the s390 specific implementation of spinlock code
and is now using the generic one.
ChangeLog:
* sysdeps/s390/nptl/pthread_spin_init.c: Delete File.
* sysdeps/s390/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_trylock.c: Likewise.
* sysdeps/s390/nptl/pthread_spin_unlock.c: Likewise.
---
sysdeps/s390/nptl/pthread_spin_init.c | 19 -------------------
sysdeps/s390/nptl/pthread_spin_lock.c | 32 --------------------------------
sysdeps/s390/nptl/pthread_spin_trylock.c | 32 --------------------------------
sysdeps/s390/nptl/pthread_spin_unlock.c | 32 --------------------------------
4 files changed, 115 deletions(-)
delete mode 100644 sysdeps/s390/nptl/pthread_spin_init.c
delete mode 100644 sysdeps/s390/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/s390/nptl/pthread_spin_trylock.c
delete mode 100644 sysdeps/s390/nptl/pthread_spin_unlock.c
diff --git a/sysdeps/s390/nptl/pthread_spin_init.c b/sysdeps/s390/nptl/pthread_spin_init.c
deleted file mode 100644
index d826871..0000000
--- a/sysdeps/s390/nptl/pthread_spin_init.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Not needed. pthread_spin_init is an alias for pthread_spin_unlock. */
diff --git a/sysdeps/s390/nptl/pthread_spin_lock.c b/sysdeps/s390/nptl/pthread_spin_lock.c
deleted file mode 100644
index 7349940..0000000
--- a/sysdeps/s390/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#include "pthreadP.h"
-
-int
-pthread_spin_lock (pthread_spinlock_t *lock)
-{
- int oldval;
-
- __asm__ __volatile__ ("0: lhi %0,0\n"
- " cs %0,%2,%1\n"
- " jl 0b"
- : "=&d" (oldval), "=Q" (*lock)
- : "d" (1), "m" (*lock) : "cc" );
- return 0;
-}
diff --git a/sysdeps/s390/nptl/pthread_spin_trylock.c b/sysdeps/s390/nptl/pthread_spin_trylock.c
deleted file mode 100644
index 0e848da..0000000
--- a/sysdeps/s390/nptl/pthread_spin_trylock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#include <errno.h>
-#include "pthreadP.h"
-
-int
-pthread_spin_trylock (pthread_spinlock_t *lock)
-{
- int old;
-
- __asm__ __volatile__ ("cs %0,%3,%1"
- : "=d" (old), "=Q" (*lock)
- : "0" (0), "d" (1), "m" (*lock) : "cc" );
-
- return old != 0 ? EBUSY : 0;
-}
diff --git a/sysdeps/s390/nptl/pthread_spin_unlock.c b/sysdeps/s390/nptl/pthread_spin_unlock.c
deleted file mode 100644
index 54e7378..0000000
--- a/sysdeps/s390/nptl/pthread_spin_unlock.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright (C) 2003-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Martin Schwidefsky <schwidefsky@de.ibm.com>, 2003.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-/* Ugly hack to avoid the declaration of pthread_spin_init. */
-#define pthread_spin_init pthread_spin_init_XXX
-#include "pthreadP.h"
-#undef pthread_spin_init
-
-int
-pthread_spin_unlock (pthread_spinlock_t *lock)
-{
- __asm__ __volatile__ (" xc %O0(4,%R0),%0\n"
- " bcr 15,0"
- : "=Q" (*lock) : "m" (*lock) : "cc" );
- return 0;
-}
-strong_alias (pthread_spin_unlock, pthread_spin_init)
--
2.7.4
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-20 13:51 ` Torvald Riegel
@ 2017-03-14 15:55 ` Stefan Liebler
2017-03-21 15:43 ` Stefan Liebler
` (2 more replies)
0 siblings, 3 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-03-14 15:55 UTC (permalink / raw)
To: libc-alpha
[-- Attachment #1: Type: text/plain, Size: 7190 bytes --]
On 02/20/2017 02:51 PM, Torvald Riegel wrote:
> On Mon, 2017-02-20 at 13:15 +0100, Stefan Liebler wrote:
>>>>> A while ago we tried hard to remove all code that would fail silently
>>>>> when a macro had a typo in the name, for example. We still have a few
>>>>> of them left (e.g., in the atomics), but I think this here doesn't
>>>>> warrant an exception.
>>>>>
>>>> Okay. You're right.
>>>>
>>>> In comment of patch 2/2, you've mentioned a header where an architecture
>>>> shall define those parameters.
>>>> Thus I've added the file nptl/pthread_spin_parameters.h.
>>>
>>> I think the stub version should be in sysdeps/ but the wiki is missing
>>> this information (default ENOTSUP location):
>>> https://sourceware.org/glibc/wiki/Style_and_Conventions#Proper_sysdeps_Location
>> In case we need a new header, shall we move it to sysdeps/nptl/ ?
>
> I would guess that this would be the right place for a stub / generic
> variant of such a header, but I'm not quite sure.
>
>>>
>>> I'm still a bit undecided about how to deal with other arch's
>>> pthread_spin_lock.c files that just set SPIN_LOCK_READS_BETWEEN_CMPXCHG
>>> and then include the generic pthread_spin_lock.c. Maybe it's best if we
>>> just remove them in this patch of yours.
>>>
>> I think the archs currently using the generic implementation have just
>> copied the default value to get rid of the warning "machine-dependent
>> file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG". But this is only an
>> assumption.
>> In general removing those "wrapper"-pthread_spin_lock.c files and using
>> information from a header like the proposed pthread_spin_parameters.h or
>> atomic-machine.h is a good approach.
>
> Okay. So let's do that.
>
Done. The wrapper-pthread_spin_lock.c files in sysdeps subfolders are
removed and the option SPIN_LOCK_READS_BETWEEN_CMPXCHG is not available
anymore.
Instead there is only a loop of plain reads until we observe an not
acquired lock.
See comment in nptl/pthread_spin_lock.c.
>>> I agree that the there are architecture-specific properties of atomic
>>> operations that have a significant effect on performance. For s390, you
>>> list the following points:
>>> * atomic exchange (I suppose all atomic read-modify-write ops?) are
>>> implemented through CAS.
>> atomic exchange is implemented by a CAS loop due to lack of an exchange
>> instruction. For exchanging to a "0", s390 can use the load-and-and
>> instruction instead of a CAS loop (See my atomic-machine.h patch; For
>> gcc, we plan to emit such a load-and-and instruction for builtin
>> __atomic_exchange_n in future;). This also saves one register usage
>> compared to the CAS loop.
>> Exchanging to "0" is e.g. used for lll_unlock macro or in
>> malloc_consolidate.
>
> I guess this may then be yet another property atomic-machine.h could
> expose: Whether an atomic fetch-and-and exists and is not implemented
> throough a CAS loop. Something like lll_unlock would then do an
> exchange or fetch-and-and, and if that fails, a CAS loop.
>
>> Starting with z196 zarch CPUs, the following instructions which are used
>> by the appropriate __atomic_fetch_xyz builtins instead of a CAS loop:
>> load-and-add, load-and-and, load-and-exclusive-or, load-and-or.
>> As information:
>> I will update my atomic-machine.h patch to use at least some of the C11
>> atomic builtins or all depending on gcc version.
>
> Thanks.
>
>>> These properties are specific to the architecture, but they are not
>>> specific to the synchronization code (eg, to spinlocks). Thus, I think
>>> such settings should be in the atomics headers (i.e., in
>>> atomic-machine.h).
>>> This should probably be a separate patch. I would propose the following
>>> macros (both are bool):
>>> /* Nonzero iff all atomic read-modify-write operations (e.g., atomic
>>> exchange) are implemented using a CAS loop. */
>>> #define ATOMIC_RMW_USES_CAS 1
>> Is one macro enough to describe all read-modify-write operations in
>> include/atomic.h?
>> Please also see my comment above.
>
> Yes, it may not be enough (e.g., you say that s390 may have fetch_and
> but not an exchange, but other archs may just have an exchange but no
> custom fetch_and).
> So maybe we should add ATOMIC_EXCHANGE_USES_CAS and
> ATOMIC_FETCH_AND_USES_CAS for now, and add further ones on demand?
>
>>> /* Nonzero iff CAS always assumes it will store, and thus has cache
>>> performance effects similar to a store (e.g., it always puts the
>>> respective cacheline into an exclusive state, even if the comparison
>>> against the expected value fails). */
>>> ATOMIC_CAS_ALWAYS_PREPARES_FOR_STORE 1
>>>
>>> I'm not sure whether there are architectures for which the second macro
>>> would not be true. It would be good to investigate this, maybe we don't
>>> need to add this at all.
>>>
>> We plan that in future gcc will emit e.g. a load-and-test instruction in
>> front of the CAS instruction if the old-value is a constant zero.
>
> That can be useful, but what I outlined would be about a more generic
> case. If you are going to solve this for your arch in gcc, you might
> not need to address this in this patch.
>
>>>
>>>
>>> For the spin lock specifically, we have the following possibilities:
>>>
>>> 1) If we assume that trylock will most likely succeed in practice:
>>> * We just do an exchange. The properties above don't matter.
>>>
>>> 2) If we want to bias towards cases where trylock succeeds, but don't
>>> rule out contention:
>>> * If exchange not a CAS loop, and exchange is faster than CAS, do an
>>> exchange.
>>> * If exchange is a CAS loop, use a weak CAS and not an exchange so we
>>> bail out after the first failed attempt to change the state.
>>>
>>> 3) If we expect contention to be likely:
>>> * If CAS always brings the cache line into an exclusive state, then load
>>> first. Then do 2).
>>>
>>> Do we have consensus yet on whether we assume 2 or 3 (I don't think 1
>>> buys us anything over 2)?
>>>
>> Yes. Sounds good.
>
> I read this as stating that you agree that 1) doesn't need to be
> considered. But we still to choose between 2) and 3) :)
>
> I'm not quite sure what to favor because some of the code out there that
> uses trylock just uses it to prevent deadlock (e.g., when trying to
> acquire multiple locks at once), whereas other code uses spin_trylock to
> implement their own back-off and bounded spinning.
> I lean towards assuming that lock acquisitons, including the former use
> case for trylock, are supposed to succeed in the common case. That is,
> I would pick 2), but I have no data to back this up.
>
> Either way, whatever we choose, we should document polish the cases 1-3
> above and the reasoning behind our choice for one of them, and add it as
> a comment to the spinlock code.
>
Okay. I've attached an updated patch. It is now using case 2).
This choice applies to pthread_spin_trylock.c and the first attempt to
acquire the lock in pthread_spin_lock.c.
Therefore I've introduced ATOMIC_EXCHANGE_USES_CAS for all architectures
in atomic-machine.h files. There is a check in include/atomic.h which
ensures that it is defined to either 0 or 1. Can you please review the
setting of 0 or 1?
Bye Stefan
[-- Attachment #2: 0001-Optimize-generic-spinlock-code-and-use-C11-like-atom.patch --]
[-- Type: text/x-patch, Size: 37165 bytes --]
From b8dc58807825423ce5e569018ce9dbc3bd170e67 Mon Sep 17 00:00:00 2001
From: Stefan Liebler <stli@linux.vnet.ibm.com>
Date: Tue, 14 Mar 2017 14:10:05 +0100
Subject: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic
macros.
This patch optimizes the generic spinlock code.
The type pthread_spinlock_t is a typedef to volatile int on all archs.
Passing a volatile pointer to the atomic macros which are not mapped to the
C11 atomic builtins can lead to extra stores and loads to stack if such
a macro creates a temporary variable by using "__typeof (*(mem)) tmp;".
Thus, those macros which are used by spinlock code - atomic_exchange_acquire,
atomic_load_relaxed, atomic_compare_exchange_weak - have to be adjusted.
According to the comment from Szabolcs Nagy, the type of a cast expression is
unqualified (see http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm):
__typeof ((__typeof (*(mem)) *(mem)) tmp;
Thus from spinlock perspective the variable tmp is of type int instead of
type volatile int. This patch adjusts those macros in include/atomic.h.
With this construct GCC >= 5 omits the extra stores and loads.
The atomic macros are replaced by the C11 like atomic macros and thus
the code is aligned to it. The pthread_spin_unlock implementation is now
using release memory order instead of sequentially consistent memory order.
The issue with passed volatile int pointers applies to the C11 like atomic
macros as well as the ones used before.
I've added a glibc_likely hint to the first atomic exchange in
pthread_spin_lock in order to return immediately to the caller if the lock is
free. Without the hint, there is an additional jump if the lock is free.
I've added the atomic_spin_nop macro within the loop of plain reads.
The plain reads are also realized by C11 like atomic_load_relaxed macro.
The new define ATOMIC_EXCHANGE_USES_CAS determines if the first try to acquire
the spinlock in pthread_spin_lock or pthread_spin_trylock is an exchange
or a CAS. This is defined in atomic-machine.h for all architectures.
The define SPIN_LOCK_READS_BETWEEN_CMPXCHG is now removed.
There is no technical reason for throwing in a CAS every now and then,
and so far we have no evidence that it can improve performance.
If that would be the case, we have to adjust other spin-waiting loops
elsewhere, too! Using a CAS loop without plain reads is not a good idea
on many targets and wasn't used by one. Thus there is now no option to
do so.
Architectures are now using the generic spinlock automatically if they
do not provide an own implementation. Thus the pthread_spin_lock.c files
in sysdeps folder are deleted.
ChangeLog:
* NEWS: Mention new spinlock implementation.
* include/atomic.h:
(__atomic_val_bysize): Cast type to omit volatile qualifier.
(atomic_exchange_acq): Likewise.
(atomic_load_relaxed): Likewise.
(ATOMIC_EXCHANGE_USES_CAS): Check definition.
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros.
* nptl/pthread_spin_trylock.c (pthread_spin_trylock):
Likewise.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
* sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/arm/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/hppa/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/m68k/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/microblaze/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/mips/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/nios2/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/aarch64/atomic-machine.h (ATOMIC_EXCHANGE_USES_CAS): Define.
* sysdeps/alpha/atomic-machine.h: Likewise.
* sysdeps/arm/atomic-machine.h: Likewise.
* sysdeps/i386/atomic-machine.h: Likewise.
* sysdeps/ia64/atomic-machine.h: Likewise.
* sysdeps/m68k/coldfire/atomic-machine.h: Likewise.
* sysdeps/m68k/m680x0/m68020/atomic-machine.h: Likewise.
* sysdeps/microblaze/atomic-machine.h: Likewise.
* sysdeps/mips/atomic-machine.h: Likewise.
* sysdeps/powerpc/powerpc32/atomic-machine.h: Likewise.
* sysdeps/powerpc/powerpc64/atomic-machine.h: Likewise.
* sysdeps/s390/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc32/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc32/sparcv9/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc64/atomic-machine.h: Likewise.
* sysdeps/tile/tilegx/atomic-machine.h: Likewise.
* sysdeps/tile/tilepro/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/hppa/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/nios2/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/sh/atomic-machine.h: Likewise.
* sysdeps/x86_64/atomic-machine.h: Likewise.
---
NEWS | 11 ++++
include/atomic.h | 17 ++++--
nptl/pthread_spin_init.c | 3 +-
nptl/pthread_spin_lock.c | 64 +++++++++++++---------
nptl/pthread_spin_trylock.c | 48 +++++++++++++++-
nptl/pthread_spin_unlock.c | 6 +-
sysdeps/aarch64/atomic-machine.h | 1 +
sysdeps/aarch64/nptl/pthread_spin_lock.c | 24 --------
sysdeps/alpha/atomic-machine.h | 1 +
sysdeps/arm/atomic-machine.h | 1 +
sysdeps/arm/nptl/pthread_spin_lock.c | 23 --------
sysdeps/hppa/nptl/pthread_spin_lock.c | 23 --------
sysdeps/i386/atomic-machine.h | 1 +
sysdeps/ia64/atomic-machine.h | 1 +
sysdeps/m68k/coldfire/atomic-machine.h | 1 +
sysdeps/m68k/m680x0/m68020/atomic-machine.h | 1 +
sysdeps/m68k/nptl/pthread_spin_lock.c | 24 --------
sysdeps/microblaze/atomic-machine.h | 1 +
sysdeps/microblaze/nptl/pthread_spin_lock.c | 24 --------
sysdeps/mips/atomic-machine.h | 2 +
sysdeps/mips/nptl/pthread_spin_lock.c | 23 --------
sysdeps/nios2/nptl/pthread_spin_lock.c | 24 --------
sysdeps/powerpc/powerpc32/atomic-machine.h | 1 +
sysdeps/powerpc/powerpc64/atomic-machine.h | 1 +
sysdeps/s390/atomic-machine.h | 2 +
sysdeps/sparc/sparc32/atomic-machine.h | 1 +
sysdeps/sparc/sparc32/sparcv9/atomic-machine.h | 1 +
sysdeps/sparc/sparc64/atomic-machine.h | 1 +
sysdeps/tile/tilegx/atomic-machine.h | 1 +
sysdeps/tile/tilepro/atomic-machine.h | 1 +
sysdeps/unix/sysv/linux/hppa/atomic-machine.h | 1 +
.../unix/sysv/linux/m68k/coldfire/atomic-machine.h | 1 +
sysdeps/unix/sysv/linux/nios2/atomic-machine.h | 1 +
sysdeps/unix/sysv/linux/sh/atomic-machine.h | 1 +
sysdeps/x86_64/atomic-machine.h | 1 +
35 files changed, 139 insertions(+), 199 deletions(-)
delete mode 100644 sysdeps/aarch64/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/arm/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/hppa/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/m68k/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/microblaze/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/mips/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/nios2/nptl/pthread_spin_lock.c
diff --git a/NEWS b/NEWS
index 9efe1e5..19ac934 100644
--- a/NEWS
+++ b/NEWS
@@ -17,6 +17,17 @@ Version 2.26
by default. Applications needing features missing from TIRPC should
consider the rpcsvc-proto project developed by Thorsten Kukuk (SUSE).
+* The synchronization that pthread_spin_unlock performs has been changed
+ to now be equivalent to a C11 atomic store with release memory order to
+ the spin lock's memory location. This ensures correct synchronization
+ for the spin lock's operations and critical sections protected by a spin
+ lock. Previously, several (but not all) architectures used stronger
+ synchronization (e.g., containing what is often called a full barrier).
+ This change can improve performance, but may affect odd fringe uses of
+ spin locks that depend on the previous behavior (e.g., using spin locks
+ as atomic variables to try to implement Dekker's mutual exclusion
+ algorithm).
+
Security related changes:
[Add security related changes here]
diff --git a/include/atomic.h b/include/atomic.h
index 7f32640..4d1b0df 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -54,7 +54,7 @@
and following args. */
#define __atomic_val_bysize(pre, post, mem, ...) \
({ \
- __typeof (*mem) __atg1_result; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
if (sizeof (*mem) == 1) \
__atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
else if (sizeof (*mem) == 2) \
@@ -162,9 +162,9 @@
/* Store NEWVALUE in *MEM and return the old value. */
#ifndef atomic_exchange_acq
# define atomic_exchange_acq(mem, newvalue) \
- ({ __typeof (*(mem)) __atg5_oldval; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
__typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
\
do \
__atg5_oldval = *__atg5_memp; \
@@ -668,7 +668,7 @@ void __atomic_link_error (void);
# ifndef atomic_load_relaxed
# define atomic_load_relaxed(mem) \
- ({ __typeof (*(mem)) __atg100_val; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
__asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
__atg100_val; })
# endif
@@ -818,4 +818,13 @@ void __atomic_link_error (void);
# define atomic_spin_nop() do { /* nothing */ } while (0)
#endif
+/* This is equal to 1 if atomic_exchange is implemented by a CAS loop
+ and 0 if atomic_exchange is implemented with an instruction faster than
+ CAS. */
+#if ! defined ATOMIC_EXCHANGE_USES_CAS || ! (ATOMIC_EXCHANGE_USES_CAS == 0 \
+ || ATOMIC_EXCHANGE_USES_CAS == 1)
+# error ATOMIC_EXCHANGE_USES_CAS has to be defined to 0 or 1
+#endif
+
#endif /* atomic.h */
+
diff --git a/nptl/pthread_spin_init.c b/nptl/pthread_spin_init.c
index 01dec5e..fe30913 100644
--- a/nptl/pthread_spin_init.c
+++ b/nptl/pthread_spin_init.c
@@ -22,6 +22,7 @@
int
pthread_spin_init (pthread_spinlock_t *lock, int pshared)
{
- *lock = 0;
+ /* Relaxed MO is fine because this is an initializing store. */
+ atomic_store_relaxed (lock, 0);
return 0;
}
diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
index 4d03b78..c2fb8e7 100644
--- a/nptl/pthread_spin_lock.c
+++ b/nptl/pthread_spin_lock.c
@@ -19,27 +19,38 @@
#include <atomic.h>
#include "pthreadP.h"
-/* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
- to the number of plain reads that it's optimal to spin on between uses
- of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
- then use -1. If no plain reads here would ever be optimal, use 0. */
-#ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
-# warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
-# define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-#endif
-
int
pthread_spin_lock (pthread_spinlock_t *lock)
{
+ int val = 0;
+
/* atomic_exchange usually takes less instructions than
atomic_compare_and_exchange. On the other hand,
atomic_compare_and_exchange potentially generates less bus traffic
when the lock is locked.
- We assume that the first try mostly will be successful, and we use
- atomic_exchange. For the subsequent tries we use
- atomic_compare_and_exchange. */
- if (atomic_exchange_acq (lock, 1) == 0)
+ We assume that the first try mostly will be successful, thus we use
+ atomic_exchange if it is not implemented by a CAS loop. Otherwise
+ we use a weak CAS and not an exchange so we bail out after the first
+ failed attempt to change the state.
+ For the subsequent tries we use atomic_compare_and_exchange after we
+ observe a not acquired lock.
+ See also comment in pthread_spin_trylock.
+ We use acquire MO to synchronize-with the release MO store in
+ pthread_spin_unlock, and thus ensure that prior critical sections
+ happen-before this critical section. */
+#if ATOMIC_EXCHANGE_USES_CAS == 0
+ /* Try to acquire the lock with an exchange instruction as this architecture
+ has such an instruction and we assume it is faster than a CAS.
+ The acquisition succeeds if the lock had not been acquired before. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
+ return 0;
+#elif ATOMIC_EXCHANGE_USES_CAS == 1
+ /* Try to acquire the lock with a CAS instruction as this architecture
+ has no exchange instruction. The acquisition succeeds if the lock is not
+ acquired. */
+ if (__glibc_likely (atomic_compare_exchange_weak_acquire (lock, &val, 1)))
return 0;
+#endif
do
{
@@ -47,23 +58,24 @@ pthread_spin_lock (pthread_spinlock_t *lock)
to cmpxchg is not a good idea on many targets as that will force
expensive memory synchronizations among processors and penalize other
running threads.
- On the other hand, we do want to update memory state on the local core
- once in a while to avoid spinning indefinitely until some event that
- will happen to update local memory as a side-effect. */
- if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
+ There is no technical reason for throwing in a CAS every now and then,
+ and so far we have no evidence that it can improve performance.
+ If that would be the case, we have to adjust other spin-waiting loops
+ elsewhere, too!
+ Thus we use relaxed MO reads until we observe the lock to not be
+ acquired anymore. */
+ do
{
- int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
+ atomic_spin_nop ();
- while (*lock != 0 && wait > 0)
- --wait;
- }
- else
- {
- while (*lock != 0)
- ;
+ val = atomic_load_relaxed (lock);
}
+ while (val != 0);
+
+ /* We need acquire memory order here for the same reason as mentioned
+ for the first try to lock the spinlock. */
}
- while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
+ while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
return 0;
}
diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
index 593bba3..a3e9e44 100644
--- a/nptl/pthread_spin_trylock.c
+++ b/nptl/pthread_spin_trylock.c
@@ -23,5 +23,51 @@
int
pthread_spin_trylock (pthread_spinlock_t *lock)
{
- return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
+ /* For the spin try lock, we have the following possibilities:
+
+ 1) If we assume that trylock will most likely succeed in practice:
+ * We just do an exchange.
+
+ 2) If we want to bias towards cases where trylock succeeds, but don't
+ rule out contention:
+ * If exchange is not implemented by a CAS loop, and exchange is faster
+ than CAS, do an exchange.
+ * If exchange is implemented by a CAS loop, use a weak CAS and not an
+ exchange so we bail out after the first failed attempt to change the state.
+
+ 3) If we expect contention to be likely:
+ * If CAS always brings the cache line into an exclusive state even if the
+ spinlock is already acquired, then load the value first with
+ atomic_load_relaxed and test if lock is not acquired. Then do 2).
+
+ We prefer case 2) as some of the code out there that uses trylock just
+ uses it to prevent deadlock (e.g., when trying to acquire multiple locks
+ at once), whereas other code uses spin_trylock to implement their own
+ back-off and bounded spinning.
+ Our assumption is that lock acquisitions, including the former use case
+ for trylock, are supposed to succeed in the common case.
+ Thus we choose case 2) as it uses the faster exchange instruction if the
+ architecture has such an instruction. For those architectures case 2)
+ is the same as 1). On the other architectures we are now using one CAS
+ with zero as expected value instead of a CAS loop to exchange to one. */
+
+ /* We use acquire MO to synchronize-with the release MO store in
+ pthread_spin_unlock, and thus ensure that prior critical sections
+ happen-before this critical section. */
+#if ATOMIC_EXCHANGE_USES_CAS == 0
+ /* Try to acquire the lock with an exchange instruction as this architecture
+ has such an instruction and we assume it is faster than a CAS.
+ The acquisition succeeds if the lock had not been acquired before. */
+ if (atomic_exchange_acquire (lock, 1) == 0)
+ return 0;
+#elif ATOMIC_EXCHANGE_USES_CAS == 1
+ /* Try to acquire the lock with a CAS instruction as this architecture
+ has no exchange instruction. The acquisition succeeds if the lock is not
+ acquired. */
+ int val = 0;
+ if (atomic_compare_exchange_weak_acquire (lock, &val, 1))
+ return 0;
+#endif
+
+ return EBUSY;
}
diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
index 5fd73e5..f83b696 100644
--- a/nptl/pthread_spin_unlock.c
+++ b/nptl/pthread_spin_unlock.c
@@ -23,7 +23,9 @@
int
pthread_spin_unlock (pthread_spinlock_t *lock)
{
- atomic_full_barrier ();
- *lock = 0;
+ /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
+ or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
+ pthread_spin_trylock. */
+ atomic_store_release (lock, 0);
return 0;
}
diff --git a/sysdeps/aarch64/atomic-machine.h b/sysdeps/aarch64/atomic-machine.h
index a5d2213..eb59a5b 100644
--- a/sysdeps/aarch64/atomic-machine.h
+++ b/sysdeps/aarch64/atomic-machine.h
@@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 1
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange succesful. */
diff --git a/sysdeps/aarch64/nptl/pthread_spin_lock.c b/sysdeps/aarch64/nptl/pthread_spin_lock.c
deleted file mode 100644
index fcfcb40..0000000
--- a/sysdeps/aarch64/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
-
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public License as
- published by the Free Software Foundation; either version 2.1 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/alpha/atomic-machine.h b/sysdeps/alpha/atomic-machine.h
index 06e93f2..e55ecdd 100644
--- a/sysdeps/alpha/atomic-machine.h
+++ b/sysdeps/alpha/atomic-machine.h
@@ -44,6 +44,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
#ifdef UP
diff --git a/sysdeps/arm/atomic-machine.h b/sysdeps/arm/atomic-machine.h
index eeac7f0..2556438 100644
--- a/sysdeps/arm/atomic-machine.h
+++ b/sysdeps/arm/atomic-machine.h
@@ -35,6 +35,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
void __arm_link_error (void);
diff --git a/sysdeps/arm/nptl/pthread_spin_lock.c b/sysdeps/arm/nptl/pthread_spin_lock.c
deleted file mode 100644
index 037b3b8..0000000
--- a/sysdeps/arm/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/hppa/nptl/pthread_spin_lock.c b/sysdeps/hppa/nptl/pthread_spin_lock.c
deleted file mode 100644
index 14f36a6..0000000
--- a/sysdeps/hppa/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2005-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/i386/atomic-machine.h b/sysdeps/i386/atomic-machine.h
index 77759f7..0e24200 100644
--- a/sysdeps/i386/atomic-machine.h
+++ b/sysdeps/i386/atomic-machine.h
@@ -56,6 +56,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
diff --git a/sysdeps/ia64/atomic-machine.h b/sysdeps/ia64/atomic-machine.h
index ecf9750..971084e 100644
--- a/sysdeps/ia64/atomic-machine.h
+++ b/sysdeps/ia64/atomic-machine.h
@@ -45,6 +45,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
diff --git a/sysdeps/m68k/coldfire/atomic-machine.h b/sysdeps/m68k/coldfire/atomic-machine.h
index 9aeb993..72b037e 100644
--- a/sysdeps/m68k/coldfire/atomic-machine.h
+++ b/sysdeps/m68k/coldfire/atomic-machine.h
@@ -52,6 +52,7 @@ typedef uintmax_t uatomic_max_t;
/* If we have just non-atomic operations, we can as well make them wide. */
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* The only basic operation needed is compare and exchange. */
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
diff --git a/sysdeps/m68k/m680x0/m68020/atomic-machine.h b/sysdeps/m68k/m680x0/m68020/atomic-machine.h
index 00dc22d..a319471 100644
--- a/sysdeps/m68k/m680x0/m68020/atomic-machine.h
+++ b/sysdeps/m68k/m680x0/m68020/atomic-machine.h
@@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
({ __typeof (*(mem)) __ret; \
diff --git a/sysdeps/m68k/nptl/pthread_spin_lock.c b/sysdeps/m68k/nptl/pthread_spin_lock.c
deleted file mode 100644
index 62795f4..0000000
--- a/sysdeps/m68k/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2010-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Maxim Kuvyrkov <maxim@codesourcery.com>, 2010.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/microblaze/atomic-machine.h b/sysdeps/microblaze/atomic-machine.h
index dc5309c..3a9b58f 100644
--- a/sysdeps/microblaze/atomic-machine.h
+++ b/sysdeps/microblaze/atomic-machine.h
@@ -37,6 +37,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* Microblaze does not have byte and halfword forms of load and reserve and
diff --git a/sysdeps/microblaze/nptl/pthread_spin_lock.c b/sysdeps/microblaze/nptl/pthread_spin_lock.c
deleted file mode 100644
index fcfcb40..0000000
--- a/sysdeps/microblaze/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
-
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public License as
- published by the Free Software Foundation; either version 2.1 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h
index 54c182b..3d9da0c 100644
--- a/sysdeps/mips/atomic-machine.h
+++ b/sysdeps/mips/atomic-machine.h
@@ -50,6 +50,8 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#endif
+#define ATOMIC_EXCHANGE_USES_CAS 0
+
/* See the comments in <sys/asm.h> about the use of the sync instruction. */
#ifndef MIPS_SYNC
# define MIPS_SYNC sync
diff --git a/sysdeps/mips/nptl/pthread_spin_lock.c b/sysdeps/mips/nptl/pthread_spin_lock.c
deleted file mode 100644
index 19d87a5..0000000
--- a/sysdeps/mips/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2012-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/nios2/nptl/pthread_spin_lock.c b/sysdeps/nios2/nptl/pthread_spin_lock.c
deleted file mode 100644
index b203469..0000000
--- a/sysdeps/nios2/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* pthread spin-lock implementation for Nios II.
- Copyright (C) 2005-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/powerpc32/atomic-machine.h
index 20d5e85..8f4407b 100644
--- a/sysdeps/powerpc/powerpc32/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc32/atomic-machine.h
@@ -35,6 +35,7 @@
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/*
* The 32-bit exchange_bool is different on powerpc64 because the subf
diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h
index 40c308e..9c4a55b 100644
--- a/sysdeps/powerpc/powerpc64/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc64/atomic-machine.h
@@ -35,6 +35,7 @@
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* The 32-bit exchange_bool is different on powerpc64 because the subf
does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
diff --git a/sysdeps/s390/atomic-machine.h b/sysdeps/s390/atomic-machine.h
index 690d2e3..adaca40 100644
--- a/sysdeps/s390/atomic-machine.h
+++ b/sysdeps/s390/atomic-machine.h
@@ -67,6 +67,8 @@ typedef uintmax_t uatomic_max_t;
# define __HAVE_64B_ATOMICS 0
#endif
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* Implement some of the non-C11 atomic macros from include/atomic.h
with help of the C11 atomic builtins. The other non-C11 atomic macros
are using the macros defined here. */
diff --git a/sysdeps/sparc/sparc32/atomic-machine.h b/sysdeps/sparc/sparc32/atomic-machine.h
index acd029e..9b2eb47 100644
--- a/sysdeps/sparc/sparc32/atomic-machine.h
+++ b/sysdeps/sparc/sparc32/atomic-machine.h
@@ -49,6 +49,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* We have no compare and swap, just test and set.
diff --git a/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h b/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
index 7f7895e..c3486b4 100644
--- a/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
+++ b/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
@@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
diff --git a/sysdeps/sparc/sparc64/atomic-machine.h b/sysdeps/sparc/sparc64/atomic-machine.h
index 44a43ff..21ef009 100644
--- a/sysdeps/sparc/sparc64/atomic-machine.h
+++ b/sysdeps/sparc/sparc64/atomic-machine.h
@@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
diff --git a/sysdeps/tile/tilegx/atomic-machine.h b/sysdeps/tile/tilegx/atomic-machine.h
index 6345251..e77f670 100644
--- a/sysdeps/tile/tilegx/atomic-machine.h
+++ b/sysdeps/tile/tilegx/atomic-machine.h
@@ -31,6 +31,7 @@
#endif
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* Pick appropriate 8- or 4-byte instruction. */
#define __atomic_update(mem, v, op) \
diff --git a/sysdeps/tile/tilepro/atomic-machine.h b/sysdeps/tile/tilepro/atomic-machine.h
index 33a8b85..45e36de 100644
--- a/sysdeps/tile/tilepro/atomic-machine.h
+++ b/sysdeps/tile/tilepro/atomic-machine.h
@@ -23,6 +23,7 @@
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* 32-bit integer compare-and-exchange. */
static __inline __attribute__ ((always_inline))
diff --git a/sysdeps/unix/sysv/linux/hppa/atomic-machine.h b/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
index 2cd2235..9adcab7 100644
--- a/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
@@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* prev = *addr;
if (prev == old)
diff --git a/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h b/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
index 6755a05..c1b6950 100644
--- a/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
@@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* The only basic operation needed is compare and exchange. */
/* For ColdFire we'll have to trap into the kernel mode anyway,
diff --git a/sysdeps/unix/sysv/linux/nios2/atomic-machine.h b/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
index 6111ccf..d98fa66 100644
--- a/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
@@ -33,6 +33,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
diff --git a/sysdeps/unix/sysv/linux/sh/atomic-machine.h b/sysdeps/unix/sysv/linux/sh/atomic-machine.h
index 3c58b70..428b71e 100644
--- a/sysdeps/unix/sysv/linux/sh/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/sh/atomic-machine.h
@@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* SH kernel has implemented a gUSA ("g" User Space Atomicity) support
for the user space atomicity. The atomicity macros use this scheme.
diff --git a/sysdeps/x86_64/atomic-machine.h b/sysdeps/x86_64/atomic-machine.h
index 2e8a9aa..c454734 100644
--- a/sysdeps/x86_64/atomic-machine.h
+++ b/sysdeps/x86_64/atomic-machine.h
@@ -59,6 +59,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 1
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
__sync_val_compare_and_swap (mem, oldval, newval)
--
2.7.4
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-02-28 7:15 ` Torvald Riegel
@ 2017-03-14 15:55 ` Stefan Liebler
0 siblings, 0 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-03-14 15:55 UTC (permalink / raw)
To: libc-alpha
On 02/28/2017 08:15 AM, Torvald Riegel wrote:
> On Mon, 2017-02-27 at 17:57 +0000, Szabolcs Nagy wrote:
>> On 26/02/17 20:35, Torvald Riegel wrote:
>>> On Sun, 2017-02-26 at 21:29 +0100, Florian Weimer wrote:
>>>> * Torvald Riegel:
>>>>
>>>>>> … like this, it would change the C++ name mangling of anything related
>>>>>> to pthread_spinlock_t. It is defined as a typedef, so the mangling
>>>>>> uses the definition to refer to the type, not the name, according to
>>>>>> the language rules, where typedef does not create a new type, and
>>>>>> typedefs with the same definition can be used interchangeably.
>>>>>
>>>>> I'm not saying that we should change the definition to a union. What
>>>>> 2.14.2 in the document cited above states is that the pointers to the
>>>>> union and the individual parts are interchangeable. So we can use a
>>>>> pointer to a part (ie, non-volatile) interchangeably with the pointer to
>>>>> the union that we use internally.
>>>>
>>>> The relevant quote from that document (C memory object and value
>>>> semantics: the space of de facto and ISO standards) is:
>>>>
>>>> | The standard says: 6.7.2.1p16 “The size of a union is
>>>> | sufficient to contain the largest of its members. The value of
>>>> | at most one of the members can be stored in a union object
>>>> | at any time. *A pointer to a union object, suitably converted,*
>>>> | *points to each of its members (or if a member is a bit-field,*
>>>> | *then to the unit in which it resides), and vice versa.*†(bold
>>>> | emphasis added).
>>>>
>>>> So I think this is only valid if you actually start with a union
>>>> object. A plain top-level definition of a volatile int is not a union
>>>> member, so this rule does not apply (in the “vice versa†part).
>>>
>>> Then we'll have to agree to disagree. What do others think about this
>>> question?
>>
>> i think the standard says that
>>
>> volatile int x;
>> *(int*)&x;
>>
>> is undefined and i think
>>
>> int r = *p;
>
> At least on the architectures that already use the __atomic builtins, we
> never perform such an access -- everything goes through __atomic*. On
> other architectures, we already use plain, non-volatile accesses to
> emulate real atomics (eg, see atomic_store_relaxed). ISTM that we
> wouldn't be making things worse in the sense that we already make
> assumptions about what the compiler would do or would not (e.g., the
> compiler does not store to *p again as in your third example).
>
Yes, architectures which use the C11 atomics passes the volatile int *
to the __atomic* builtins.
For architectures not using C11 atomics:
From the spinlock perspective, the latest patch does not access a
casted pointer which discards the volatile qualifier.
Instead in atomic_exchange_acq there is a
read from a volatile int * into a local int variable.
The volatile int * is passed to
atomic_compare_and_exchange_bool_acq macro.
The passed oldval / newval variables have type int instead
of volatile int.
atomic_load_relaxed is now using a local variable of type int instead of
volatile int. Reading from the volatile int * is done by gcc via inline
assembly. Afterwards the local int variable is returned to the user of
this macro.
__atomic_val_bysize is now using a local variable of type int instead
of volatile int. The return value of pre##_<sizeof(*mem)>_##post is
stored in the local variable and then returned to the user of this macro.
If this is okay, I prefer to use the changes from the latest patch.
Then this will fix - if compiled with GCC >= 5 - the usage of
the atomic macros in include/atomic.h with volatile int *
for architectures which do not define USE_ATOMIC_COMPILER_BUILTINS
to one.
If this is not okay, I would skip those changes in include/atomic.h
for this patch.
After we have a solution, we should work on a separate patch.
Even if gcc provides an extension as mentioned by Florian, I think it
will only be available with new GCCs. What about the current GCCs?
Bye
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 2/2] S390: Use generic spinlock code.
2017-03-14 15:55 ` Stefan Liebler
@ 2017-03-21 15:43 ` Stefan Liebler
2017-04-06 12:27 ` Torvald Riegel
1 sibling, 0 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-03-21 15:43 UTC (permalink / raw)
To: libc-alpha
On 03/14/2017 04:55 PM, Stefan Liebler wrote:
> On 02/18/2017 06:05 PM, Torvald Riegel wrote:
>> On Wed, 2017-02-15 at 17:26 +0100, Stefan Liebler wrote:
>>> On 02/13/2017 09:39 PM, Torvald Riegel wrote:
>>>> On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
>>>>> This is an updated version of the patch, which adjusts the s390
>>>>> specific
>>>>> atomic-macros in the same way as in include/atomic.h.
>>>>> Thus passing a volatile int pointer is fine, too.
>>>>
>>>> The general direction of this is okay.
>>>> Some of my comments for patch 1/2 apply here as well (eg, volatile vs.
>>>> atomics).
>>>>
>>> See answer in patch 1/2.
>>>
>>>> What I don't like is the choice of 1000 for
>>>> SPIN_LOCK_READS_BETWEEN_CMPXCHG. Have you run benchmarks to come up
>>>> with this value, or is it a guess? Why isn't it documented how you end
>>>> up with this number?
>>>> We can keep these with a choice such as this, but then we need to
>>>> have a
>>>> FIXME comment in the code, explaining that this is just an arbitrary
>>>> choice.
>>>>
>>>> I would guess that just spinning forever is sufficient, and that we
>>>> don't need to throw in a CAS every now and then; using randomized
>>>> exponential back-off might be more important. This is something
>>>> that we
>>>> would be in a better position to answer if you'd provide a
>>>> microbenchmark for this choice too.
>>>> At the end of 2016, I've posted a draft of a microbenchmark for
>>>> rwlocks.
>>>> Maybe you can use this as a start and run a few experiments?
>>> >
>>> I've run own benchmarks in the same manner as your mentioned
>>> microbenchmark for rwlocks below.
>>> You are right, I can't recognize a real difference between
>>> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
>>> and
>>> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG -1
>>>
>>> As it does not hurt, I prefer to use a CAS every 1000 plain reads.
>>> A CAS is not necessary on current CPUs but from architecture
>>> perspective, it is more correct if there is such a serialization
>>> instruction.
>>
>> What do you mean by "more correct"? I'm not aware of an architecture
>> that would not ensure that stores on one CPU will eventually become
>> visible to other CPUs.
>>
>> Thus, as I wrote in my review of patch 1/2, I think we should just
>> remove the occassional CAS (ie, just do the equivalent of the -1
>> setting, always).
>>
>>> There is a difference between
>>> #define SPIN_LOCK_READS_BETWEEN_CMPXCHG 0
>>> and one of the others.
>>
>> Right. We do want to spin if the lock is acquired by another thread.
>> What we should do in a future patch is to experiment with the back-off
>> between loads. tile already has some code for this, which we at least
>> need to integrate at some point.
>>
>>> The same applies to
>>> #define SPIN_TRYLOCK_LOAD_AND_TEST_BEFORE_XCHG 1
>>> It does not hurt if the lock is free, but there is a difference if the
>>> lock is already acquired and trylock is called often.
>>
>> Yes. I've replied to this point in the 1/2 patch thread.
>>
>>> I've saw your microbenchmark-post and added some notes.
>>
>> Thanks. I'll get to them later.
>>
>>> I added a FIXME comment to re-evaluate the choice once we have the
>>> appropriate microbenchmarks.
>>>
>>>> Also, I'm not quite sure whether this number is really
>>>> spinlock-specific, and I would like to find a better place for these.
>>>> IMO, they should be in some header that contains default tuning
>>>> parameters for synchronization code, which is provided by each
>>>> architecture that uses the generic spinlock; we'd have no #ifdef for
>>>> the
>>>> tuning parameters, so we'd catch typos in those headers.
>>>>
>>> See pthread_spin_parameters.h in updated patch 1/2.
>>
>> I suggest that we'll work towards consensus on patch 1/2 first. I
>> believe once that is done, patch 2/2 would likely just remove s390 code.
>>
> I've attached an updated patch which just removes the s390 code.
>
>
PING
>> Thanks for continuing the work on this. I know we have some back and
>> forth here in terms of overall direction, but I also think we're making
>> progress and are continually improving the changes.
>>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-14 15:55 ` Stefan Liebler
@ 2017-03-21 15:43 ` Stefan Liebler
2017-03-22 12:56 ` Szabolcs Nagy
2017-03-27 13:08 ` Stefan Liebler
2017-03-29 14:16 ` Stefan Liebler
2017-04-06 14:00 ` Torvald Riegel
2 siblings, 2 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-03-21 15:43 UTC (permalink / raw)
To: libc-alpha
On 03/14/2017 04:55 PM, Stefan Liebler wrote:
> On 02/20/2017 02:51 PM, Torvald Riegel wrote:
>> On Mon, 2017-02-20 at 13:15 +0100, Stefan Liebler wrote:
>>>>>> A while ago we tried hard to remove all code that would fail silently
>>>>>> when a macro had a typo in the name, for example. We still have a
>>>>>> few
>>>>>> of them left (e.g., in the atomics), but I think this here doesn't
>>>>>> warrant an exception.
>>>>>>
>>>>> Okay. You're right.
>>>>>
>>>>> In comment of patch 2/2, you've mentioned a header where an
>>>>> architecture
>>>>> shall define those parameters.
>>>>> Thus I've added the file nptl/pthread_spin_parameters.h.
>>>>
>>>> I think the stub version should be in sysdeps/ but the wiki is missing
>>>> this information (default ENOTSUP location):
>>>> https://sourceware.org/glibc/wiki/Style_and_Conventions#Proper_sysdeps_Location
>>>>
>>> In case we need a new header, shall we move it to sysdeps/nptl/ ?
>>
>> I would guess that this would be the right place for a stub / generic
>> variant of such a header, but I'm not quite sure.
>>
>>>>
>>>> I'm still a bit undecided about how to deal with other arch's
>>>> pthread_spin_lock.c files that just set SPIN_LOCK_READS_BETWEEN_CMPXCHG
>>>> and then include the generic pthread_spin_lock.c. Maybe it's best
>>>> if we
>>>> just remove them in this patch of yours.
>>>>
>>> I think the archs currently using the generic implementation have just
>>> copied the default value to get rid of the warning "machine-dependent
>>> file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG". But this is only an
>>> assumption.
>>> In general removing those "wrapper"-pthread_spin_lock.c files and using
>>> information from a header like the proposed pthread_spin_parameters.h or
>>> atomic-machine.h is a good approach.
>>
>> Okay. So let's do that.
>>
> Done. The wrapper-pthread_spin_lock.c files in sysdeps subfolders are
> removed and the option SPIN_LOCK_READS_BETWEEN_CMPXCHG is not available
> anymore.
> Instead there is only a loop of plain reads until we observe an not
> acquired lock.
> See comment in nptl/pthread_spin_lock.c.
>
>>>> I agree that the there are architecture-specific properties of atomic
>>>> operations that have a significant effect on performance. For s390,
>>>> you
>>>> list the following points:
>>>> * atomic exchange (I suppose all atomic read-modify-write ops?) are
>>>> implemented through CAS.
>>> atomic exchange is implemented by a CAS loop due to lack of an exchange
>>> instruction. For exchanging to a "0", s390 can use the load-and-and
>>> instruction instead of a CAS loop (See my atomic-machine.h patch; For
>>> gcc, we plan to emit such a load-and-and instruction for builtin
>>> __atomic_exchange_n in future;). This also saves one register usage
>>> compared to the CAS loop.
>>> Exchanging to "0" is e.g. used for lll_unlock macro or in
>>> malloc_consolidate.
>>
>> I guess this may then be yet another property atomic-machine.h could
>> expose: Whether an atomic fetch-and-and exists and is not implemented
>> throough a CAS loop. Something like lll_unlock would then do an
>> exchange or fetch-and-and, and if that fails, a CAS loop.
>>
>>> Starting with z196 zarch CPUs, the following instructions which are used
>>> by the appropriate __atomic_fetch_xyz builtins instead of a CAS loop:
>>> load-and-add, load-and-and, load-and-exclusive-or, load-and-or.
>>> As information:
>>> I will update my atomic-machine.h patch to use at least some of the C11
>>> atomic builtins or all depending on gcc version.
>>
>> Thanks.
>>
>>>> These properties are specific to the architecture, but they are not
>>>> specific to the synchronization code (eg, to spinlocks). Thus, I think
>>>> such settings should be in the atomics headers (i.e., in
>>>> atomic-machine.h).
>>>> This should probably be a separate patch. I would propose the
>>>> following
>>>> macros (both are bool):
>>>> /* Nonzero iff all atomic read-modify-write operations (e.g., atomic
>>>> exchange) are implemented using a CAS loop. */
>>>> #define ATOMIC_RMW_USES_CAS 1
>>> Is one macro enough to describe all read-modify-write operations in
>>> include/atomic.h?
>>> Please also see my comment above.
>>
>> Yes, it may not be enough (e.g., you say that s390 may have fetch_and
>> but not an exchange, but other archs may just have an exchange but no
>> custom fetch_and).
>> So maybe we should add ATOMIC_EXCHANGE_USES_CAS and
>> ATOMIC_FETCH_AND_USES_CAS for now, and add further ones on demand?
>>
>>>> /* Nonzero iff CAS always assumes it will store, and thus has cache
>>>> performance effects similar to a store (e.g., it always puts the
>>>> respective cacheline into an exclusive state, even if the comparison
>>>> against the expected value fails). */
>>>> ATOMIC_CAS_ALWAYS_PREPARES_FOR_STORE 1
>>>>
>>>> I'm not sure whether there are architectures for which the second macro
>>>> would not be true. It would be good to investigate this, maybe we
>>>> don't
>>>> need to add this at all.
>>>>
>>> We plan that in future gcc will emit e.g. a load-and-test instruction in
>>> front of the CAS instruction if the old-value is a constant zero.
>>
>> That can be useful, but what I outlined would be about a more generic
>> case. If you are going to solve this for your arch in gcc, you might
>> not need to address this in this patch.
>>
>>>>
>>>>
>>>> For the spin lock specifically, we have the following possibilities:
>>>>
>>>> 1) If we assume that trylock will most likely succeed in practice:
>>>> * We just do an exchange. The properties above don't matter.
>>>>
>>>> 2) If we want to bias towards cases where trylock succeeds, but don't
>>>> rule out contention:
>>>> * If exchange not a CAS loop, and exchange is faster than CAS, do an
>>>> exchange.
>>>> * If exchange is a CAS loop, use a weak CAS and not an exchange so we
>>>> bail out after the first failed attempt to change the state.
>>>>
>>>> 3) If we expect contention to be likely:
>>>> * If CAS always brings the cache line into an exclusive state, then
>>>> load
>>>> first. Then do 2).
>>>>
>>>> Do we have consensus yet on whether we assume 2 or 3 (I don't think 1
>>>> buys us anything over 2)?
>>>>
>>> Yes. Sounds good.
>>
>> I read this as stating that you agree that 1) doesn't need to be
>> considered. But we still to choose between 2) and 3) :)
>>
>> I'm not quite sure what to favor because some of the code out there that
>> uses trylock just uses it to prevent deadlock (e.g., when trying to
>> acquire multiple locks at once), whereas other code uses spin_trylock to
>> implement their own back-off and bounded spinning.
>> I lean towards assuming that lock acquisitons, including the former use
>> case for trylock, are supposed to succeed in the common case. That is,
>> I would pick 2), but I have no data to back this up.
>>
>> Either way, whatever we choose, we should document polish the cases 1-3
>> above and the reasoning behind our choice for one of them, and add it as
>> a comment to the spinlock code.
>>
>
> Okay. I've attached an updated patch. It is now using case 2).
> This choice applies to pthread_spin_trylock.c and the first attempt to
> acquire the lock in pthread_spin_lock.c.
> Therefore I've introduced ATOMIC_EXCHANGE_USES_CAS for all architectures
> in atomic-machine.h files. There is a check in include/atomic.h which
> ensures that it is defined to either 0 or 1. Can you please review the
> setting of 0 or 1?
>
> Bye Stefan
Ping
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-21 15:43 ` Stefan Liebler
@ 2017-03-22 12:56 ` Szabolcs Nagy
2017-03-23 16:16 ` Stefan Liebler
2017-04-06 12:04 ` Torvald Riegel
2017-03-27 13:08 ` Stefan Liebler
1 sibling, 2 replies; 63+ messages in thread
From: Szabolcs Nagy @ 2017-03-22 12:56 UTC (permalink / raw)
To: Stefan Liebler, libc-alpha; +Cc: nd
On 21/03/17 15:43, Stefan Liebler wrote:
> On 03/14/2017 04:55 PM, Stefan Liebler wrote:
>> Okay. I've attached an updated patch. It is now using case 2).
>> This choice applies to pthread_spin_trylock.c and the first attempt to
>> acquire the lock in pthread_spin_lock.c.
>> Therefore I've introduced ATOMIC_EXCHANGE_USES_CAS for all architectures
>> in atomic-machine.h files. There is a check in include/atomic.h which
>> ensures that it is defined to either 0 or 1. Can you please review the
>> setting of 0 or 1?
>>
>> Bye Stefan
> Ping
>
the aarch64 changes look ok to me (but this is
something that ideally would be benchmarked on real
hw with interesting workload and i haven't done that
because it is non-trivial)
on a trivial benchmark it seems to be a bit better
than the current code.
the performance of the unconteded case can be improved
slightly by reverting the unlock change (the release
store is stronger than the barrier was, conceptually
there is a barrier before and after an armv8 release
store to prevent an independent load-acquire to get
reordered with it in either direction)
power consumption of a contended spin lock on armv8
can be improved using a send-event/wait-event mechanism,
but then the atomic_spin_nop needs to be in a loop with
an ll/sc pair not with a relaxed load.
(i guess we can introduce a target specific spinlock
if this turns out to be relevant)
(git apply complained about an extra newline at the
end of atomic.h)
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-22 12:56 ` Szabolcs Nagy
@ 2017-03-23 16:16 ` Stefan Liebler
2017-03-23 17:52 ` Szabolcs Nagy
2017-04-06 12:04 ` Torvald Riegel
1 sibling, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-03-23 16:16 UTC (permalink / raw)
To: libc-alpha
On 03/22/2017 01:56 PM, Szabolcs Nagy wrote:
> On 21/03/17 15:43, Stefan Liebler wrote:
>> On 03/14/2017 04:55 PM, Stefan Liebler wrote:
>>> Okay. I've attached an updated patch. It is now using case 2).
>>> This choice applies to pthread_spin_trylock.c and the first attempt to
>>> acquire the lock in pthread_spin_lock.c.
>>> Therefore I've introduced ATOMIC_EXCHANGE_USES_CAS for all architectures
>>> in atomic-machine.h files. There is a check in include/atomic.h which
>>> ensures that it is defined to either 0 or 1. Can you please review the
>>> setting of 0 or 1?
>>>
>>> Bye Stefan
>> Ping
>>
>
> the aarch64 changes look ok to me (but this is
> something that ideally would be benchmarked on real
> hw with interesting workload and i haven't done that
> because it is non-trivial)
>
> on a trivial benchmark it seems to be a bit better
> than the current code.
>
This sounds good.
> the performance of the unconteded case can be improved
> slightly by reverting the unlock change (the release
> store is stronger than the barrier was, conceptually
> there is a barrier before and after an armv8 release
> store to prevent an independent load-acquire to get
> reordered with it in either direction)
>
Thus you mean something like the following?
atomic_thread_fence_release ();
atomic_store_relaxed (lock, 0);
(Info: I've used scripts/build-many-glibcs.py to get the following
objdumps. The sysdeps/powerpc/nptl/pthread_spin_unlock.c is using
atomic_store_release, too. For the following powerpc64-linux-gnu
objdumps, I've removed the powerpc-spinlock implementation to see the
differences)
=>aarch64-linux-gnu
0000000000000000 <pthread_spin_unlock>:
0: d5033bbf dmb ish
4: b900001f str wzr, [x0]
8: 52800000 mov w0, #0x0 // #0
c: d65f03c0 ret
=>powerpc64-linux-gnu:
0000000000000000 <.pthread_spin_unlock>:
0: 7c 69 1b 78 mr r9,r3
4: 7c 20 04 ac lwsync
8: 39 40 00 00 li r10,0
c: 38 60 00 00 li r3,0
10: 91 49 00 00 stw r10,0(r9)
14: 4e 80 00 20 blr
Here is the upstream code as comparison:
atomic_full_barrier ();
*lock = 0;
=>aarch64-linux-gnu
0000000000000000 <pthread_spin_unlock>:
0: aa0003e1 mov x1, x0
4: d5033bbf dmb ish
8: 52800000 mov w0, #0x0 // #0
c: b900003f str wzr, [x1]
10: d65f03c0 ret
=>powerpc64-linux-gnu:
0000000000000000 <.pthread_spin_unlock>:
0: 7c 69 1b 78 mr r9,r3
4: 7c 00 04 ac hwsync
8: 39 40 00 00 li r10,0
c: 38 60 00 00 li r3,0
10: 91 49 00 00 stw r10,0(r9)
14: 4e 80 00 20 blr
And the code of my latest patch:
atomic_store_release (lock, 0);
=>aarch64-linux-gnu
0000000000000000 <pthread_spin_unlock>:
0: 889ffc1f stlr wzr, [x0]
4: 52800000 mov w0, #0x0 // #0
8: d65f03c0 ret
=>powerpc64-linux-gnu:
0000000000000000 <.pthread_spin_unlock>:
0: 7c 69 1b 78 mr r9,r3
4: 7c 20 04 ac lwsync
8: 39 40 00 00 li r10,0
c: 38 60 00 00 li r3,0
10: 91 49 00 00 stw r10,0(r9)
14: 4e 80 00 20 blr
> power consumption of a contended spin lock on armv8
> can be improved using a send-event/wait-event mechanism,
> but then the atomic_spin_nop needs to be in a loop with
> an ll/sc pair not with a relaxed load.
> (i guess we can introduce a target specific spinlock
> if this turns out to be relevant)
>
> (git apply complained about an extra newline at the
> end of atomic.h)
>
Oops. I'll fix it in the next version.
Thanks.
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-23 16:16 ` Stefan Liebler
@ 2017-03-23 17:52 ` Szabolcs Nagy
0 siblings, 0 replies; 63+ messages in thread
From: Szabolcs Nagy @ 2017-03-23 17:52 UTC (permalink / raw)
To: Stefan Liebler, libc-alpha; +Cc: nd
On 23/03/17 16:15, Stefan Liebler wrote:
> On 03/22/2017 01:56 PM, Szabolcs Nagy wrote:
>> the performance of the unconteded case can be improved
>> slightly by reverting the unlock change (the release
>> store is stronger than the barrier was, conceptually
>> there is a barrier before and after an armv8 release
>> store to prevent an independent load-acquire to get
>> reordered with it in either direction)
>>
> Thus you mean something like the following?
> atomic_thread_fence_release ();
> atomic_store_relaxed (lock, 0);
> (Info: I've used scripts/build-many-glibcs.py to get the following objdumps. The
> sysdeps/powerpc/nptl/pthread_spin_unlock.c is using atomic_store_release, too. For the following
> powerpc64-linux-gnu objdumps, I've removed the powerpc-spinlock implementation to see the differences)
> =>aarch64-linux-gnu
> 0000000000000000 <pthread_spin_unlock>:
> 0: d5033bbf dmb ish
> 4: b900001f str wzr, [x0]
> 8: 52800000 mov w0, #0x0 // #0
> c: d65f03c0 ret
> =>powerpc64-linux-gnu:
> 0000000000000000 <.pthread_spin_unlock>:
> 0: 7c 69 1b 78 mr r9,r3
> 4: 7c 20 04 ac lwsync
> 8: 39 40 00 00 li r10,0
> c: 38 60 00 00 li r3,0
> 10: 91 49 00 00 stw r10,0(r9)
> 14: 4e 80 00 20 blr
>
> Here is the upstream code as comparison:
> atomic_full_barrier ();
> *lock = 0;
> =>aarch64-linux-gnu
> 0000000000000000 <pthread_spin_unlock>:
> 0: aa0003e1 mov x1, x0
> 4: d5033bbf dmb ish
> 8: 52800000 mov w0, #0x0 // #0
> c: b900003f str wzr, [x1]
> 10: d65f03c0 ret
> =>powerpc64-linux-gnu:
> 0000000000000000 <.pthread_spin_unlock>:
> 0: 7c 69 1b 78 mr r9,r3
> 4: 7c 00 04 ac hwsync
> 8: 39 40 00 00 li r10,0
> c: 38 60 00 00 li r3,0
> 10: 91 49 00 00 stw r10,0(r9)
> 14: 4e 80 00 20 blr
>
i compared this (full barrier) to
> And the code of my latest patch:
> atomic_store_release (lock, 0);
> =>aarch64-linux-gnu
> 0000000000000000 <pthread_spin_unlock>:
> 0: 889ffc1f stlr wzr, [x0]
> 4: 52800000 mov w0, #0x0 // #0
> 8: d65f03c0 ret
> =>powerpc64-linux-gnu:
> 0000000000000000 <.pthread_spin_unlock>:
> 0: 7c 69 1b 78 mr r9,r3
> 4: 7c 20 04 ac lwsync
> 8: 39 40 00 00 li r10,0
> c: 38 60 00 00 li r3,0
> 10: 91 49 00 00 stw r10,0(r9)
> 14: 4e 80 00 20 blr
>
to this (release store).
but meanwhile i convinced myself that stlr
makes more sense architecturally (even though
on the particular implementation i tested
this on it was slower).
so i'd prefer keeping the atomic_store_release.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-21 15:43 ` Stefan Liebler
2017-03-22 12:56 ` Szabolcs Nagy
@ 2017-03-27 13:08 ` Stefan Liebler
2017-04-04 10:29 ` [PING] " Stefan Liebler
1 sibling, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-03-27 13:08 UTC (permalink / raw)
To: libc-alpha
On 03/21/2017 04:43 PM, Stefan Liebler wrote:
> On 03/14/2017 04:55 PM, Stefan Liebler wrote:
>> On 02/20/2017 02:51 PM, Torvald Riegel wrote:
>>> On Mon, 2017-02-20 at 13:15 +0100, Stefan Liebler wrote:
>>>>>>> A while ago we tried hard to remove all code that would fail
>>>>>>> silently
>>>>>>> when a macro had a typo in the name, for example. We still have a
>>>>>>> few
>>>>>>> of them left (e.g., in the atomics), but I think this here doesn't
>>>>>>> warrant an exception.
>>>>>>>
>>>>>> Okay. You're right.
>>>>>>
>>>>>> In comment of patch 2/2, you've mentioned a header where an
>>>>>> architecture
>>>>>> shall define those parameters.
>>>>>> Thus I've added the file nptl/pthread_spin_parameters.h.
>>>>>
>>>>> I think the stub version should be in sysdeps/ but the wiki is missing
>>>>> this information (default ENOTSUP location):
>>>>> https://sourceware.org/glibc/wiki/Style_and_Conventions#Proper_sysdeps_Location
>>>>>
>>>>>
>>>> In case we need a new header, shall we move it to sysdeps/nptl/ ?
>>>
>>> I would guess that this would be the right place for a stub / generic
>>> variant of such a header, but I'm not quite sure.
>>>
>>>>>
>>>>> I'm still a bit undecided about how to deal with other arch's
>>>>> pthread_spin_lock.c files that just set
>>>>> SPIN_LOCK_READS_BETWEEN_CMPXCHG
>>>>> and then include the generic pthread_spin_lock.c. Maybe it's best
>>>>> if we
>>>>> just remove them in this patch of yours.
>>>>>
>>>> I think the archs currently using the generic implementation have just
>>>> copied the default value to get rid of the warning "machine-dependent
>>>> file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG". But this is
>>>> only an
>>>> assumption.
>>>> In general removing those "wrapper"-pthread_spin_lock.c files and using
>>>> information from a header like the proposed
>>>> pthread_spin_parameters.h or
>>>> atomic-machine.h is a good approach.
>>>
>>> Okay. So let's do that.
>>>
>> Done. The wrapper-pthread_spin_lock.c files in sysdeps subfolders are
>> removed and the option SPIN_LOCK_READS_BETWEEN_CMPXCHG is not available
>> anymore.
>> Instead there is only a loop of plain reads until we observe an not
>> acquired lock.
>> See comment in nptl/pthread_spin_lock.c.
>>
>>>>> I agree that the there are architecture-specific properties of atomic
>>>>> operations that have a significant effect on performance. For s390,
>>>>> you
>>>>> list the following points:
>>>>> * atomic exchange (I suppose all atomic read-modify-write ops?) are
>>>>> implemented through CAS.
>>>> atomic exchange is implemented by a CAS loop due to lack of an exchange
>>>> instruction. For exchanging to a "0", s390 can use the load-and-and
>>>> instruction instead of a CAS loop (See my atomic-machine.h patch; For
>>>> gcc, we plan to emit such a load-and-and instruction for builtin
>>>> __atomic_exchange_n in future;). This also saves one register usage
>>>> compared to the CAS loop.
>>>> Exchanging to "0" is e.g. used for lll_unlock macro or in
>>>> malloc_consolidate.
>>>
>>> I guess this may then be yet another property atomic-machine.h could
>>> expose: Whether an atomic fetch-and-and exists and is not implemented
>>> throough a CAS loop. Something like lll_unlock would then do an
>>> exchange or fetch-and-and, and if that fails, a CAS loop.
>>>
>>>> Starting with z196 zarch CPUs, the following instructions which are
>>>> used
>>>> by the appropriate __atomic_fetch_xyz builtins instead of a CAS loop:
>>>> load-and-add, load-and-and, load-and-exclusive-or, load-and-or.
>>>> As information:
>>>> I will update my atomic-machine.h patch to use at least some of the C11
>>>> atomic builtins or all depending on gcc version.
>>>
>>> Thanks.
>>>
>>>>> These properties are specific to the architecture, but they are not
>>>>> specific to the synchronization code (eg, to spinlocks). Thus, I
>>>>> think
>>>>> such settings should be in the atomics headers (i.e., in
>>>>> atomic-machine.h).
>>>>> This should probably be a separate patch. I would propose the
>>>>> following
>>>>> macros (both are bool):
>>>>> /* Nonzero iff all atomic read-modify-write operations (e.g., atomic
>>>>> exchange) are implemented using a CAS loop. */
>>>>> #define ATOMIC_RMW_USES_CAS 1
>>>> Is one macro enough to describe all read-modify-write operations in
>>>> include/atomic.h?
>>>> Please also see my comment above.
>>>
>>> Yes, it may not be enough (e.g., you say that s390 may have fetch_and
>>> but not an exchange, but other archs may just have an exchange but no
>>> custom fetch_and).
>>> So maybe we should add ATOMIC_EXCHANGE_USES_CAS and
>>> ATOMIC_FETCH_AND_USES_CAS for now, and add further ones on demand?
>>>
>>>>> /* Nonzero iff CAS always assumes it will store, and thus has cache
>>>>> performance effects similar to a store (e.g., it always puts the
>>>>> respective cacheline into an exclusive state, even if the comparison
>>>>> against the expected value fails). */
>>>>> ATOMIC_CAS_ALWAYS_PREPARES_FOR_STORE 1
>>>>>
>>>>> I'm not sure whether there are architectures for which the second
>>>>> macro
>>>>> would not be true. It would be good to investigate this, maybe we
>>>>> don't
>>>>> need to add this at all.
>>>>>
>>>> We plan that in future gcc will emit e.g. a load-and-test
>>>> instruction in
>>>> front of the CAS instruction if the old-value is a constant zero.
>>>
>>> That can be useful, but what I outlined would be about a more generic
>>> case. If you are going to solve this for your arch in gcc, you might
>>> not need to address this in this patch.
>>>
>>>>>
>>>>>
>>>>> For the spin lock specifically, we have the following possibilities:
>>>>>
>>>>> 1) If we assume that trylock will most likely succeed in practice:
>>>>> * We just do an exchange. The properties above don't matter.
>>>>>
>>>>> 2) If we want to bias towards cases where trylock succeeds, but don't
>>>>> rule out contention:
>>>>> * If exchange not a CAS loop, and exchange is faster than CAS, do an
>>>>> exchange.
>>>>> * If exchange is a CAS loop, use a weak CAS and not an exchange so we
>>>>> bail out after the first failed attempt to change the state.
>>>>>
>>>>> 3) If we expect contention to be likely:
>>>>> * If CAS always brings the cache line into an exclusive state, then
>>>>> load
>>>>> first. Then do 2).
>>>>>
>>>>> Do we have consensus yet on whether we assume 2 or 3 (I don't think 1
>>>>> buys us anything over 2)?
>>>>>
>>>> Yes. Sounds good.
>>>
>>> I read this as stating that you agree that 1) doesn't need to be
>>> considered. But we still to choose between 2) and 3) :)
>>>
>>> I'm not quite sure what to favor because some of the code out there that
>>> uses trylock just uses it to prevent deadlock (e.g., when trying to
>>> acquire multiple locks at once), whereas other code uses spin_trylock to
>>> implement their own back-off and bounded spinning.
>>> I lean towards assuming that lock acquisitons, including the former use
>>> case for trylock, are supposed to succeed in the common case. That is,
>>> I would pick 2), but I have no data to back this up.
>>>
>>> Either way, whatever we choose, we should document polish the cases 1-3
>>> above and the reasoning behind our choice for one of them, and add it as
>>> a comment to the spinlock code.
>>>
>>
>> Okay. I've attached an updated patch. It is now using case 2).
>> This choice applies to pthread_spin_trylock.c and the first attempt to
>> acquire the lock in pthread_spin_lock.c.
>> Therefore I've introduced ATOMIC_EXCHANGE_USES_CAS for all architectures
>> in atomic-machine.h files. There is a check in include/atomic.h which
>> ensures that it is defined to either 0 or 1. Can you please review the
>> setting of 0 or 1?
>>
>> Bye Stefan
> Ping
>
Ping
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-14 15:55 ` Stefan Liebler
2017-03-21 15:43 ` Stefan Liebler
@ 2017-03-29 14:16 ` Stefan Liebler
2017-04-06 14:00 ` Torvald Riegel
2 siblings, 0 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-03-29 14:16 UTC (permalink / raw)
To: libc-alpha; +Cc: Torvald Riegel
On 03/14/2017 04:55 PM, Stefan Liebler wrote:
> On 02/20/2017 02:51 PM, Torvald Riegel wrote:
>> On Mon, 2017-02-20 at 13:15 +0100, Stefan Liebler wrote:
>>>>>> A while ago we tried hard to remove all code that would fail silently
>>>>>> when a macro had a typo in the name, for example. We still have a
>>>>>> few
>>>>>> of them left (e.g., in the atomics), but I think this here doesn't
>>>>>> warrant an exception.
>>>>>>
>>>>> Okay. You're right.
>>>>>
>>>>> In comment of patch 2/2, you've mentioned a header where an
>>>>> architecture
>>>>> shall define those parameters.
>>>>> Thus I've added the file nptl/pthread_spin_parameters.h.
>>>>
>>>> I think the stub version should be in sysdeps/ but the wiki is missing
>>>> this information (default ENOTSUP location):
>>>> https://sourceware.org/glibc/wiki/Style_and_Conventions#Proper_sysdeps_Location
>>>>
>>> In case we need a new header, shall we move it to sysdeps/nptl/ ?
>>
>> I would guess that this would be the right place for a stub / generic
>> variant of such a header, but I'm not quite sure.
>>
>>>>
>>>> I'm still a bit undecided about how to deal with other arch's
>>>> pthread_spin_lock.c files that just set SPIN_LOCK_READS_BETWEEN_CMPXCHG
>>>> and then include the generic pthread_spin_lock.c. Maybe it's best
>>>> if we
>>>> just remove them in this patch of yours.
>>>>
>>> I think the archs currently using the generic implementation have just
>>> copied the default value to get rid of the warning "machine-dependent
>>> file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG". But this is only an
>>> assumption.
>>> In general removing those "wrapper"-pthread_spin_lock.c files and using
>>> information from a header like the proposed pthread_spin_parameters.h or
>>> atomic-machine.h is a good approach.
>>
>> Okay. So let's do that.
>>
> Done. The wrapper-pthread_spin_lock.c files in sysdeps subfolders are
> removed and the option SPIN_LOCK_READS_BETWEEN_CMPXCHG is not available
> anymore.
> Instead there is only a loop of plain reads until we observe an not
> acquired lock.
> See comment in nptl/pthread_spin_lock.c.
>
>>>> I agree that the there are architecture-specific properties of atomic
>>>> operations that have a significant effect on performance. For s390,
>>>> you
>>>> list the following points:
>>>> * atomic exchange (I suppose all atomic read-modify-write ops?) are
>>>> implemented through CAS.
>>> atomic exchange is implemented by a CAS loop due to lack of an exchange
>>> instruction. For exchanging to a "0", s390 can use the load-and-and
>>> instruction instead of a CAS loop (See my atomic-machine.h patch; For
>>> gcc, we plan to emit such a load-and-and instruction for builtin
>>> __atomic_exchange_n in future;). This also saves one register usage
>>> compared to the CAS loop.
>>> Exchanging to "0" is e.g. used for lll_unlock macro or in
>>> malloc_consolidate.
>>
>> I guess this may then be yet another property atomic-machine.h could
>> expose: Whether an atomic fetch-and-and exists and is not implemented
>> throough a CAS loop. Something like lll_unlock would then do an
>> exchange or fetch-and-and, and if that fails, a CAS loop.
>>
>>> Starting with z196 zarch CPUs, the following instructions which are used
>>> by the appropriate __atomic_fetch_xyz builtins instead of a CAS loop:
>>> load-and-add, load-and-and, load-and-exclusive-or, load-and-or.
>>> As information:
>>> I will update my atomic-machine.h patch to use at least some of the C11
>>> atomic builtins or all depending on gcc version.
>>
>> Thanks.
>>
>>>> These properties are specific to the architecture, but they are not
>>>> specific to the synchronization code (eg, to spinlocks). Thus, I think
>>>> such settings should be in the atomics headers (i.e., in
>>>> atomic-machine.h).
>>>> This should probably be a separate patch. I would propose the
>>>> following
>>>> macros (both are bool):
>>>> /* Nonzero iff all atomic read-modify-write operations (e.g., atomic
>>>> exchange) are implemented using a CAS loop. */
>>>> #define ATOMIC_RMW_USES_CAS 1
>>> Is one macro enough to describe all read-modify-write operations in
>>> include/atomic.h?
>>> Please also see my comment above.
>>
>> Yes, it may not be enough (e.g., you say that s390 may have fetch_and
>> but not an exchange, but other archs may just have an exchange but no
>> custom fetch_and).
>> So maybe we should add ATOMIC_EXCHANGE_USES_CAS and
>> ATOMIC_FETCH_AND_USES_CAS for now, and add further ones on demand?
>>
>>>> /* Nonzero iff CAS always assumes it will store, and thus has cache
>>>> performance effects similar to a store (e.g., it always puts the
>>>> respective cacheline into an exclusive state, even if the comparison
>>>> against the expected value fails). */
>>>> ATOMIC_CAS_ALWAYS_PREPARES_FOR_STORE 1
>>>>
>>>> I'm not sure whether there are architectures for which the second macro
>>>> would not be true. It would be good to investigate this, maybe we
>>>> don't
>>>> need to add this at all.
>>>>
>>> We plan that in future gcc will emit e.g. a load-and-test instruction in
>>> front of the CAS instruction if the old-value is a constant zero.
>>
>> That can be useful, but what I outlined would be about a more generic
>> case. If you are going to solve this for your arch in gcc, you might
>> not need to address this in this patch.
>>
>>>>
>>>>
>>>> For the spin lock specifically, we have the following possibilities:
>>>>
>>>> 1) If we assume that trylock will most likely succeed in practice:
>>>> * We just do an exchange. The properties above don't matter.
>>>>
>>>> 2) If we want to bias towards cases where trylock succeeds, but don't
>>>> rule out contention:
>>>> * If exchange not a CAS loop, and exchange is faster than CAS, do an
>>>> exchange.
>>>> * If exchange is a CAS loop, use a weak CAS and not an exchange so we
>>>> bail out after the first failed attempt to change the state.
>>>>
>>>> 3) If we expect contention to be likely:
>>>> * If CAS always brings the cache line into an exclusive state, then
>>>> load
>>>> first. Then do 2).
>>>>
>>>> Do we have consensus yet on whether we assume 2 or 3 (I don't think 1
>>>> buys us anything over 2)?
>>>>
>>> Yes. Sounds good.
>>
>> I read this as stating that you agree that 1) doesn't need to be
>> considered. But we still to choose between 2) and 3) :)
>>
>> I'm not quite sure what to favor because some of the code out there that
>> uses trylock just uses it to prevent deadlock (e.g., when trying to
>> acquire multiple locks at once), whereas other code uses spin_trylock to
>> implement their own back-off and bounded spinning.
>> I lean towards assuming that lock acquisitons, including the former use
>> case for trylock, are supposed to succeed in the common case. That is,
>> I would pick 2), but I have no data to back this up.
>>
>> Either way, whatever we choose, we should document polish the cases 1-3
>> above and the reasoning behind our choice for one of them, and add it as
>> a comment to the spinlock code.
>>
>
> Okay. I've attached an updated patch. It is now using case 2).
> This choice applies to pthread_spin_trylock.c and the first attempt to
> acquire the lock in pthread_spin_lock.c.
> Therefore I've introduced ATOMIC_EXCHANGE_USES_CAS for all architectures
> in atomic-machine.h files. There is a check in include/atomic.h which
> ensures that it is defined to either 0 or 1. Can you please review the
> setting of 0 or 1?
>
> Bye Stefan
I link the post of Torvald Riegel in this spinlock mailthread, so we
have all the discussions here. See
"Re: [PATCH v3 0/6] Add support for ISO C11 threads.h"
(https://www.sourceware.org/ml/libc-alpha/2017-03/msg00615.html):
Current DR log: http://www.open-std.org/jtc1/sc22/wg14/www/docs/n2109.htm
470:
C11's requirements on implementations are weaker than what POSIX
requires. Arguably, POSIX should require what C11 requires.
We need to check the lowlevellock implementation, in particular on archs
that use LL/SC (I'm not aware of an arch with a true CAS instruction
that can fail spuriously).
Our generic lowlevellock implementation on master still uses the
old-style atomics (ie, atomic_compare_and_exchange_bool_acq); if we move
to C11 atomics, C11 (with DR 470's proposed corrigendum applied) would
require our atomic_compare_exchange_weak_acquire, whereas current POSIX
would require the strong variant of the CAS.
Thus, what we do is okay in terms of C11.
I don't recall right now whether we have an open Austin Group bug about
POSIX allowing a spurious failure; I believe we have, or we should,
because this is also related to what memory order is required for lock
acquisitions (generally, not just trylock).
(Stefan, that's why I'm CC'ing you too, this is relevant for
pthread_spin_trylock too, but I can't remember right now whether we
already discussed this or not.)
Thus you mean we have to use a "atomic_compare_exchange_strong_acquire"
in pthread_spin_trylock due to POSIX?
I've found your "Bug 17428 - lll_trylock barrier semantics when lock was
not acquired differ between architectures"
(https://sourceware.org/bugzilla/show_bug.cgi?id=17428)
and an older post: "Re: [PATCHv2] powerpc: Spinlock optimization and
cleanup" (https://sourceware.org/ml/libc-alpha/2015-10/msg00012.html).
Bye
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PING] [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-27 13:08 ` Stefan Liebler
@ 2017-04-04 10:29 ` Stefan Liebler
0 siblings, 0 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-04-04 10:29 UTC (permalink / raw)
To: libc-alpha; +Cc: Torvald Riegel
On 03/27/2017 03:08 PM, Stefan Liebler wrote:
> On 03/21/2017 04:43 PM, Stefan Liebler wrote:
>> On 03/14/2017 04:55 PM, Stefan Liebler wrote:
>>> On 02/20/2017 02:51 PM, Torvald Riegel wrote:
>>>> On Mon, 2017-02-20 at 13:15 +0100, Stefan Liebler wrote:
>>>>>>>> A while ago we tried hard to remove all code that would fail
>>>>>>>> silently
>>>>>>>> when a macro had a typo in the name, for example. We still have a
>>>>>>>> few
>>>>>>>> of them left (e.g., in the atomics), but I think this here doesn't
>>>>>>>> warrant an exception.
>>>>>>>>
>>>>>>> Okay. You're right.
>>>>>>>
>>>>>>> In comment of patch 2/2, you've mentioned a header where an
>>>>>>> architecture
>>>>>>> shall define those parameters.
>>>>>>> Thus I've added the file nptl/pthread_spin_parameters.h.
>>>>>>
>>>>>> I think the stub version should be in sysdeps/ but the wiki is
>>>>>> missing
>>>>>> this information (default ENOTSUP location):
>>>>>> https://sourceware.org/glibc/wiki/Style_and_Conventions#Proper_sysdeps_Location
>>>>>>
>>>>>>
>>>>>>
>>>>> In case we need a new header, shall we move it to sysdeps/nptl/ ?
>>>>
>>>> I would guess that this would be the right place for a stub / generic
>>>> variant of such a header, but I'm not quite sure.
>>>>
>>>>>>
>>>>>> I'm still a bit undecided about how to deal with other arch's
>>>>>> pthread_spin_lock.c files that just set
>>>>>> SPIN_LOCK_READS_BETWEEN_CMPXCHG
>>>>>> and then include the generic pthread_spin_lock.c. Maybe it's best
>>>>>> if we
>>>>>> just remove them in this patch of yours.
>>>>>>
>>>>> I think the archs currently using the generic implementation have just
>>>>> copied the default value to get rid of the warning "machine-dependent
>>>>> file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG". But this is
>>>>> only an
>>>>> assumption.
>>>>> In general removing those "wrapper"-pthread_spin_lock.c files and
>>>>> using
>>>>> information from a header like the proposed
>>>>> pthread_spin_parameters.h or
>>>>> atomic-machine.h is a good approach.
>>>>
>>>> Okay. So let's do that.
>>>>
>>> Done. The wrapper-pthread_spin_lock.c files in sysdeps subfolders are
>>> removed and the option SPIN_LOCK_READS_BETWEEN_CMPXCHG is not available
>>> anymore.
>>> Instead there is only a loop of plain reads until we observe an not
>>> acquired lock.
>>> See comment in nptl/pthread_spin_lock.c.
>>>
>>>>>> I agree that the there are architecture-specific properties of atomic
>>>>>> operations that have a significant effect on performance. For s390,
>>>>>> you
>>>>>> list the following points:
>>>>>> * atomic exchange (I suppose all atomic read-modify-write ops?) are
>>>>>> implemented through CAS.
>>>>> atomic exchange is implemented by a CAS loop due to lack of an
>>>>> exchange
>>>>> instruction. For exchanging to a "0", s390 can use the load-and-and
>>>>> instruction instead of a CAS loop (See my atomic-machine.h patch; For
>>>>> gcc, we plan to emit such a load-and-and instruction for builtin
>>>>> __atomic_exchange_n in future;). This also saves one register usage
>>>>> compared to the CAS loop.
>>>>> Exchanging to "0" is e.g. used for lll_unlock macro or in
>>>>> malloc_consolidate.
>>>>
>>>> I guess this may then be yet another property atomic-machine.h could
>>>> expose: Whether an atomic fetch-and-and exists and is not implemented
>>>> throough a CAS loop. Something like lll_unlock would then do an
>>>> exchange or fetch-and-and, and if that fails, a CAS loop.
>>>>
>>>>> Starting with z196 zarch CPUs, the following instructions which are
>>>>> used
>>>>> by the appropriate __atomic_fetch_xyz builtins instead of a CAS loop:
>>>>> load-and-add, load-and-and, load-and-exclusive-or, load-and-or.
>>>>> As information:
>>>>> I will update my atomic-machine.h patch to use at least some of the
>>>>> C11
>>>>> atomic builtins or all depending on gcc version.
>>>>
>>>> Thanks.
>>>>
>>>>>> These properties are specific to the architecture, but they are not
>>>>>> specific to the synchronization code (eg, to spinlocks). Thus, I
>>>>>> think
>>>>>> such settings should be in the atomics headers (i.e., in
>>>>>> atomic-machine.h).
>>>>>> This should probably be a separate patch. I would propose the
>>>>>> following
>>>>>> macros (both are bool):
>>>>>> /* Nonzero iff all atomic read-modify-write operations (e.g., atomic
>>>>>> exchange) are implemented using a CAS loop. */
>>>>>> #define ATOMIC_RMW_USES_CAS 1
>>>>> Is one macro enough to describe all read-modify-write operations in
>>>>> include/atomic.h?
>>>>> Please also see my comment above.
>>>>
>>>> Yes, it may not be enough (e.g., you say that s390 may have fetch_and
>>>> but not an exchange, but other archs may just have an exchange but no
>>>> custom fetch_and).
>>>> So maybe we should add ATOMIC_EXCHANGE_USES_CAS and
>>>> ATOMIC_FETCH_AND_USES_CAS for now, and add further ones on demand?
>>>>
>>>>>> /* Nonzero iff CAS always assumes it will store, and thus has cache
>>>>>> performance effects similar to a store (e.g., it always puts the
>>>>>> respective cacheline into an exclusive state, even if the comparison
>>>>>> against the expected value fails). */
>>>>>> ATOMIC_CAS_ALWAYS_PREPARES_FOR_STORE 1
>>>>>>
>>>>>> I'm not sure whether there are architectures for which the second
>>>>>> macro
>>>>>> would not be true. It would be good to investigate this, maybe we
>>>>>> don't
>>>>>> need to add this at all.
>>>>>>
>>>>> We plan that in future gcc will emit e.g. a load-and-test
>>>>> instruction in
>>>>> front of the CAS instruction if the old-value is a constant zero.
>>>>
>>>> That can be useful, but what I outlined would be about a more generic
>>>> case. If you are going to solve this for your arch in gcc, you might
>>>> not need to address this in this patch.
>>>>
>>>>>>
>>>>>>
>>>>>> For the spin lock specifically, we have the following possibilities:
>>>>>>
>>>>>> 1) If we assume that trylock will most likely succeed in practice:
>>>>>> * We just do an exchange. The properties above don't matter.
>>>>>>
>>>>>> 2) If we want to bias towards cases where trylock succeeds, but don't
>>>>>> rule out contention:
>>>>>> * If exchange not a CAS loop, and exchange is faster than CAS, do an
>>>>>> exchange.
>>>>>> * If exchange is a CAS loop, use a weak CAS and not an exchange so we
>>>>>> bail out after the first failed attempt to change the state.
>>>>>>
>>>>>> 3) If we expect contention to be likely:
>>>>>> * If CAS always brings the cache line into an exclusive state, then
>>>>>> load
>>>>>> first. Then do 2).
>>>>>>
>>>>>> Do we have consensus yet on whether we assume 2 or 3 (I don't think 1
>>>>>> buys us anything over 2)?
>>>>>>
>>>>> Yes. Sounds good.
>>>>
>>>> I read this as stating that you agree that 1) doesn't need to be
>>>> considered. But we still to choose between 2) and 3) :)
>>>>
>>>> I'm not quite sure what to favor because some of the code out there
>>>> that
>>>> uses trylock just uses it to prevent deadlock (e.g., when trying to
>>>> acquire multiple locks at once), whereas other code uses
>>>> spin_trylock to
>>>> implement their own back-off and bounded spinning.
>>>> I lean towards assuming that lock acquisitons, including the former use
>>>> case for trylock, are supposed to succeed in the common case. That is,
>>>> I would pick 2), but I have no data to back this up.
>>>>
>>>> Either way, whatever we choose, we should document polish the cases 1-3
>>>> above and the reasoning behind our choice for one of them, and add
>>>> it as
>>>> a comment to the spinlock code.
>>>>
>>>
>>> Okay. I've attached an updated patch. It is now using case 2).
>>> This choice applies to pthread_spin_trylock.c and the first attempt to
>>> acquire the lock in pthread_spin_lock.c.
>>> Therefore I've introduced ATOMIC_EXCHANGE_USES_CAS for all architectures
>>> in atomic-machine.h files. There is a check in include/atomic.h which
>>> ensures that it is defined to either 0 or 1. Can you please review the
>>> setting of 0 or 1?
>>>
>>> Bye Stefan
>> Ping
>>
>
> Ping
>
PING
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-22 12:56 ` Szabolcs Nagy
2017-03-23 16:16 ` Stefan Liebler
@ 2017-04-06 12:04 ` Torvald Riegel
1 sibling, 0 replies; 63+ messages in thread
From: Torvald Riegel @ 2017-04-06 12:04 UTC (permalink / raw)
To: Szabolcs Nagy; +Cc: Stefan Liebler, libc-alpha, nd
On Wed, 2017-03-22 at 12:56 +0000, Szabolcs Nagy wrote:
> On 21/03/17 15:43, Stefan Liebler wrote:
> > On 03/14/2017 04:55 PM, Stefan Liebler wrote:
> >> Okay. I've attached an updated patch. It is now using case 2).
> >> This choice applies to pthread_spin_trylock.c and the first attempt to
> >> acquire the lock in pthread_spin_lock.c.
> >> Therefore I've introduced ATOMIC_EXCHANGE_USES_CAS for all architectures
> >> in atomic-machine.h files. There is a check in include/atomic.h which
> >> ensures that it is defined to either 0 or 1. Can you please review the
> >> setting of 0 or 1?
> >>
> >> Bye Stefan
> > Ping
> >
>
> the aarch64 changes look ok to me (but this is
> something that ideally would be benchmarked on real
> hw with interesting workload and i haven't done that
> because it is non-trivial)
This is something that we need to continue working on. I don't think
it's required for this patch. But any further tuning will need some
benchmark.
I won't have time to work on benchmarks in the foreseeable future I
believe; it would be great if you, Stefan, or someone else could
continue to work on this.
> power consumption of a contended spin lock on armv8
> can be improved using a send-event/wait-event mechanism,
> but then the atomic_spin_nop needs to be in a loop with
> an ll/sc pair not with a relaxed load.
> (i guess we can introduce a target specific spinlock
> if this turns out to be relevant)
Interesting. I expect the machine maintainers to drive such
optimizations in the future; performance differences should be made
reproducable using benchmarks contributed to glibc.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 2/2] S390: Use generic spinlock code.
2017-03-14 15:55 ` Stefan Liebler
2017-03-21 15:43 ` Stefan Liebler
@ 2017-04-06 12:27 ` Torvald Riegel
1 sibling, 0 replies; 63+ messages in thread
From: Torvald Riegel @ 2017-04-06 12:27 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Tue, 2017-03-14 at 16:55 +0100, Stefan Liebler wrote:
> On 02/18/2017 06:05 PM, Torvald Riegel wrote:
> > On Wed, 2017-02-15 at 17:26 +0100, Stefan Liebler wrote:
> >> On 02/13/2017 09:39 PM, Torvald Riegel wrote:
> >>> On Wed, 2017-02-08 at 15:49 +0100, Stefan Liebler wrote:
> >>> Also, I'm not quite sure whether this number is really
> >>> spinlock-specific, and I would like to find a better place for these.
> >>> IMO, they should be in some header that contains default tuning
> >>> parameters for synchronization code, which is provided by each
> >>> architecture that uses the generic spinlock; we'd have no #ifdef for the
> >>> tuning parameters, so we'd catch typos in those headers.
> >>>
> >> See pthread_spin_parameters.h in updated patch 1/2.
> >
> > I suggest that we'll work towards consensus on patch 1/2 first. I
> > believe once that is done, patch 2/2 would likely just remove s390 code.
> >
> I've attached an updated patch which just removes the s390 code.
Okay.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-03-14 15:55 ` Stefan Liebler
2017-03-21 15:43 ` Stefan Liebler
2017-03-29 14:16 ` Stefan Liebler
@ 2017-04-06 14:00 ` Torvald Riegel
2017-04-07 16:23 ` Stefan Liebler
2017-04-18 21:17 ` Joseph Myers
2 siblings, 2 replies; 63+ messages in thread
From: Torvald Riegel @ 2017-04-06 14:00 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Tue, 2017-03-14 at 16:55 +0100, Stefan Liebler wrote:
> +/* This is equal to 1 if atomic_exchange is implemented by a CAS loop
> + and 0 if atomic_exchange is implemented with an instruction faster than
> + CAS. */
I'd change this to:
"ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
are implemented based on a CAS loop; otherwise, this is 0 and we assume
that the atomic_exchange operations could provide better performance
than a CAS loop."
> +#if ! defined ATOMIC_EXCHANGE_USES_CAS || ! (ATOMIC_EXCHANGE_USES_CAS == 0 \
> + || ATOMIC_EXCHANGE_USES_CAS == 1)
> +# error ATOMIC_EXCHANGE_USES_CAS has to be defined to 0 or 1
> +#endif
> +
> #endif /* atomic.h */
> +
Extra new line.
> diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
> index 4d03b78..c2fb8e7 100644
> --- a/nptl/pthread_spin_lock.c
>
> +++ b/nptl/pthread_spin_lock.c
>
> @@ -19,27 +19,38 @@
> #include <atomic.h>
> #include "pthreadP.h"
>
> -/* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
>
> - to the number of plain reads that it's optimal to spin on between uses
>
> - of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
>
> - then use -1. If no plain reads here would ever be optimal, use 0. */
>
> -#ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
>
> -# warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
>
> -# define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
>
> -#endif
>
> -
>
> int
> pthread_spin_lock (pthread_spinlock_t *lock)
> {
> + int val = 0;
>
> +
>
> /* atomic_exchange usually takes less instructions than
> atomic_compare_and_exchange. On the other hand,
> atomic_compare_and_exchange potentially generates less bus traffic
> when the lock is locked.
I'd remove these sentences, and rather come back to this ...
> - We assume that the first try mostly will be successful, and we use
>
> - atomic_exchange. For the subsequent tries we use
>
> - atomic_compare_and_exchange. */
>
> - if (atomic_exchange_acq (lock, 1) == 0)
>
> + We assume that the first try mostly will be successful, thus we use
>
> + atomic_exchange if it is not implemented by a CAS loop. Otherwise
.. here. Change to:
We assume that the first try mostly will be successful, thus we use
atomic_exchange if it is not implemented by a CAS loop (we also assume
that atomic_exchange can be faster if it succeeds, see
ATOMIC_EXCHANGE_USES_CAS). Otherwise,
>
> + we use a weak CAS and not an exchange so we bail out after the first
>
> + failed attempt to change the state.
>
> + For the subsequent tries we use atomic_compare_and_exchange after we
>
> + observe a not acquired lock.
s/subsequent tries/subsequent attempts,/
s/a not acquired lock/that the lock is not acquired/
> + See also comment in pthread_spin_trylock.
Also see the comment ...
>
> + We use acquire MO to synchronize-with the release MO store in
>
> + pthread_spin_unlock, and thus ensure that prior critical sections
>
> + happen-before this critical section. */
>
> +#if ATOMIC_EXCHANGE_USES_CAS == 0
We make this a binary macro, so #if !... or #if != 0 is fine.
> + /* Try to acquire the lock with an exchange instruction as this architecture
>
> + has such an instruction and we assume it is faster than a CAS.
>
> + The acquisition succeeds if the lock had not been acquired before. */
change to: ... if the lock is not in an acquired state.
(What you are saying is that the lock had (never) been acquired before,
which doesn't make sense.)
> + if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
>
> + return 0;
>
> +#elif ATOMIC_EXCHANGE_USES_CAS == 1
just #else
> + /* Try to acquire the lock with a CAS instruction as this architecture
>
> + has no exchange instruction. The acquisition succeeds if the lock is not
>
> + acquired. */
>
> + if (__glibc_likely (atomic_compare_exchange_weak_acquire (lock, &val, 1)))
>
> return 0;
> +#endif
>
>
> do
> {
> @@ -47,23 +58,24 @@ pthread_spin_lock (pthread_spinlock_t *lock)
> to cmpxchg is not a good idea on many targets as that will force
> expensive memory synchronizations among processors and penalize other
> running threads.
> - On the other hand, we do want to update memory state on the local core
>
> - once in a while to avoid spinning indefinitely until some event that
>
> - will happen to update local memory as a side-effect. */
>
> - if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
>
> + There is no technical reason for throwing in a CAS every now and then,
>
> + and so far we have no evidence that it can improve performance.
>
> + If that would be the case, we have to adjust other spin-waiting loops
>
> + elsewhere, too!
>
> + Thus we use relaxed MO reads until we observe the lock to not be
>
> + acquired anymore. */
>
> + do
>
> {
> - int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
Please add this comment here (we've been adding it elsewhere too, in
similar cases):
/* TODO Back-off. */
> + atomic_spin_nop ();
>
>
> - while (*lock != 0 && wait > 0)
>
> - --wait;
>
> - }
>
> - else
>
> - {
>
> - while (*lock != 0)
>
> - ;
>
> + val = atomic_load_relaxed (lock);
>
> }
> + while (val != 0);
>
> +
>
> + /* We need acquire memory order here for the same reason as mentioned
>
> + for the first try to lock the spinlock. */
>
> }
> - while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
>
> + while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
>
>
> return 0;
> }
> diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
> index 593bba3..a3e9e44 100644
> --- a/nptl/pthread_spin_trylock.c
>
> +++ b/nptl/pthread_spin_trylock.c
>
> @@ -23,5 +23,51 @@
> int
> pthread_spin_trylock (pthread_spinlock_t *lock)
> {
> - return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
>
> + /* For the spin try lock, we have the following possibilities:
>
> +
>
> + 1) If we assume that trylock will most likely succeed in practice:
>
> + * We just do an exchange.
>
> +
>
> + 2) If we want to bias towards cases where trylock succeeds, but don't
>
> + rule out contention:
>
> + * If exchange is not implemented by a CAS loop, and exchange is faster
>
> + than CAS, do an exchange.
>
> + * If exchange is implemented by a CAS loop, use a weak CAS and not an
>
> + exchange so we bail out after the first failed attempt to change the state.
>
> +
>
> + 3) If we expect contention to be likely:
>
> + * If CAS always brings the cache line into an exclusive state even if the
>
> + spinlock is already acquired, then load the value first with
>
> + atomic_load_relaxed and test if lock is not acquired. Then do 2).
>
> +
>
> + We prefer case 2) as some of the code out there that uses trylock just
>
> + uses it to prevent deadlock (e.g., when trying to acquire multiple locks
>
> + at once), whereas other code uses spin_trylock to implement their own
>
> + back-off and bounded spinning.
>
> + Our assumption is that lock acquisitions, including the former use case
>
> + for trylock, are supposed to succeed in the common case.
>
> + Thus we choose case 2) as it uses the faster exchange instruction if the
>
> + architecture has such an instruction. For those architectures case 2)
>
> + is the same as 1). On the other architectures we are now using one CAS
>
> + with zero as expected value instead of a CAS loop to exchange to one. */
I'd just say that we assume that 2) is the common case, and that this
won't be slower than 1) in the common case.
We'd have to rephrase the other sentences too much to make them easy to
understand, and I don't think they are really necessary.
> +
>
> + /* We use acquire MO to synchronize-with the release MO store in
>
> + pthread_spin_unlock, and thus ensure that prior critical sections
>
> + happen-before this critical section. */
>
> +#if ATOMIC_EXCHANGE_USES_CAS == 0
>
> + /* Try to acquire the lock with an exchange instruction as this architecture
>
> + has such an instruction and we assume it is faster than a CAS.
>
> + The acquisition succeeds if the lock had not been acquired before. */
See above.
> + if (atomic_exchange_acquire (lock, 1) == 0)
>
> + return 0;
>
> +#elif ATOMIC_EXCHANGE_USES_CAS == 1
See above.
> + /* Try to acquire the lock with a CAS instruction as this architecture
>
> + has no exchange instruction. The acquisition succeeds if the lock is not
>
> + acquired. */
>
> + int val = 0;
>
> + if (atomic_compare_exchange_weak_acquire (lock, &val, 1))
>
> + return 0;
Here is where we may address the spurious failure issue:
do
{
/* Make sure we always expect a lock that is not acquired. */
int val = 0;
if (atomic_compare_exchange_weak_acquire (lock, &val, 1))
return 0;
}
/* atomic_compare_exchange_weak_acquire can fail spuriously. Whereas
C++11 and C11 make it clear that trylock operations can fail spuriously,
POSIX does not explicitly specify this; it only specifies that failing
synchronization operations do not need to have synchronization effects
themselves, but a spurious failure is something that could contradict a
happens-before established earlier (e.g., that we need to observe that
the lock is acquired). Therefore, we emulate a strong CAS by simply
checking with a relaxed MO load that the lock is really acquired before
returning EBUSY; the additional overhead this may cause is on the slow
path. */
while (atomic_load_relaxed (lock) == 0);
> +#endif
>
> +
>
> + return EBUSY;
>
> }
> diff --git a/sysdeps/aarch64/atomic-machine.h b/sysdeps/aarch64/atomic-machine.h
> index a5d2213..eb59a5b 100644
> --- a/sysdeps/aarch64/atomic-machine.h
>
> +++ b/sysdeps/aarch64/atomic-machine.h
>
> @@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
>
> #define __HAVE_64B_ATOMICS 1
> #define USE_ATOMIC_COMPILER_BUILTINS 1
> +#define ATOMIC_EXCHANGE_USES_CAS 0
I'll ask Szabolcs again about this. We may need a comment here
explaining the choice.
>
> /* Compare and exchange.
> For all "bool" routines, we return FALSE if exchange succesful. */
> diff --git a/sysdeps/alpha/atomic-machine.h b/sysdeps/alpha/atomic-machine.h
> index 06e93f2..e55ecdd 100644
> --- a/sysdeps/alpha/atomic-machine.h
>
> +++ b/sysdeps/alpha/atomic-machine.h
>
> @@ -44,6 +44,7 @@ typedef uintmax_t uatomic_max_t;
>
> #define __HAVE_64B_ATOMICS 1
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
This should be 1, I believe.
>
>
> #ifdef UP
> diff --git a/sysdeps/arm/atomic-machine.h b/sysdeps/arm/atomic-machine.h
> index eeac7f0..2556438 100644
> --- a/sysdeps/arm/atomic-machine.h
>
> +++ b/sysdeps/arm/atomic-machine.h
>
> @@ -35,6 +35,7 @@ typedef uintmax_t uatomic_max_t;
>
> #define __HAVE_64B_ATOMICS 0
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
This should be 1. Szabolcs?
>
> void __arm_link_error (void);
>
> diff --git a/sysdeps/microblaze/atomic-machine.h b/sysdeps/microblaze/atomic-machine.h
> index dc5309c..3a9b58f 100644
> --- a/sysdeps/microblaze/atomic-machine.h
>
> +++ b/sysdeps/microblaze/atomic-machine.h
>
> @@ -37,6 +37,7 @@ typedef uintmax_t uatomic_max_t;
>
> #define __HAVE_64B_ATOMICS 0
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
1, not 0.
Have you been actually looking at these? The next line in the file is a
pretty obvious hint that this is an LLSC machine, and atomic_exchange
isn't defined anywhere:
> /* Microblaze does not have byte and halfword forms of load and reserve and
> diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h
> index 54c182b..3d9da0c 100644
> --- a/sysdeps/mips/atomic-machine.h
>
> +++ b/sysdeps/mips/atomic-machine.h
>
> @@ -50,6 +50,8 @@ typedef uintmax_t uatomic_max_t;
> #define __HAVE_64B_ATOMICS 1
> #endif
>
> +#define ATOMIC_EXCHANGE_USES_CAS 0
>
> +
Please ask the MIPS maintainers to review this.
> /* See the comments in <sys/asm.h> about the use of the sync instruction. */
> #ifndef MIPS_SYNC
> # define MIPS_SYNC sync
> diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/powerpc32/atomic-machine.h
> index 20d5e85..8f4407b 100644
> --- a/sysdeps/powerpc/powerpc32/atomic-machine.h
>
> +++ b/sysdeps/powerpc/powerpc32/atomic-machine.h
>
> @@ -35,6 +35,7 @@
>
> #define __HAVE_64B_ATOMICS 0
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
1
>
> /*
> * The 32-bit exchange_bool is different on powerpc64 because the subf
> diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h
> index 40c308e..9c4a55b 100644
> --- a/sysdeps/powerpc/powerpc64/atomic-machine.h
>
> +++ b/sysdeps/powerpc/powerpc64/atomic-machine.h
>
> @@ -35,6 +35,7 @@
>
> #define __HAVE_64B_ATOMICS 1
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
1
>
> /* The 32-bit exchange_bool is different on powerpc64 because the subf
> does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
> diff --git a/sysdeps/sparc/sparc32/atomic-machine.h b/sysdeps/sparc/sparc32/atomic-machine.h
> index acd029e..9b2eb47 100644
> --- a/sysdeps/sparc/sparc32/atomic-machine.h
>
> +++ b/sysdeps/sparc/sparc32/atomic-machine.h
>
> @@ -49,6 +49,7 @@ typedef uintmax_t uatomic_max_t;
>
> #define __HAVE_64B_ATOMICS 0
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
I believe this should be 1.
>
> /* We have no compare and swap, just test and set.
> diff --git a/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h b/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
> index 7f7895e..c3486b4 100644
> --- a/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
>
> +++ b/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
>
> @@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
>
> #define __HAVE_64B_ATOMICS 0
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
Likewise.
>
>
> #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
> diff --git a/sysdeps/sparc/sparc64/atomic-machine.h b/sysdeps/sparc/sparc64/atomic-machine.h
> index 44a43ff..21ef009 100644
> --- a/sysdeps/sparc/sparc64/atomic-machine.h
>
> +++ b/sysdeps/sparc/sparc64/atomic-machine.h
>
> @@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
>
> #define __HAVE_64B_ATOMICS 1
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
Likewise.
>
>
> #define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
> diff --git a/sysdeps/tile/tilegx/atomic-machine.h b/sysdeps/tile/tilegx/atomic-machine.h
> index 6345251..e77f670 100644
> --- a/sysdeps/tile/tilegx/atomic-machine.h
>
> +++ b/sysdeps/tile/tilegx/atomic-machine.h
>
> @@ -31,6 +31,7 @@
> #endif
>
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
Ask the tile maintainers. I assume this could be either 1 or 0, because
both go into the kernel.
>
> /* Pick appropriate 8- or 4-byte instruction. */
> #define __atomic_update(mem, v, op) \
> diff --git a/sysdeps/tile/tilepro/atomic-machine.h b/sysdeps/tile/tilepro/atomic-machine.h
> index 33a8b85..45e36de 100644
> --- a/sysdeps/tile/tilepro/atomic-machine.h
>
> +++ b/sysdeps/tile/tilepro/atomic-machine.h
>
> @@ -23,6 +23,7 @@
>
> #define __HAVE_64B_ATOMICS 0
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 0
Likewise.
>
> /* 32-bit integer compare-and-exchange. */
> static __inline __attribute__ ((always_inline))
> diff --git a/sysdeps/unix/sysv/linux/hppa/atomic-machine.h b/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
> index 2cd2235..9adcab7 100644
> --- a/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
>
> +++ b/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
>
> @@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
>
> #define __HAVE_64B_ATOMICS 0
> #define USE_ATOMIC_COMPILER_BUILTINS 0
> +#define ATOMIC_EXCHANGE_USES_CAS 1
Same as for tile.
>
> /* prev = *addr;
> if (prev == old)
Otherwise, this patch looks good to me.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-06 14:00 ` Torvald Riegel
@ 2017-04-07 16:23 ` Stefan Liebler
2017-04-09 13:51 ` Torvald Riegel
` (2 more replies)
2017-04-18 21:17 ` Joseph Myers
1 sibling, 3 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-04-07 16:23 UTC (permalink / raw)
To: libc-alpha
Cc: szabolcs.nagy, marcus.shawcroft, pb, Joseph S. Myers, rth,
Carlos O'Donell, vapier, schwab, cmetcalf, david,
chunglin_tang, munroesj, davem, cmetcalf
[-- Attachment #1: Type: text/plain, Size: 2847 bytes --]
On 04/06/2017 04:00 PM, Torvald Riegel wrote:
> Otherwise, this patch looks good to me.
Thanks for review. Here is an updated patch. I've changed the comments
and added the POSIX requirement in pthread_spin_trylock.
@architecture maintainers:
I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
specific atomic-machine.h files.
See comment in include/atomic.h:
/* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
are implemented based on a CAS loop; otherwise, this is 0 and we assume
that the atomic_exchange operations could provide better performance
than a CAS loop. */
Can review the definition to 0 or 1 in the atomic-machine.h file of your
architecture, please?
ChangeLog:
* NEWS: Mention new spinlock implementation.
* include/atomic.h:
(__atomic_val_bysize): Cast type to omit volatile qualifier.
(atomic_exchange_acq): Likewise.
(atomic_load_relaxed): Likewise.
(ATOMIC_EXCHANGE_USES_CAS): Check definition.
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros.
* nptl/pthread_spin_trylock.c (pthread_spin_trylock):
Likewise.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
* sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/arm/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/hppa/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/m68k/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/microblaze/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/mips/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/nios2/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/aarch64/atomic-machine.h (ATOMIC_EXCHANGE_USES_CAS):
Define.
* sysdeps/alpha/atomic-machine.h: Likewise.
* sysdeps/arm/atomic-machine.h: Likewise.
* sysdeps/i386/atomic-machine.h: Likewise.
* sysdeps/ia64/atomic-machine.h: Likewise.
* sysdeps/m68k/coldfire/atomic-machine.h: Likewise.
* sysdeps/m68k/m680x0/m68020/atomic-machine.h: Likewise.
* sysdeps/microblaze/atomic-machine.h: Likewise.
* sysdeps/mips/atomic-machine.h: Likewise.
* sysdeps/powerpc/powerpc32/atomic-machine.h: Likewise.
* sysdeps/powerpc/powerpc64/atomic-machine.h: Likewise.
* sysdeps/s390/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc32/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc32/sparcv9/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc64/atomic-machine.h: Likewise.
* sysdeps/tile/tilegx/atomic-machine.h: Likewise.
* sysdeps/tile/tilepro/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/hppa/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h:
Likewise.
* sysdeps/unix/sysv/linux/nios2/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/sh/atomic-machine.h: Likewise.
* sysdeps/x86_64/atomic-machine.h: Likewise.
Bye
Stefan
[-- Attachment #2: 0001-Optimize-generic-spinlock-code-and-use-C11-like-atom.patch --]
[-- Type: text/x-patch, Size: 37443 bytes --]
From db4c69c6d20bfe4cc3fedcbd5571736dc50c290d Mon Sep 17 00:00:00 2001
From: Stefan Liebler <stli@linux.vnet.ibm.com>
Date: Fri, 7 Apr 2017 18:15:09 +0200
Subject: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic
macros.
This patch optimizes the generic spinlock code.
The type pthread_spinlock_t is a typedef to volatile int on all archs.
Passing a volatile pointer to the atomic macros which are not mapped to the
C11 atomic builtins can lead to extra stores and loads to stack if such
a macro creates a temporary variable by using "__typeof (*(mem)) tmp;".
Thus, those macros which are used by spinlock code - atomic_exchange_acquire,
atomic_load_relaxed, atomic_compare_exchange_weak - have to be adjusted.
According to the comment from Szabolcs Nagy, the type of a cast expression is
unqualified (see http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm):
__typeof ((__typeof (*(mem)) *(mem)) tmp;
Thus from spinlock perspective the variable tmp is of type int instead of
type volatile int. This patch adjusts those macros in include/atomic.h.
With this construct GCC >= 5 omits the extra stores and loads.
The atomic macros are replaced by the C11 like atomic macros and thus
the code is aligned to it. The pthread_spin_unlock implementation is now
using release memory order instead of sequentially consistent memory order.
The issue with passed volatile int pointers applies to the C11 like atomic
macros as well as the ones used before.
I've added a glibc_likely hint to the first atomic exchange in
pthread_spin_lock in order to return immediately to the caller if the lock is
free. Without the hint, there is an additional jump if the lock is free.
I've added the atomic_spin_nop macro within the loop of plain reads.
The plain reads are also realized by C11 like atomic_load_relaxed macro.
The new define ATOMIC_EXCHANGE_USES_CAS determines if the first try to acquire
the spinlock in pthread_spin_lock or pthread_spin_trylock is an exchange
or a CAS. This is defined in atomic-machine.h for all architectures.
The define SPIN_LOCK_READS_BETWEEN_CMPXCHG is now removed.
There is no technical reason for throwing in a CAS every now and then,
and so far we have no evidence that it can improve performance.
If that would be the case, we have to adjust other spin-waiting loops
elsewhere, too! Using a CAS loop without plain reads is not a good idea
on many targets and wasn't used by one. Thus there is now no option to
do so.
Architectures are now using the generic spinlock automatically if they
do not provide an own implementation. Thus the pthread_spin_lock.c files
in sysdeps folder are deleted.
ChangeLog:
* NEWS: Mention new spinlock implementation.
* include/atomic.h:
(__atomic_val_bysize): Cast type to omit volatile qualifier.
(atomic_exchange_acq): Likewise.
(atomic_load_relaxed): Likewise.
(ATOMIC_EXCHANGE_USES_CAS): Check definition.
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros.
* nptl/pthread_spin_trylock.c (pthread_spin_trylock):
Likewise.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
* sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/arm/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/hppa/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/m68k/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/microblaze/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/mips/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/nios2/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/aarch64/atomic-machine.h (ATOMIC_EXCHANGE_USES_CAS): Define.
* sysdeps/alpha/atomic-machine.h: Likewise.
* sysdeps/arm/atomic-machine.h: Likewise.
* sysdeps/i386/atomic-machine.h: Likewise.
* sysdeps/ia64/atomic-machine.h: Likewise.
* sysdeps/m68k/coldfire/atomic-machine.h: Likewise.
* sysdeps/m68k/m680x0/m68020/atomic-machine.h: Likewise.
* sysdeps/microblaze/atomic-machine.h: Likewise.
* sysdeps/mips/atomic-machine.h: Likewise.
* sysdeps/powerpc/powerpc32/atomic-machine.h: Likewise.
* sysdeps/powerpc/powerpc64/atomic-machine.h: Likewise.
* sysdeps/s390/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc32/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc32/sparcv9/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc64/atomic-machine.h: Likewise.
* sysdeps/tile/tilegx/atomic-machine.h: Likewise.
* sysdeps/tile/tilepro/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/hppa/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/nios2/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/sh/atomic-machine.h: Likewise.
* sysdeps/x86_64/atomic-machine.h: Likewise.
---
NEWS | 11 ++++
include/atomic.h | 17 ++++--
nptl/pthread_spin_init.c | 3 +-
nptl/pthread_spin_lock.c | 71 +++++++++++++---------
nptl/pthread_spin_trylock.c | 54 +++++++++++++++-
nptl/pthread_spin_unlock.c | 6 +-
sysdeps/aarch64/atomic-machine.h | 1 +
sysdeps/aarch64/nptl/pthread_spin_lock.c | 24 --------
sysdeps/alpha/atomic-machine.h | 1 +
sysdeps/arm/atomic-machine.h | 1 +
sysdeps/arm/nptl/pthread_spin_lock.c | 23 -------
sysdeps/hppa/nptl/pthread_spin_lock.c | 23 -------
sysdeps/i386/atomic-machine.h | 1 +
sysdeps/ia64/atomic-machine.h | 1 +
sysdeps/m68k/coldfire/atomic-machine.h | 1 +
sysdeps/m68k/m680x0/m68020/atomic-machine.h | 1 +
sysdeps/m68k/nptl/pthread_spin_lock.c | 24 --------
sysdeps/microblaze/atomic-machine.h | 1 +
sysdeps/microblaze/nptl/pthread_spin_lock.c | 24 --------
sysdeps/mips/atomic-machine.h | 2 +
sysdeps/mips/nptl/pthread_spin_lock.c | 23 -------
sysdeps/nios2/nptl/pthread_spin_lock.c | 24 --------
sysdeps/powerpc/powerpc32/atomic-machine.h | 1 +
sysdeps/powerpc/powerpc64/atomic-machine.h | 1 +
sysdeps/s390/atomic-machine.h | 2 +
sysdeps/sparc/sparc32/atomic-machine.h | 1 +
sysdeps/sparc/sparc32/sparcv9/atomic-machine.h | 1 +
sysdeps/sparc/sparc64/atomic-machine.h | 1 +
sysdeps/tile/tilegx/atomic-machine.h | 1 +
sysdeps/tile/tilepro/atomic-machine.h | 1 +
sysdeps/unix/sysv/linux/hppa/atomic-machine.h | 1 +
.../unix/sysv/linux/m68k/coldfire/atomic-machine.h | 1 +
sysdeps/unix/sysv/linux/nios2/atomic-machine.h | 1 +
sysdeps/unix/sysv/linux/sh/atomic-machine.h | 1 +
sysdeps/x86_64/atomic-machine.h | 1 +
35 files changed, 148 insertions(+), 203 deletions(-)
delete mode 100644 sysdeps/aarch64/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/arm/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/hppa/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/m68k/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/microblaze/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/mips/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/nios2/nptl/pthread_spin_lock.c
diff --git a/NEWS b/NEWS
index 3590878..e6702ad 100644
--- a/NEWS
+++ b/NEWS
@@ -41,6 +41,17 @@ Version 2.26
"The Rules of Hungarian Orthography, 12th edition" and the work of
Egmont Koblinger (Bug 18934).
+* The synchronization that pthread_spin_unlock performs has been changed
+ to now be equivalent to a C11 atomic store with release memory order to
+ the spin lock's memory location. This ensures correct synchronization
+ for the spin lock's operations and critical sections protected by a spin
+ lock. Previously, several (but not all) architectures used stronger
+ synchronization (e.g., containing what is often called a full barrier).
+ This change can improve performance, but may affect odd fringe uses of
+ spin locks that depend on the previous behavior (e.g., using spin locks
+ as atomic variables to try to implement Dekker's mutual exclusion
+ algorithm).
+
Security related changes:
[Add security related changes here]
diff --git a/include/atomic.h b/include/atomic.h
index 7f32640..0d1e42e 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -54,7 +54,7 @@
and following args. */
#define __atomic_val_bysize(pre, post, mem, ...) \
({ \
- __typeof (*mem) __atg1_result; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
if (sizeof (*mem) == 1) \
__atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
else if (sizeof (*mem) == 2) \
@@ -162,9 +162,9 @@
/* Store NEWVALUE in *MEM and return the old value. */
#ifndef atomic_exchange_acq
# define atomic_exchange_acq(mem, newvalue) \
- ({ __typeof (*(mem)) __atg5_oldval; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
__typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
\
do \
__atg5_oldval = *__atg5_memp; \
@@ -668,7 +668,7 @@ void __atomic_link_error (void);
# ifndef atomic_load_relaxed
# define atomic_load_relaxed(mem) \
- ({ __typeof (*(mem)) __atg100_val; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
__asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
__atg100_val; })
# endif
@@ -818,4 +818,13 @@ void __atomic_link_error (void);
# define atomic_spin_nop() do { /* nothing */ } while (0)
#endif
+/* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
+ are implemented based on a CAS loop; otherwise, this is 0 and we assume
+ that the atomic_exchange operations could provide better performance
+ than a CAS loop. */
+#if ! defined ATOMIC_EXCHANGE_USES_CAS || ! (ATOMIC_EXCHANGE_USES_CAS == 0 \
+ || ATOMIC_EXCHANGE_USES_CAS == 1)
+# error ATOMIC_EXCHANGE_USES_CAS has to be defined to 0 or 1
+#endif
+
#endif /* atomic.h */
diff --git a/nptl/pthread_spin_init.c b/nptl/pthread_spin_init.c
index 01dec5e..fe30913 100644
--- a/nptl/pthread_spin_init.c
+++ b/nptl/pthread_spin_init.c
@@ -22,6 +22,7 @@
int
pthread_spin_init (pthread_spinlock_t *lock, int pshared)
{
- *lock = 0;
+ /* Relaxed MO is fine because this is an initializing store. */
+ atomic_store_relaxed (lock, 0);
return 0;
}
diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
index 4d03b78..682af80 100644
--- a/nptl/pthread_spin_lock.c
+++ b/nptl/pthread_spin_lock.c
@@ -19,27 +19,35 @@
#include <atomic.h>
#include "pthreadP.h"
-/* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
- to the number of plain reads that it's optimal to spin on between uses
- of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
- then use -1. If no plain reads here would ever be optimal, use 0. */
-#ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
-# warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
-# define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-#endif
-
int
pthread_spin_lock (pthread_spinlock_t *lock)
{
- /* atomic_exchange usually takes less instructions than
- atomic_compare_and_exchange. On the other hand,
- atomic_compare_and_exchange potentially generates less bus traffic
- when the lock is locked.
- We assume that the first try mostly will be successful, and we use
- atomic_exchange. For the subsequent tries we use
- atomic_compare_and_exchange. */
- if (atomic_exchange_acq (lock, 1) == 0)
+ int val = 0;
+
+ /* We assume that the first try mostly will be successful, thus we use
+ atomic_exchange if it is not implemented by a CAS loop (we also assume
+ that atomic_exchange can be faster if it succeeds, see
+ ATOMIC_EXCHANGE_USES_CAS). Otherwise, we use a weak CAS and not an
+ exchange so we bail out after the first failed attempt to change the
+ state. For the subsequent attempts we use atomic_compare_and_exchange
+ after we observe that the lock is not acquired.
+ See also comment in pthread_spin_trylock.
+ We use acquire MO to synchronize-with the release MO store in
+ pthread_spin_unlock, and thus ensure that prior critical sections
+ happen-before this critical section. */
+#if ! ATOMIC_EXCHANGE_USES_CAS
+ /* Try to acquire the lock with an exchange instruction as this architecture
+ has such an instruction and we assume it is faster than a CAS.
+ The acquisition succeeds if the lock is not in an acquired state. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
return 0;
+#else
+ /* Try to acquire the lock with a CAS instruction as this architecture
+ has no exchange instruction. The acquisition succeeds if the lock is not
+ acquired. */
+ if (__glibc_likely (atomic_compare_exchange_weak_acquire (lock, &val, 1)))
+ return 0;
+#endif
do
{
@@ -47,23 +55,26 @@ pthread_spin_lock (pthread_spinlock_t *lock)
to cmpxchg is not a good idea on many targets as that will force
expensive memory synchronizations among processors and penalize other
running threads.
- On the other hand, we do want to update memory state on the local core
- once in a while to avoid spinning indefinitely until some event that
- will happen to update local memory as a side-effect. */
- if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
+ There is no technical reason for throwing in a CAS every now and then,
+ and so far we have no evidence that it can improve performance.
+ If that would be the case, we have to adjust other spin-waiting loops
+ elsewhere, too!
+ Thus we use relaxed MO reads until we observe the lock to not be
+ acquired anymore. */
+ do
{
- int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
+ /* TODO Back-off. */
- while (*lock != 0 && wait > 0)
- --wait;
- }
- else
- {
- while (*lock != 0)
- ;
+ atomic_spin_nop ();
+
+ val = atomic_load_relaxed (lock);
}
+ while (val != 0);
+
+ /* We need acquire memory order here for the same reason as mentioned
+ for the first try to lock the spinlock. */
}
- while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
+ while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
return 0;
}
diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
index 593bba3..83921b0 100644
--- a/nptl/pthread_spin_trylock.c
+++ b/nptl/pthread_spin_trylock.c
@@ -23,5 +23,57 @@
int
pthread_spin_trylock (pthread_spinlock_t *lock)
{
- return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
+ /* For the spin try lock, we have the following possibilities:
+
+ 1) If we assume that trylock will most likely succeed in practice:
+ * We just do an exchange.
+
+ 2) If we want to bias towards cases where trylock succeeds, but don't
+ rule out contention:
+ * If exchange is not implemented by a CAS loop, and exchange is faster
+ than CAS, do an exchange.
+ * If exchange is implemented by a CAS loop, use a weak CAS and not an
+ exchange so we bail out after the first failed attempt to change the state.
+
+ 3) If we expect contention to be likely:
+ * If CAS always brings the cache line into an exclusive state even if the
+ spinlock is already acquired, then load the value first with
+ atomic_load_relaxed and test if lock is not acquired. Then do 2).
+
+ We assume that 2) is the common case, and that this won't be slower than
+ 1) in the common case.
+
+ We use acquire MO to synchronize-with the release MO store in
+ pthread_spin_unlock, and thus ensure that prior critical sections
+ happen-before this critical section. */
+#if ! ATOMIC_EXCHANGE_USES_CAS
+ /* Try to acquire the lock with an exchange instruction as this architecture
+ has such an instruction and we assume it is faster than a CAS.
+ The acquisition succeeds if the lock is not in an acquired state. */
+ if (atomic_exchange_acquire (lock, 1) == 0)
+ return 0;
+#else
+ /* Try to acquire the lock with a CAS instruction as this architecture
+ has no exchange instruction. The acquisition succeeds if the lock is not
+ acquired. */
+ do
+ {
+ int val = 0;
+ if (atomic_compare_exchange_weak_acquire (lock, &val, 1))
+ return 0;
+ }
+ /* atomic_compare_exchange_weak_acquire can fail spuriously. Whereas
+ C++11 and C11 make it clear that trylock operations can fail spuriously,
+ POSIX does not explicitly specify this; it only specifies that failing
+ synchronization operations do not need to have synchronization effects
+ themselves, but a spurious failure is something that could contradict a
+ happens-before established earlier (e.g., that we need to observe that
+ the lock is acquired). Therefore, we emulate a strong CAS by simply
+ checking with a relaxed MO load that the lock is really acquired before
+ returning EBUSY; the additional overhead this may cause is on the slow
+ path. */
+ while (atomic_load_relaxed (lock) == 0);
+#endif
+
+ return EBUSY;
}
diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
index 5fd73e5..f83b696 100644
--- a/nptl/pthread_spin_unlock.c
+++ b/nptl/pthread_spin_unlock.c
@@ -23,7 +23,9 @@
int
pthread_spin_unlock (pthread_spinlock_t *lock)
{
- atomic_full_barrier ();
- *lock = 0;
+ /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
+ or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
+ pthread_spin_trylock. */
+ atomic_store_release (lock, 0);
return 0;
}
diff --git a/sysdeps/aarch64/atomic-machine.h b/sysdeps/aarch64/atomic-machine.h
index a5d2213..eb59a5b 100644
--- a/sysdeps/aarch64/atomic-machine.h
+++ b/sysdeps/aarch64/atomic-machine.h
@@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 1
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange succesful. */
diff --git a/sysdeps/aarch64/nptl/pthread_spin_lock.c b/sysdeps/aarch64/nptl/pthread_spin_lock.c
deleted file mode 100644
index fcfcb40..0000000
--- a/sysdeps/aarch64/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
-
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public License as
- published by the Free Software Foundation; either version 2.1 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/alpha/atomic-machine.h b/sysdeps/alpha/atomic-machine.h
index 06e93f2..f710606 100644
--- a/sysdeps/alpha/atomic-machine.h
+++ b/sysdeps/alpha/atomic-machine.h
@@ -44,6 +44,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
#ifdef UP
diff --git a/sysdeps/arm/atomic-machine.h b/sysdeps/arm/atomic-machine.h
index eeac7f0..c22d05b 100644
--- a/sysdeps/arm/atomic-machine.h
+++ b/sysdeps/arm/atomic-machine.h
@@ -35,6 +35,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
void __arm_link_error (void);
diff --git a/sysdeps/arm/nptl/pthread_spin_lock.c b/sysdeps/arm/nptl/pthread_spin_lock.c
deleted file mode 100644
index 037b3b8..0000000
--- a/sysdeps/arm/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/hppa/nptl/pthread_spin_lock.c b/sysdeps/hppa/nptl/pthread_spin_lock.c
deleted file mode 100644
index 14f36a6..0000000
--- a/sysdeps/hppa/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2005-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/i386/atomic-machine.h b/sysdeps/i386/atomic-machine.h
index 77759f7..0e24200 100644
--- a/sysdeps/i386/atomic-machine.h
+++ b/sysdeps/i386/atomic-machine.h
@@ -56,6 +56,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
diff --git a/sysdeps/ia64/atomic-machine.h b/sysdeps/ia64/atomic-machine.h
index ecf9750..971084e 100644
--- a/sysdeps/ia64/atomic-machine.h
+++ b/sysdeps/ia64/atomic-machine.h
@@ -45,6 +45,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
diff --git a/sysdeps/m68k/coldfire/atomic-machine.h b/sysdeps/m68k/coldfire/atomic-machine.h
index 9aeb993..72b037e 100644
--- a/sysdeps/m68k/coldfire/atomic-machine.h
+++ b/sysdeps/m68k/coldfire/atomic-machine.h
@@ -52,6 +52,7 @@ typedef uintmax_t uatomic_max_t;
/* If we have just non-atomic operations, we can as well make them wide. */
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* The only basic operation needed is compare and exchange. */
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
diff --git a/sysdeps/m68k/m680x0/m68020/atomic-machine.h b/sysdeps/m68k/m680x0/m68020/atomic-machine.h
index 00dc22d..a319471 100644
--- a/sysdeps/m68k/m680x0/m68020/atomic-machine.h
+++ b/sysdeps/m68k/m680x0/m68020/atomic-machine.h
@@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
({ __typeof (*(mem)) __ret; \
diff --git a/sysdeps/m68k/nptl/pthread_spin_lock.c b/sysdeps/m68k/nptl/pthread_spin_lock.c
deleted file mode 100644
index 62795f4..0000000
--- a/sysdeps/m68k/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2010-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Maxim Kuvyrkov <maxim@codesourcery.com>, 2010.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/microblaze/atomic-machine.h b/sysdeps/microblaze/atomic-machine.h
index dc5309c..49315c6 100644
--- a/sysdeps/microblaze/atomic-machine.h
+++ b/sysdeps/microblaze/atomic-machine.h
@@ -37,6 +37,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* Microblaze does not have byte and halfword forms of load and reserve and
diff --git a/sysdeps/microblaze/nptl/pthread_spin_lock.c b/sysdeps/microblaze/nptl/pthread_spin_lock.c
deleted file mode 100644
index fcfcb40..0000000
--- a/sysdeps/microblaze/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
-
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public License as
- published by the Free Software Foundation; either version 2.1 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h
index 54c182b..3d9da0c 100644
--- a/sysdeps/mips/atomic-machine.h
+++ b/sysdeps/mips/atomic-machine.h
@@ -50,6 +50,8 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#endif
+#define ATOMIC_EXCHANGE_USES_CAS 0
+
/* See the comments in <sys/asm.h> about the use of the sync instruction. */
#ifndef MIPS_SYNC
# define MIPS_SYNC sync
diff --git a/sysdeps/mips/nptl/pthread_spin_lock.c b/sysdeps/mips/nptl/pthread_spin_lock.c
deleted file mode 100644
index 19d87a5..0000000
--- a/sysdeps/mips/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2012-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/nios2/nptl/pthread_spin_lock.c b/sysdeps/nios2/nptl/pthread_spin_lock.c
deleted file mode 100644
index b203469..0000000
--- a/sysdeps/nios2/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* pthread spin-lock implementation for Nios II.
- Copyright (C) 2005-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/powerpc32/atomic-machine.h
index 20d5e85..96c7d81 100644
--- a/sysdeps/powerpc/powerpc32/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc32/atomic-machine.h
@@ -35,6 +35,7 @@
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/*
* The 32-bit exchange_bool is different on powerpc64 because the subf
diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h
index 40c308e..46df488 100644
--- a/sysdeps/powerpc/powerpc64/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc64/atomic-machine.h
@@ -35,6 +35,7 @@
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* The 32-bit exchange_bool is different on powerpc64 because the subf
does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
diff --git a/sysdeps/s390/atomic-machine.h b/sysdeps/s390/atomic-machine.h
index 690d2e3..adaca40 100644
--- a/sysdeps/s390/atomic-machine.h
+++ b/sysdeps/s390/atomic-machine.h
@@ -67,6 +67,8 @@ typedef uintmax_t uatomic_max_t;
# define __HAVE_64B_ATOMICS 0
#endif
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* Implement some of the non-C11 atomic macros from include/atomic.h
with help of the C11 atomic builtins. The other non-C11 atomic macros
are using the macros defined here. */
diff --git a/sysdeps/sparc/sparc32/atomic-machine.h b/sysdeps/sparc/sparc32/atomic-machine.h
index acd029e..5950131 100644
--- a/sysdeps/sparc/sparc32/atomic-machine.h
+++ b/sysdeps/sparc/sparc32/atomic-machine.h
@@ -49,6 +49,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* We have no compare and swap, just test and set.
diff --git a/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h b/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
index 7f7895e..07e67e6 100644
--- a/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
+++ b/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
@@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
diff --git a/sysdeps/sparc/sparc64/atomic-machine.h b/sysdeps/sparc/sparc64/atomic-machine.h
index 44a43ff..d3d95e3 100644
--- a/sysdeps/sparc/sparc64/atomic-machine.h
+++ b/sysdeps/sparc/sparc64/atomic-machine.h
@@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
diff --git a/sysdeps/tile/tilegx/atomic-machine.h b/sysdeps/tile/tilegx/atomic-machine.h
index 6345251..e77f670 100644
--- a/sysdeps/tile/tilegx/atomic-machine.h
+++ b/sysdeps/tile/tilegx/atomic-machine.h
@@ -31,6 +31,7 @@
#endif
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* Pick appropriate 8- or 4-byte instruction. */
#define __atomic_update(mem, v, op) \
diff --git a/sysdeps/tile/tilepro/atomic-machine.h b/sysdeps/tile/tilepro/atomic-machine.h
index 33a8b85..45e36de 100644
--- a/sysdeps/tile/tilepro/atomic-machine.h
+++ b/sysdeps/tile/tilepro/atomic-machine.h
@@ -23,6 +23,7 @@
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* 32-bit integer compare-and-exchange. */
static __inline __attribute__ ((always_inline))
diff --git a/sysdeps/unix/sysv/linux/hppa/atomic-machine.h b/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
index 2cd2235..9adcab7 100644
--- a/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
@@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* prev = *addr;
if (prev == old)
diff --git a/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h b/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
index 6755a05..c1b6950 100644
--- a/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
@@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* The only basic operation needed is compare and exchange. */
/* For ColdFire we'll have to trap into the kernel mode anyway,
diff --git a/sysdeps/unix/sysv/linux/nios2/atomic-machine.h b/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
index 6111ccf..d98fa66 100644
--- a/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
@@ -33,6 +33,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
diff --git a/sysdeps/unix/sysv/linux/sh/atomic-machine.h b/sysdeps/unix/sysv/linux/sh/atomic-machine.h
index 3c58b70..428b71e 100644
--- a/sysdeps/unix/sysv/linux/sh/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/sh/atomic-machine.h
@@ -46,6 +46,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* SH kernel has implemented a gUSA ("g" User Space Atomicity) support
for the user space atomicity. The atomicity macros use this scheme.
diff --git a/sysdeps/x86_64/atomic-machine.h b/sysdeps/x86_64/atomic-machine.h
index 2e8a9aa..c454734 100644
--- a/sysdeps/x86_64/atomic-machine.h
+++ b/sysdeps/x86_64/atomic-machine.h
@@ -59,6 +59,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 1
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
__sync_val_compare_and_swap (mem, oldval, newval)
--
2.7.4
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-07 16:23 ` Stefan Liebler
@ 2017-04-09 13:51 ` Torvald Riegel
2017-04-10 12:00 ` Stefan Liebler
2017-04-10 8:17 ` [PATCH 1/2] " Andreas Schwab
2017-05-30 21:00 ` Tulio Magno Quites Machado Filho
2 siblings, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-04-09 13:51 UTC (permalink / raw)
To: Stefan Liebler
Cc: libc-alpha, szabolcs.nagy, marcus.shawcroft, pb, Joseph S. Myers,
rth, Carlos O'Donell, vapier, schwab, cmetcalf, david,
chunglin_tang, munroesj, davem
On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
> On 04/06/2017 04:00 PM, Torvald Riegel wrote:
> > Otherwise, this patch looks good to me.
> Thanks for review. Here is an updated patch. I've changed the comments
> and added the POSIX requirement in pthread_spin_trylock.
I assume that this means that you have taken care of all the review
comments I have and changed nothing else; thus, I won't review this in
detail again. (If there have been other changes, please let me know so
that I can look at them specifically.)
> @architecture maintainers:
> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
> specific atomic-machine.h files.
> See comment in include/atomic.h:
> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
> are implemented based on a CAS loop; otherwise, this is 0 and we assume
> that the atomic_exchange operations could provide better performance
> than a CAS loop. */
>
> Can review the definition to 0 or 1 in the atomic-machine.h file of your
> architecture, please?
I think we primarily need feedback from the maintainers of the
architectures where we're not quite sure. Let's see how responsive
everyone is and then decide whether we need to continue pinging some of
them potentially or whether we have enough information to be able to
commit the patch.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-07 16:23 ` Stefan Liebler
2017-04-09 13:51 ` Torvald Riegel
@ 2017-04-10 8:17 ` Andreas Schwab
2017-04-10 12:00 ` Stefan Liebler
2017-05-30 21:00 ` Tulio Magno Quites Machado Filho
2 siblings, 1 reply; 63+ messages in thread
From: Andreas Schwab @ 2017-04-10 8:17 UTC (permalink / raw)
To: Stefan Liebler
Cc: libc-alpha, szabolcs.nagy, marcus.shawcroft, pb, Joseph S. Myers,
rth, Carlos O'Donell, vapier, cmetcalf, david, chunglin_tang,
munroesj, davem
On Apr 07 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
Why 1 exactly, and not just non-zero?
Andreas.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-09 13:51 ` Torvald Riegel
@ 2017-04-10 12:00 ` Stefan Liebler
2017-04-18 13:09 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-04-10 12:00 UTC (permalink / raw)
To: libc-alpha
On 04/09/2017 03:51 PM, Torvald Riegel wrote:
> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>> On 04/06/2017 04:00 PM, Torvald Riegel wrote:
>>> Otherwise, this patch looks good to me.
>> Thanks for review. Here is an updated patch. I've changed the comments
>> and added the POSIX requirement in pthread_spin_trylock.
>
> I assume that this means that you have taken care of all the review
> comments I have and changed nothing else; thus, I won't review this in
> detail again. (If there have been other changes, please let me know so
> that I can look at them specifically.)
>
Yes, I have taken care of all the review comments and changed nothing else.
>> @architecture maintainers:
>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>> specific atomic-machine.h files.
>> See comment in include/atomic.h:
>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
>> are implemented based on a CAS loop; otherwise, this is 0 and we assume
>> that the atomic_exchange operations could provide better performance
>> than a CAS loop. */
>>
>> Can review the definition to 0 or 1 in the atomic-machine.h file of your
>> architecture, please?
>
> I think we primarily need feedback from the maintainers of the
> architectures where we're not quite sure. Let's see how responsive
> everyone is and then decide whether we need to continue pinging some of
> them potentially or whether we have enough information to be able to
> commit the patch.
>
Okay.
Chris has already replied directly to me.
On 04/07/2017 06:50 PM, Chris Metcalf wrote:
> Thanks, looks good for tilegx/tilepro.
Bye
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-10 8:17 ` [PATCH 1/2] " Andreas Schwab
@ 2017-04-10 12:00 ` Stefan Liebler
2017-04-10 13:36 ` Andreas Schwab
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-04-10 12:00 UTC (permalink / raw)
To: libc-alpha
On 04/10/2017 10:17 AM, Andreas Schwab wrote:
> On Apr 07 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
>
>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
>
> Why 1 exactly, and not just non-zero?
>
> Andreas.
>
This points out that there is only a true/false choice and
all architectures have to define it.
__HAVE_64B_ATOMICS is used in the same way.
/* This is equal to 1 iff the architecture supports 64b atomic
operations. */
Bye
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-10 12:00 ` Stefan Liebler
@ 2017-04-10 13:36 ` Andreas Schwab
2017-04-11 7:06 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Andreas Schwab @ 2017-04-10 13:36 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Apr 10 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
> On 04/10/2017 10:17 AM, Andreas Schwab wrote:
>> On Apr 07 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
>>
>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
>>
>> Why 1 exactly, and not just non-zero?
>>
>> Andreas.
>>
>
> This points out that there is only a true/false choice and
> all architectures have to define it.
That doesn't answer my question. Why do you need the dance of checking
for 1 explicitly?
Andreas.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-10 13:36 ` Andreas Schwab
@ 2017-04-11 7:06 ` Stefan Liebler
2017-04-11 8:45 ` Andreas Schwab
2017-04-13 16:36 ` Torvald Riegel
0 siblings, 2 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-04-11 7:06 UTC (permalink / raw)
To: libc-alpha
On 04/10/2017 03:36 PM, Andreas Schwab wrote:
> On Apr 10 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
>
>> On 04/10/2017 10:17 AM, Andreas Schwab wrote:
>>> On Apr 07 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
>>>
>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
>>>
>>> Why 1 exactly, and not just non-zero?
>>>
>>> Andreas.
>>>
>>
>> This points out that there is only a true/false choice and
>> all architectures have to define it.
>
> That doesn't answer my question. Why do you need the dance of checking
> for 1 explicitly?
>
> Andreas.
>
At the moment there is only a choice between 0 and 1.
The check ensures that ATOMIC_EXCHANGE_USES_CAS is defined and it has a
specific value.
If someone defines it to another value, he will get an error here.
Then the check and the comment is hopefully updated, too.
__HAVE_64B_ATOMICS has to be 0 or 1, but it is not checked explicitly.
Here are some users of it:
./nptl/sem_waitcommon.c:81:#if !__HAVE_64B_ATOMICS
./nptl/sem_waitcommon.c:91:#if __HAVE_64B_ATOMICS
./nptl/pthread_cond_common.c:26:#if __HAVE_64B_ATOMICS == 1
./nptl/pthread_cond_common.c:59:#else
./nptl/pthread_cond_common.c:245:#endif /* !__HAVE_64B_ATOMICS */
...
If someone defines __HAVE_64B_ATOMICS to 2, build/test will fail with
some unspecified error.
If someone defines ATOMIC_EXCHANGE_USES_CAS to 2, build fails with
"ATOMIC_EXCHANGE_USES_CAS has to be defined to 0 or 1".
But you are right, zero or non-zero is fine, too.
My latest patch is only using:
#if ! ATOMIC_EXCHANGE_USES_CAS
#else
#endif
But perhaps #if ATOMIC_EXCHANGE_USES_CAS == 1 will be introduced by a
future patch.
Bye
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-11 7:06 ` Stefan Liebler
@ 2017-04-11 8:45 ` Andreas Schwab
2017-04-11 10:15 ` Stefan Liebler
2017-04-13 16:36 ` Torvald Riegel
1 sibling, 1 reply; 63+ messages in thread
From: Andreas Schwab @ 2017-04-11 8:45 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Apr 11 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
> But perhaps #if ATOMIC_EXCHANGE_USES_CAS == 1 will be introduced by a
> future patch.
Why would anyone want to do that?
Andreas.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-11 8:45 ` Andreas Schwab
@ 2017-04-11 10:15 ` Stefan Liebler
2017-04-11 12:05 ` Andreas Schwab
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-04-11 10:15 UTC (permalink / raw)
To: libc-alpha
On 04/11/2017 10:45 AM, Andreas Schwab wrote:
> On Apr 11 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
>
>> But perhaps #if ATOMIC_EXCHANGE_USES_CAS == 1 will be introduced by a
>> future patch.
>
> Why would anyone want to do that?
>
> Andreas.
>
By accident!?
It happened in the case of __HAVE_64B_ATOMICS.
Bye
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-11 10:15 ` Stefan Liebler
@ 2017-04-11 12:05 ` Andreas Schwab
2017-04-11 12:19 ` Stefan Liebler
2017-04-11 13:08 ` Zack Weinberg
0 siblings, 2 replies; 63+ messages in thread
From: Andreas Schwab @ 2017-04-11 12:05 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Apr 11 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
> It happened in the case of __HAVE_64B_ATOMICS.
We shouldn't follow a bad example.
Andreas.
--
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-11 12:05 ` Andreas Schwab
@ 2017-04-11 12:19 ` Stefan Liebler
2017-04-11 13:08 ` Zack Weinberg
1 sibling, 0 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-04-11 12:19 UTC (permalink / raw)
To: libc-alpha
On 04/11/2017 02:05 PM, Andreas Schwab wrote:
> On Apr 11 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
>
>> It happened in the case of __HAVE_64B_ATOMICS.
>
> We shouldn't follow a bad example.
>
> Andreas.
>
Then I'll change the check to:
/* ATOMIC_EXCHANGE_USES_CAS is non-zero if atomic_exchange operations
are implemented based on a CAS loop; otherwise, this is zero and we
assume
that the atomic_exchange operations could provide better performance
than a CAS loop. */
#ifndef ATOMIC_EXCHANGE_USES_CAS
# error ATOMIC_EXCHANGE_USES_CAS has to be defined.
#endif
Bye
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-11 12:05 ` Andreas Schwab
2017-04-11 12:19 ` Stefan Liebler
@ 2017-04-11 13:08 ` Zack Weinberg
1 sibling, 0 replies; 63+ messages in thread
From: Zack Weinberg @ 2017-04-11 13:08 UTC (permalink / raw)
To: Andreas Schwab; +Cc: Stefan Liebler, GNU C Library
On Tue, Apr 11, 2017 at 8:05 AM, Andreas Schwab <schwab@suse.de> wrote:
> On Apr 11 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
>> It happened in the case of __HAVE_64B_ATOMICS.
>
> We shouldn't follow a bad example.
How about you propose a patch to fix __HAVE_64B_ATOMICS the way you
think it should be, Andreas, since you're making such a fuss about
this?
zw
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-11 7:06 ` Stefan Liebler
2017-04-11 8:45 ` Andreas Schwab
@ 2017-04-13 16:36 ` Torvald Riegel
1 sibling, 0 replies; 63+ messages in thread
From: Torvald Riegel @ 2017-04-13 16:36 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Tue, 2017-04-11 at 09:06 +0200, Stefan Liebler wrote:
> On 04/10/2017 03:36 PM, Andreas Schwab wrote:
> > On Apr 10 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
> >
> >> On 04/10/2017 10:17 AM, Andreas Schwab wrote:
> >>> On Apr 07 2017, Stefan Liebler <stli@linux.vnet.ibm.com> wrote:
> >>>
> >>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
> >>>
> >>> Why 1 exactly, and not just non-zero?
> >>>
> >>> Andreas.
> >>>
> >>
> >> This points out that there is only a true/false choice and
> >> all architectures have to define it.
> >
> > That doesn't answer my question. Why do you need the dance of checking
> > for 1 explicitly?
> >
> > Andreas.
> >
> At the moment there is only a choice between 0 and 1.
This is fine. There is no reason to allow a different value even if
this is just a boolean.
> The check ensures that ATOMIC_EXCHANGE_USES_CAS is defined and it has a
> specific value.
> If someone defines it to another value, he will get an error here.
> Then the check and the comment is hopefully updated, too.
The comments make it clear that it has to be 0 or 1, and can be used
without explicitly checking the value.
We can add the explicit check once, as you did in atomic.h, but I don't
think it's neither required nor a bad thing to do.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-10 12:00 ` Stefan Liebler
@ 2017-04-18 13:09 ` Stefan Liebler
2017-04-25 6:47 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-04-18 13:09 UTC (permalink / raw)
To: libc-alpha
On 04/10/2017 01:59 PM, Stefan Liebler wrote:
> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>>> @architecture maintainers:
>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>>> specific atomic-machine.h files.
>>> See comment in include/atomic.h:
>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
>>> are implemented based on a CAS loop; otherwise, this is 0 and we
>>> assume
>>> that the atomic_exchange operations could provide better performance
>>> than a CAS loop. */
>>>
>>> Can review the definition to 0 or 1 in the atomic-machine.h file of your
>>> architecture, please?
PING
>>
>> I think we primarily need feedback from the maintainers of the
>> architectures where we're not quite sure. Let's see how responsive
>> everyone is and then decide whether we need to continue pinging some of
>> them potentially or whether we have enough information to be able to
>> commit the patch.
>>
> Okay.
>
> Chris has already replied directly to me.
> On 04/07/2017 06:50 PM, Chris Metcalf wrote:
>> Thanks, looks good for tilegx/tilepro.
>
> Bye
> Stefan
>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-06 14:00 ` Torvald Riegel
2017-04-07 16:23 ` Stefan Liebler
@ 2017-04-18 21:17 ` Joseph Myers
2017-04-19 8:27 ` Stefan Liebler
1 sibling, 1 reply; 63+ messages in thread
From: Joseph Myers @ 2017-04-18 21:17 UTC (permalink / raw)
To: Torvald Riegel; +Cc: Stefan Liebler, libc-alpha
On Thu, 6 Apr 2017, Torvald Riegel wrote:
> Have you been actually looking at these? The next line in the file is a
> pretty obvious hint that this is an LLSC machine, and atomic_exchange
> isn't defined anywhere:
>
> > /* Microblaze does not have byte and halfword forms of load and reserve and
> > diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h
> > index 54c182b..3d9da0c 100644
> > --- a/sysdeps/mips/atomic-machine.h
> >
> > +++ b/sysdeps/mips/atomic-machine.h
> >
> > @@ -50,6 +50,8 @@ typedef uintmax_t uatomic_max_t;
> > #define __HAVE_64B_ATOMICS 1
> > #endif
> >
> > +#define ATOMIC_EXCHANGE_USES_CAS 0
> >
> > +
>
> Please ask the MIPS maintainers to review this.
MIPS is an LLSC machine. However, XLP has a direct atomic exchange
instruction (so that will be used if _MIPS_ARCH_XLP is defined, in the
case where this header is using compiler builtins).
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-18 21:17 ` Joseph Myers
@ 2017-04-19 8:27 ` Stefan Liebler
0 siblings, 0 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-04-19 8:27 UTC (permalink / raw)
To: libc-alpha
On 04/18/2017 11:17 PM, Joseph Myers wrote:
> On Thu, 6 Apr 2017, Torvald Riegel wrote:
>
>> Have you been actually looking at these? The next line in the file is a
>> pretty obvious hint that this is an LLSC machine, and atomic_exchange
>> isn't defined anywhere:
>>
>>> /* Microblaze does not have byte and halfword forms of load and reserve and
>>> diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h
>>> index 54c182b..3d9da0c 100644
>>> --- a/sysdeps/mips/atomic-machine.h
>>>
>>> +++ b/sysdeps/mips/atomic-machine.h
>>>
>>> @@ -50,6 +50,8 @@ typedef uintmax_t uatomic_max_t;
>>> #define __HAVE_64B_ATOMICS 1
>>> #endif
>>>
>>> +#define ATOMIC_EXCHANGE_USES_CAS 0
>>>
>>> +
>>
>> Please ask the MIPS maintainers to review this.
>
> MIPS is an LLSC machine. However, XLP has a direct atomic exchange
> instruction (so that will be used if _MIPS_ARCH_XLP is defined, in the
> case where this header is using compiler builtins).
>
Thanks for review.
I've changed the patch to:
--- a/sysdeps/mips/atomic-machine.h
+++ b/sysdeps/mips/atomic-machine.h
@@ -92,7 +92,15 @@ typedef uintmax_t uatomic_max_t;
have no assembly alternative available and want to avoid the __sync_*
builtins if at all possible. */
-#define USE_ATOMIC_COMPILER_BUILTINS 1
+# define USE_ATOMIC_COMPILER_BUILTINS 1
+
+/* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange
+ instruction which will be used by __atomic_exchange_n. */
+# ifdef _MIPS_ARCH_XLP
+# define ATOMIC_EXCHANGE_USES_CAS 0
+# else
+# define ATOMIC_EXCHANGE_USES_CAS 1
+# endif
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange succesful. */
@@ -213,7 +221,8 @@ typedef uintmax_t uatomic_max_t;
/* This implementation using inline assembly will be removed once glibc
requires GCC 4.8 or later to build. */
-#define USE_ATOMIC_COMPILER_BUILTINS 0
+# define USE_ATOMIC_COMPILER_BUILTINS 0
+# define ATOMIC_EXCHANGE_USES_CAS 1
/* Compare and exchange. For all of the "xxx" routines, we expect a
"__prev" and a "__cmp" variable to be provided by the enclosing scope,
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-18 13:09 ` Stefan Liebler
@ 2017-04-25 6:47 ` Stefan Liebler
2017-05-03 11:38 ` [PATCH 1/2] [PING] " Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-04-25 6:47 UTC (permalink / raw)
To: libc-alpha
Cc: davem, tuliom, chunglin_tang, david, schwab, vapier,
Carlos O'Donell, rth, pb, marcus.shawcroft, szabolcs.nagy
On 04/18/2017 03:09 PM, Stefan Liebler wrote:
> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>>>> @architecture maintainers:
>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>>>> specific atomic-machine.h files.
>>>> See comment in include/atomic.h:
>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
>>>> are implemented based on a CAS loop; otherwise, this is 0 and we
>>>> assume
>>>> that the atomic_exchange operations could provide better
>>>> performance
>>>> than a CAS loop. */
>>>>
>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
>>>> your
>>>> architecture, please?
>
>
> PING
>
PING
>
>>>
>>> I think we primarily need feedback from the maintainers of the
>>> architectures where we're not quite sure. Let's see how responsive
>>> everyone is and then decide whether we need to continue pinging some of
>>> them potentially or whether we have enough information to be able to
>>> commit the patch.
>>>
>> Okay.
>>
>> Chris has already replied directly to me.
>> On 04/07/2017 06:50 PM, Chris Metcalf wrote:
>>> Thanks, looks good for tilegx/tilepro.
>>
Andreas has answered regarding the explicit check of
ATOMIC_EXCHANGE_USES_CAS in include/atomic.h.
@Andreas: is m68k okay?
Joseph has replied for mips.
What about the other architectures? Is the definition of
ATOMIC_EXCHANGE_USES_CAS correct?
>> Bye
>> Stefan
>>
>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-25 6:47 ` Stefan Liebler
@ 2017-05-03 11:38 ` Stefan Liebler
2017-05-10 13:00 ` Stefan Liebler
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-05-03 11:38 UTC (permalink / raw)
To: libc-alpha
On 04/25/2017 08:46 AM, Stefan Liebler wrote:
> On 04/18/2017 03:09 PM, Stefan Liebler wrote:
>> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
>>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
>>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>>>>> @architecture maintainers:
>>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>>>>> specific atomic-machine.h files.
>>>>> See comment in include/atomic.h:
>>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange
>>>>> operations
>>>>> are implemented based on a CAS loop; otherwise, this is 0 and we
>>>>> assume
>>>>> that the atomic_exchange operations could provide better
>>>>> performance
>>>>> than a CAS loop. */
>>>>>
>>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
>>>>> your
>>>>> architecture, please?
>>
>>
>> PING
>>
> PING
PING
>>
>>>>
>>>> I think we primarily need feedback from the maintainers of the
>>>> architectures where we're not quite sure. Let's see how responsive
>>>> everyone is and then decide whether we need to continue pinging some of
>>>> them potentially or whether we have enough information to be able to
>>>> commit the patch.
>>>>
>>> Okay.
>>>
>>> Chris has already replied directly to me.
>>> On 04/07/2017 06:50 PM, Chris Metcalf wrote:
>>>> Thanks, looks good for tilegx/tilepro.
>>>
> Andreas has answered regarding the explicit check of
> ATOMIC_EXCHANGE_USES_CAS in include/atomic.h.
> @Andreas: is m68k okay?
>
> Joseph has replied for mips.
>
> What about the other architectures? Is the definition of
> ATOMIC_EXCHANGE_USES_CAS correct?
>
>>> Bye
>>> Stefan
>>>
>>
>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-05-03 11:38 ` [PATCH 1/2] [PING] " Stefan Liebler
@ 2017-05-10 13:00 ` Stefan Liebler
2017-05-17 13:09 ` Stefan Liebler
2017-05-30 7:18 ` Torvald Riegel
0 siblings, 2 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-05-10 13:00 UTC (permalink / raw)
To: libc-alpha; +Cc: Torvald Riegel
On 05/03/2017 01:38 PM, Stefan Liebler wrote:
> On 04/25/2017 08:46 AM, Stefan Liebler wrote:
>> On 04/18/2017 03:09 PM, Stefan Liebler wrote:
>>> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
>>>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
>>>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>>>>>> @architecture maintainers:
>>>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>>>>>> specific atomic-machine.h files.
>>>>>> See comment in include/atomic.h:
>>>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange
>>>>>> operations
>>>>>> are implemented based on a CAS loop; otherwise, this is 0 and we
>>>>>> assume
>>>>>> that the atomic_exchange operations could provide better
>>>>>> performance
>>>>>> than a CAS loop. */
>>>>>>
>>>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
>>>>>> your
>>>>>> architecture, please?
>>>
>>>
>>> PING
>>>
>> PING
>
> PING
PING
@Torvald:
I'm not sure if we will get answers from everybody.
What do you propose how to proceed with the definitions of
ATOMIC_EXCHANGE_USES_CAS?
>>>
>>>>>
>>>>> I think we primarily need feedback from the maintainers of the
>>>>> architectures where we're not quite sure. Let's see how responsive
>>>>> everyone is and then decide whether we need to continue pinging
>>>>> some of
>>>>> them potentially or whether we have enough information to be able to
>>>>> commit the patch.
>>>>>
>>>> Okay.
>>>>
>>>> Chris has already replied directly to me.
>>>> On 04/07/2017 06:50 PM, Chris Metcalf wrote:
>>>>> Thanks, looks good for tilegx/tilepro.
>>>>
>> Andreas has answered regarding the explicit check of
>> ATOMIC_EXCHANGE_USES_CAS in include/atomic.h.
>> @Andreas: is m68k okay?
>>
>> Joseph has replied for mips.
>>
>> What about the other architectures? Is the definition of
>> ATOMIC_EXCHANGE_USES_CAS correct?
>>
>>>> Bye
>>>> Stefan
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-05-10 13:00 ` Stefan Liebler
@ 2017-05-17 13:09 ` Stefan Liebler
2017-05-24 6:37 ` Stefan Liebler
2017-05-30 7:18 ` Torvald Riegel
1 sibling, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-05-17 13:09 UTC (permalink / raw)
To: libc-alpha
Cc: davem, tuliom, chunglin_tang, david, schwab, vapier,
Carlos O'Donell, rth, pb, marcus.shawcroft, szabolcs.nagy
On 05/10/2017 03:00 PM, Stefan Liebler wrote:
> On 05/03/2017 01:38 PM, Stefan Liebler wrote:
>> On 04/25/2017 08:46 AM, Stefan Liebler wrote:
>>> On 04/18/2017 03:09 PM, Stefan Liebler wrote:
>>>> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
>>>>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
>>>>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>>>>>>> @architecture maintainers:
>>>>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>>>>>>> specific atomic-machine.h files.
>>>>>>> See comment in include/atomic.h:
>>>>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange
>>>>>>> operations
>>>>>>> are implemented based on a CAS loop; otherwise, this is 0 and we
>>>>>>> assume
>>>>>>> that the atomic_exchange operations could provide better
>>>>>>> performance
>>>>>>> than a CAS loop. */
>>>>>>>
>>>>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
>>>>>>> your
>>>>>>> architecture, please?
>>>>
>>>>
>>>> PING
>>>>
>>> PING
>>
>> PING
>
> PING
>
> @Torvald:
> I'm not sure if we will get answers from everybody.
> What do you propose how to proceed with the definitions of
> ATOMIC_EXCHANGE_USES_CAS?
>
PING
(This is the post with the patch defining ATOMIC_EXCHANGE_USES_CAS:
https://www.sourceware.org/ml/libc-alpha/2017-04/msg00135.html)
>>>>
>>>>>>
>>>>>> I think we primarily need feedback from the maintainers of the
>>>>>> architectures where we're not quite sure. Let's see how responsive
>>>>>> everyone is and then decide whether we need to continue pinging
>>>>>> some of
>>>>>> them potentially or whether we have enough information to be able to
>>>>>> commit the patch.
>>>>>>
>>>>> Okay.
>>>>>
>>>>> Chris has already replied directly to me.
>>>>> On 04/07/2017 06:50 PM, Chris Metcalf wrote:
>>>>>> Thanks, looks good for tilegx/tilepro.
>>>>>
>>> Andreas has answered regarding the explicit check of
>>> ATOMIC_EXCHANGE_USES_CAS in include/atomic.h.
>>> @Andreas: is m68k okay?
>>>
>>> Joseph has replied for mips.
>>>
>>> What about the other architectures? Is the definition of
>>> ATOMIC_EXCHANGE_USES_CAS correct?
>>>
>>>>> Bye
>>>>> Stefan
>>>>>
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-05-17 13:09 ` Stefan Liebler
@ 2017-05-24 6:37 ` Stefan Liebler
0 siblings, 0 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-05-24 6:37 UTC (permalink / raw)
To: libc-alpha
On 05/17/2017 03:09 PM, Stefan Liebler wrote:
> On 05/10/2017 03:00 PM, Stefan Liebler wrote:
>> On 05/03/2017 01:38 PM, Stefan Liebler wrote:
>>> On 04/25/2017 08:46 AM, Stefan Liebler wrote:
>>>> On 04/18/2017 03:09 PM, Stefan Liebler wrote:
>>>>> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
>>>>>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
>>>>>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>>>>>>>> @architecture maintainers:
>>>>>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>>>>>>>> specific atomic-machine.h files.
>>>>>>>> See comment in include/atomic.h:
>>>>>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange
>>>>>>>> operations
>>>>>>>> are implemented based on a CAS loop; otherwise, this is 0
>>>>>>>> and we
>>>>>>>> assume
>>>>>>>> that the atomic_exchange operations could provide better
>>>>>>>> performance
>>>>>>>> than a CAS loop. */
>>>>>>>>
>>>>>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
>>>>>>>> your
>>>>>>>> architecture, please?
>>>>>
>>>>>
>>>>> PING
>>>>>
>>>> PING
>>>
>>> PING
>>
>> PING
>>
>> @Torvald:
>> I'm not sure if we will get answers from everybody.
>> What do you propose how to proceed with the definitions of
>> ATOMIC_EXCHANGE_USES_CAS?
>>
> PING
>
> (This is the post with the patch defining ATOMIC_EXCHANGE_USES_CAS:
> https://www.sourceware.org/ml/libc-alpha/2017-04/msg00135.html)
PING
>>>>>
>>>>>>>
>>>>>>> I think we primarily need feedback from the maintainers of the
>>>>>>> architectures where we're not quite sure. Let's see how responsive
>>>>>>> everyone is and then decide whether we need to continue pinging
>>>>>>> some of
>>>>>>> them potentially or whether we have enough information to be able to
>>>>>>> commit the patch.
>>>>>>>
>>>>>> Okay.
>>>>>>
>>>>>> Chris has already replied directly to me.
>>>>>> On 04/07/2017 06:50 PM, Chris Metcalf wrote:
>>>>>>> Thanks, looks good for tilegx/tilepro.
>>>>>>
>>>> Andreas has answered regarding the explicit check of
>>>> ATOMIC_EXCHANGE_USES_CAS in include/atomic.h.
>>>> @Andreas: is m68k okay?
>>>>
>>>> Joseph has replied for mips.
>>>>
>>>> What about the other architectures? Is the definition of
>>>> ATOMIC_EXCHANGE_USES_CAS correct?
>>>>
>>>>>> Bye
>>>>>> Stefan
>>>>>>
>>>>>
>>>>
>>>
>>
>
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-05-10 13:00 ` Stefan Liebler
2017-05-17 13:09 ` Stefan Liebler
@ 2017-05-30 7:18 ` Torvald Riegel
2017-05-31 8:29 ` Stefan Liebler
1 sibling, 1 reply; 63+ messages in thread
From: Torvald Riegel @ 2017-05-30 7:18 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha
On Wed, 2017-05-10 at 15:00 +0200, Stefan Liebler wrote:
> On 05/03/2017 01:38 PM, Stefan Liebler wrote:
> > On 04/25/2017 08:46 AM, Stefan Liebler wrote:
> >> On 04/18/2017 03:09 PM, Stefan Liebler wrote:
> >>> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
> >>>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
> >>>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
> >>>>>> @architecture maintainers:
> >>>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
> >>>>>> specific atomic-machine.h files.
> >>>>>> See comment in include/atomic.h:
> >>>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange
> >>>>>> operations
> >>>>>> are implemented based on a CAS loop; otherwise, this is 0 and we
> >>>>>> assume
> >>>>>> that the atomic_exchange operations could provide better
> >>>>>> performance
> >>>>>> than a CAS loop. */
> >>>>>>
> >>>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
> >>>>>> your
> >>>>>> architecture, please?
> >>>
> >>>
> >>> PING
> >>>
> >> PING
> >
> > PING
>
> PING
>
> @Torvald:
> I'm not sure if we will get answers from everybody.
> What do you propose how to proceed with the definitions of
> ATOMIC_EXCHANGE_USES_CAS?
Which archs are still missing? If maintainers don't reply, I suggest we
do our best to figure out what's the case for each missing arch, and add
a note that it should be checked eventually (eg, /* XXX Is this actually
correct? */) to the code, and then commit. Please CC: me on such a
patch, so I can have a last look at it.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros.
2017-04-07 16:23 ` Stefan Liebler
2017-04-09 13:51 ` Torvald Riegel
2017-04-10 8:17 ` [PATCH 1/2] " Andreas Schwab
@ 2017-05-30 21:00 ` Tulio Magno Quites Machado Filho
2 siblings, 0 replies; 63+ messages in thread
From: Tulio Magno Quites Machado Filho @ 2017-05-30 21:00 UTC (permalink / raw)
To: Stefan Liebler, libc-alpha
Cc: szabolcs.nagy, marcus.shawcroft, pb, Joseph S. Myers, rth,
Carlos O'Donell, vapier, schwab, cmetcalf, david,
chunglin_tang, munroesj, davem, cmetcalf
Stefan Liebler <stli@linux.vnet.ibm.com> writes:
> On 04/06/2017 04:00 PM, Torvald Riegel wrote:
>> Otherwise, this patch looks good to me.
> Thanks for review. Here is an updated patch. I've changed the comments
> and added the POSIX requirement in pthread_spin_trylock.
>
> @architecture maintainers:
> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
> specific atomic-machine.h files.
> See comment in include/atomic.h:
> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange operations
> are implemented based on a CAS loop; otherwise, this is 0 and we assume
> that the atomic_exchange operations could provide better performance
> than a CAS loop. */
>
> Can review the definition to 0 or 1 in the atomic-machine.h file of your
> architecture, please?
The values look good for powerpc32 and powerpc64.
--
Tulio Magno
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-05-30 7:18 ` Torvald Riegel
@ 2017-05-31 8:29 ` Stefan Liebler
2017-05-31 16:48 ` Torvald Riegel
0 siblings, 1 reply; 63+ messages in thread
From: Stefan Liebler @ 2017-05-31 8:29 UTC (permalink / raw)
To: libc-alpha; +Cc: Torvald Riegel
[-- Attachment #1: Type: text/plain, Size: 2861 bytes --]
On 05/30/2017 09:18 AM, Torvald Riegel wrote:
> On Wed, 2017-05-10 at 15:00 +0200, Stefan Liebler wrote:
>> On 05/03/2017 01:38 PM, Stefan Liebler wrote:
>>> On 04/25/2017 08:46 AM, Stefan Liebler wrote:
>>>> On 04/18/2017 03:09 PM, Stefan Liebler wrote:
>>>>> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
>>>>>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
>>>>>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>>>>>>>> @architecture maintainers:
>>>>>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>>>>>>>> specific atomic-machine.h files.
>>>>>>>> See comment in include/atomic.h:
>>>>>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange
>>>>>>>> operations
>>>>>>>> are implemented based on a CAS loop; otherwise, this is 0 and we
>>>>>>>> assume
>>>>>>>> that the atomic_exchange operations could provide better
>>>>>>>> performance
>>>>>>>> than a CAS loop. */
>>>>>>>>
>>>>>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
>>>>>>>> your
>>>>>>>> architecture, please?
>>>>>
>>>>>
>>>>> PING
>>>>>
>>>> PING
>>>
>>> PING
>>
>> PING
>>
>> @Torvald:
>> I'm not sure if we will get answers from everybody.
>> What do you propose how to proceed with the definitions of
>> ATOMIC_EXCHANGE_USES_CAS?
>
> Which archs are still missing? If maintainers don't reply, I suggest we
> do our best to figure out what's the case for each missing arch, and add
> a note that it should be checked eventually (eg, /* XXX Is this actually
> correct? */) to the code, and then commit. Please CC: me on such a
> patch, so I can have a last look at it.
>
We are sure for these archs:
-aarch64: #define ATOMIC_EXCHANGE_USES_CAS 0
-i386/x86: #define ATOMIC_EXCHANGE_USES_CAS 0
-mips: #define ATOMIC_EXCHANGE_USES_CAS 0/1
-powerpc: #define ATOMIC_EXCHANGE_USES_CAS 1
-s390: #define ATOMIC_EXCHANGE_USES_CAS 1
-tile: #define ATOMIC_EXCHANGE_USES_CAS 0
Nobody answered for these archs:
-alpha: #define ATOMIC_EXCHANGE_USES_CAS 1
-arm: #define ATOMIC_EXCHANGE_USES_CAS 1
-hppa: #define ATOMIC_EXCHANGE_USES_CAS 1
-ia64: #define ATOMIC_EXCHANGE_USES_CAS 0
-m68k: #define ATOMIC_EXCHANGE_USES_CAS 1
-microblaze: #define ATOMIC_EXCHANGE_USES_CAS 1
-nios2: #define ATOMIC_EXCHANGE_USES_CAS 1
-sh: #define ATOMIC_EXCHANGE_USES_CAS 1
-sparc: #define ATOMIC_EXCHANGE_USES_CAS 1
In the two of three sparc files ...
./sysdeps/sparc/sparc64/atomic-machine.h
./sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
... there is the swap instruction in macro atomic_exchange_acq
for 4 bytes. Other sizes are aborted or done by CAS.
Shall we use #define ATOMIC_EXCHANGE_USES_CAS 0 here?
I've attached the current version with
/* XXX Is this actually correct? */
for all architecture for which we didn't get an answer.
The second patch "S390: Use generic spinlock code." remains the same.
Bye
Stefan
[-- Attachment #2: 0001-Optimize-generic-spinlock-code-and-use-C11-like-atom.patch --]
[-- Type: text/x-patch, Size: 39143 bytes --]
From eb3d559d07a93508d62e9a1ff08dede5b69da1a8 Mon Sep 17 00:00:00 2001
From: Stefan Liebler <stli@linux.vnet.ibm.com>
Date: Wed, 31 May 2017 10:06:36 +0200
Subject: [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic
macros.
This patch optimizes the generic spinlock code.
The type pthread_spinlock_t is a typedef to volatile int on all archs.
Passing a volatile pointer to the atomic macros which are not mapped to the
C11 atomic builtins can lead to extra stores and loads to stack if such
a macro creates a temporary variable by using "__typeof (*(mem)) tmp;".
Thus, those macros which are used by spinlock code - atomic_exchange_acquire,
atomic_load_relaxed, atomic_compare_exchange_weak - have to be adjusted.
According to the comment from Szabolcs Nagy, the type of a cast expression is
unqualified (see http://www.open-std.org/jtc1/sc22/wg14/www/docs/dr_423.htm):
__typeof ((__typeof (*(mem)) *(mem)) tmp;
Thus from spinlock perspective the variable tmp is of type int instead of
type volatile int. This patch adjusts those macros in include/atomic.h.
With this construct GCC >= 5 omits the extra stores and loads.
The atomic macros are replaced by the C11 like atomic macros and thus
the code is aligned to it. The pthread_spin_unlock implementation is now
using release memory order instead of sequentially consistent memory order.
The issue with passed volatile int pointers applies to the C11 like atomic
macros as well as the ones used before.
I've added a glibc_likely hint to the first atomic exchange in
pthread_spin_lock in order to return immediately to the caller if the lock is
free. Without the hint, there is an additional jump if the lock is free.
I've added the atomic_spin_nop macro within the loop of plain reads.
The plain reads are also realized by C11 like atomic_load_relaxed macro.
The new define ATOMIC_EXCHANGE_USES_CAS determines if the first try to acquire
the spinlock in pthread_spin_lock or pthread_spin_trylock is an exchange
or a CAS. This is defined in atomic-machine.h for all architectures.
The define SPIN_LOCK_READS_BETWEEN_CMPXCHG is now removed.
There is no technical reason for throwing in a CAS every now and then,
and so far we have no evidence that it can improve performance.
If that would be the case, we have to adjust other spin-waiting loops
elsewhere, too! Using a CAS loop without plain reads is not a good idea
on many targets and wasn't used by one. Thus there is now no option to
do so.
Architectures are now using the generic spinlock automatically if they
do not provide an own implementation. Thus the pthread_spin_lock.c files
in sysdeps folder are deleted.
ChangeLog:
* NEWS: Mention new spinlock implementation.
* include/atomic.h:
(__atomic_val_bysize): Cast type to omit volatile qualifier.
(atomic_exchange_acq): Likewise.
(atomic_load_relaxed): Likewise.
(ATOMIC_EXCHANGE_USES_CAS): Check definition.
* nptl/pthread_spin_init.c (pthread_spin_init):
Use atomic_store_relaxed.
* nptl/pthread_spin_lock.c (pthread_spin_lock):
Use C11-like atomic macros.
* nptl/pthread_spin_trylock.c (pthread_spin_trylock):
Likewise.
* nptl/pthread_spin_unlock.c (pthread_spin_unlock):
Use atomic_store_release.
* sysdeps/aarch64/nptl/pthread_spin_lock.c: Delete File.
* sysdeps/arm/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/hppa/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/m68k/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/microblaze/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/mips/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/nios2/nptl/pthread_spin_lock.c: Likewise.
* sysdeps/aarch64/atomic-machine.h (ATOMIC_EXCHANGE_USES_CAS): Define.
* sysdeps/alpha/atomic-machine.h: Likewise.
* sysdeps/arm/atomic-machine.h: Likewise.
* sysdeps/i386/atomic-machine.h: Likewise.
* sysdeps/ia64/atomic-machine.h: Likewise.
* sysdeps/m68k/coldfire/atomic-machine.h: Likewise.
* sysdeps/m68k/m680x0/m68020/atomic-machine.h: Likewise.
* sysdeps/microblaze/atomic-machine.h: Likewise.
* sysdeps/mips/atomic-machine.h: Likewise.
* sysdeps/powerpc/powerpc32/atomic-machine.h: Likewise.
* sysdeps/powerpc/powerpc64/atomic-machine.h: Likewise.
* sysdeps/s390/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc32/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc32/sparcv9/atomic-machine.h: Likewise.
* sysdeps/sparc/sparc64/atomic-machine.h: Likewise.
* sysdeps/tile/tilegx/atomic-machine.h: Likewise.
* sysdeps/tile/tilepro/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/hppa/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/nios2/atomic-machine.h: Likewise.
* sysdeps/unix/sysv/linux/sh/atomic-machine.h: Likewise.
* sysdeps/x86_64/atomic-machine.h: Likewise.
---
NEWS | 11 ++++
include/atomic.h | 16 +++--
nptl/pthread_spin_init.c | 3 +-
nptl/pthread_spin_lock.c | 71 +++++++++++++---------
nptl/pthread_spin_trylock.c | 54 +++++++++++++++-
nptl/pthread_spin_unlock.c | 6 +-
sysdeps/aarch64/atomic-machine.h | 1 +
sysdeps/aarch64/nptl/pthread_spin_lock.c | 24 --------
sysdeps/alpha/atomic-machine.h | 3 +
sysdeps/arm/atomic-machine.h | 3 +
sysdeps/arm/nptl/pthread_spin_lock.c | 23 -------
sysdeps/hppa/nptl/pthread_spin_lock.c | 23 -------
sysdeps/i386/atomic-machine.h | 1 +
sysdeps/ia64/atomic-machine.h | 3 +
sysdeps/m68k/coldfire/atomic-machine.h | 3 +
sysdeps/m68k/m680x0/m68020/atomic-machine.h | 3 +
sysdeps/m68k/nptl/pthread_spin_lock.c | 24 --------
sysdeps/microblaze/atomic-machine.h | 3 +
sysdeps/microblaze/nptl/pthread_spin_lock.c | 24 --------
sysdeps/mips/atomic-machine.h | 13 +++-
sysdeps/mips/nptl/pthread_spin_lock.c | 23 -------
sysdeps/nios2/nptl/pthread_spin_lock.c | 24 --------
sysdeps/powerpc/powerpc32/atomic-machine.h | 1 +
sysdeps/powerpc/powerpc64/atomic-machine.h | 1 +
sysdeps/s390/atomic-machine.h | 2 +
sysdeps/sparc/sparc32/atomic-machine.h | 3 +
sysdeps/sparc/sparc32/sparcv9/atomic-machine.h | 3 +
sysdeps/sparc/sparc64/atomic-machine.h | 3 +
sysdeps/tile/tilegx/atomic-machine.h | 1 +
sysdeps/tile/tilepro/atomic-machine.h | 1 +
sysdeps/unix/sysv/linux/hppa/atomic-machine.h | 3 +
.../unix/sysv/linux/m68k/coldfire/atomic-machine.h | 3 +
sysdeps/unix/sysv/linux/nios2/atomic-machine.h | 3 +
sysdeps/unix/sysv/linux/sh/atomic-machine.h | 3 +
sysdeps/x86_64/atomic-machine.h | 1 +
35 files changed, 182 insertions(+), 205 deletions(-)
delete mode 100644 sysdeps/aarch64/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/arm/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/hppa/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/m68k/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/microblaze/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/mips/nptl/pthread_spin_lock.c
delete mode 100644 sysdeps/nios2/nptl/pthread_spin_lock.c
diff --git a/NEWS b/NEWS
index b4ecd62..b3cbdb8 100644
--- a/NEWS
+++ b/NEWS
@@ -66,6 +66,17 @@ Version 2.26
* The port to Native Client running on ARMv7-A (--host=arm-nacl) has been
removed.
+* The synchronization that pthread_spin_unlock performs has been changed
+ to now be equivalent to a C11 atomic store with release memory order to
+ the spin lock's memory location. This ensures correct synchronization
+ for the spin lock's operations and critical sections protected by a spin
+ lock. Previously, several (but not all) architectures used stronger
+ synchronization (e.g., containing what is often called a full barrier).
+ This change can improve performance, but may affect odd fringe uses of
+ spin locks that depend on the previous behavior (e.g., using spin locks
+ as atomic variables to try to implement Dekker's mutual exclusion
+ algorithm).
+
Security related changes:
* The DNS stub resolver limits the advertised UDP buffer size to 1200 bytes,
diff --git a/include/atomic.h b/include/atomic.h
index 7f32640..d002b11 100644
--- a/include/atomic.h
+++ b/include/atomic.h
@@ -54,7 +54,7 @@
and following args. */
#define __atomic_val_bysize(pre, post, mem, ...) \
({ \
- __typeof (*mem) __atg1_result; \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg1_result; \
if (sizeof (*mem) == 1) \
__atg1_result = pre##_8_##post (mem, __VA_ARGS__); \
else if (sizeof (*mem) == 2) \
@@ -162,9 +162,9 @@
/* Store NEWVALUE in *MEM and return the old value. */
#ifndef atomic_exchange_acq
# define atomic_exchange_acq(mem, newvalue) \
- ({ __typeof (*(mem)) __atg5_oldval; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg5_oldval; \
__typeof (mem) __atg5_memp = (mem); \
- __typeof (*(mem)) __atg5_value = (newvalue); \
+ __typeof ((__typeof (*(mem))) *(mem)) __atg5_value = (newvalue); \
\
do \
__atg5_oldval = *__atg5_memp; \
@@ -668,7 +668,7 @@ void __atomic_link_error (void);
# ifndef atomic_load_relaxed
# define atomic_load_relaxed(mem) \
- ({ __typeof (*(mem)) __atg100_val; \
+ ({ __typeof ((__typeof (*(mem))) *(mem)) __atg100_val; \
__asm ("" : "=r" (__atg100_val) : "0" (*(mem))); \
__atg100_val; })
# endif
@@ -818,4 +818,12 @@ void __atomic_link_error (void);
# define atomic_spin_nop() do { /* nothing */ } while (0)
#endif
+/* ATOMIC_EXCHANGE_USES_CAS is non-zero if atomic_exchange operations
+ are implemented based on a CAS loop; otherwise, this is zero and we assume
+ that the atomic_exchange operations could provide better performance
+ than a CAS loop. */
+#ifndef ATOMIC_EXCHANGE_USES_CAS
+# error ATOMIC_EXCHANGE_USES_CAS has to be defined.
+#endif
+
#endif /* atomic.h */
diff --git a/nptl/pthread_spin_init.c b/nptl/pthread_spin_init.c
index 01dec5e..fe30913 100644
--- a/nptl/pthread_spin_init.c
+++ b/nptl/pthread_spin_init.c
@@ -22,6 +22,7 @@
int
pthread_spin_init (pthread_spinlock_t *lock, int pshared)
{
- *lock = 0;
+ /* Relaxed MO is fine because this is an initializing store. */
+ atomic_store_relaxed (lock, 0);
return 0;
}
diff --git a/nptl/pthread_spin_lock.c b/nptl/pthread_spin_lock.c
index 4d03b78..682af80 100644
--- a/nptl/pthread_spin_lock.c
+++ b/nptl/pthread_spin_lock.c
@@ -19,27 +19,35 @@
#include <atomic.h>
#include "pthreadP.h"
-/* A machine-specific version can define SPIN_LOCK_READS_BETWEEN_CMPXCHG
- to the number of plain reads that it's optimal to spin on between uses
- of atomic_compare_and_exchange_val_acq. If spinning forever is optimal
- then use -1. If no plain reads here would ever be optimal, use 0. */
-#ifndef SPIN_LOCK_READS_BETWEEN_CMPXCHG
-# warning machine-dependent file should define SPIN_LOCK_READS_BETWEEN_CMPXCHG
-# define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-#endif
-
int
pthread_spin_lock (pthread_spinlock_t *lock)
{
- /* atomic_exchange usually takes less instructions than
- atomic_compare_and_exchange. On the other hand,
- atomic_compare_and_exchange potentially generates less bus traffic
- when the lock is locked.
- We assume that the first try mostly will be successful, and we use
- atomic_exchange. For the subsequent tries we use
- atomic_compare_and_exchange. */
- if (atomic_exchange_acq (lock, 1) == 0)
+ int val = 0;
+
+ /* We assume that the first try mostly will be successful, thus we use
+ atomic_exchange if it is not implemented by a CAS loop (we also assume
+ that atomic_exchange can be faster if it succeeds, see
+ ATOMIC_EXCHANGE_USES_CAS). Otherwise, we use a weak CAS and not an
+ exchange so we bail out after the first failed attempt to change the
+ state. For the subsequent attempts we use atomic_compare_and_exchange
+ after we observe that the lock is not acquired.
+ See also comment in pthread_spin_trylock.
+ We use acquire MO to synchronize-with the release MO store in
+ pthread_spin_unlock, and thus ensure that prior critical sections
+ happen-before this critical section. */
+#if ! ATOMIC_EXCHANGE_USES_CAS
+ /* Try to acquire the lock with an exchange instruction as this architecture
+ has such an instruction and we assume it is faster than a CAS.
+ The acquisition succeeds if the lock is not in an acquired state. */
+ if (__glibc_likely (atomic_exchange_acquire (lock, 1) == 0))
return 0;
+#else
+ /* Try to acquire the lock with a CAS instruction as this architecture
+ has no exchange instruction. The acquisition succeeds if the lock is not
+ acquired. */
+ if (__glibc_likely (atomic_compare_exchange_weak_acquire (lock, &val, 1)))
+ return 0;
+#endif
do
{
@@ -47,23 +55,26 @@ pthread_spin_lock (pthread_spinlock_t *lock)
to cmpxchg is not a good idea on many targets as that will force
expensive memory synchronizations among processors and penalize other
running threads.
- On the other hand, we do want to update memory state on the local core
- once in a while to avoid spinning indefinitely until some event that
- will happen to update local memory as a side-effect. */
- if (SPIN_LOCK_READS_BETWEEN_CMPXCHG >= 0)
+ There is no technical reason for throwing in a CAS every now and then,
+ and so far we have no evidence that it can improve performance.
+ If that would be the case, we have to adjust other spin-waiting loops
+ elsewhere, too!
+ Thus we use relaxed MO reads until we observe the lock to not be
+ acquired anymore. */
+ do
{
- int wait = SPIN_LOCK_READS_BETWEEN_CMPXCHG;
+ /* TODO Back-off. */
- while (*lock != 0 && wait > 0)
- --wait;
- }
- else
- {
- while (*lock != 0)
- ;
+ atomic_spin_nop ();
+
+ val = atomic_load_relaxed (lock);
}
+ while (val != 0);
+
+ /* We need acquire memory order here for the same reason as mentioned
+ for the first try to lock the spinlock. */
}
- while (atomic_compare_and_exchange_val_acq (lock, 1, 0) != 0);
+ while (!atomic_compare_exchange_weak_acquire (lock, &val, 1));
return 0;
}
diff --git a/nptl/pthread_spin_trylock.c b/nptl/pthread_spin_trylock.c
index 593bba3..83921b0 100644
--- a/nptl/pthread_spin_trylock.c
+++ b/nptl/pthread_spin_trylock.c
@@ -23,5 +23,57 @@
int
pthread_spin_trylock (pthread_spinlock_t *lock)
{
- return atomic_exchange_acq (lock, 1) ? EBUSY : 0;
+ /* For the spin try lock, we have the following possibilities:
+
+ 1) If we assume that trylock will most likely succeed in practice:
+ * We just do an exchange.
+
+ 2) If we want to bias towards cases where trylock succeeds, but don't
+ rule out contention:
+ * If exchange is not implemented by a CAS loop, and exchange is faster
+ than CAS, do an exchange.
+ * If exchange is implemented by a CAS loop, use a weak CAS and not an
+ exchange so we bail out after the first failed attempt to change the state.
+
+ 3) If we expect contention to be likely:
+ * If CAS always brings the cache line into an exclusive state even if the
+ spinlock is already acquired, then load the value first with
+ atomic_load_relaxed and test if lock is not acquired. Then do 2).
+
+ We assume that 2) is the common case, and that this won't be slower than
+ 1) in the common case.
+
+ We use acquire MO to synchronize-with the release MO store in
+ pthread_spin_unlock, and thus ensure that prior critical sections
+ happen-before this critical section. */
+#if ! ATOMIC_EXCHANGE_USES_CAS
+ /* Try to acquire the lock with an exchange instruction as this architecture
+ has such an instruction and we assume it is faster than a CAS.
+ The acquisition succeeds if the lock is not in an acquired state. */
+ if (atomic_exchange_acquire (lock, 1) == 0)
+ return 0;
+#else
+ /* Try to acquire the lock with a CAS instruction as this architecture
+ has no exchange instruction. The acquisition succeeds if the lock is not
+ acquired. */
+ do
+ {
+ int val = 0;
+ if (atomic_compare_exchange_weak_acquire (lock, &val, 1))
+ return 0;
+ }
+ /* atomic_compare_exchange_weak_acquire can fail spuriously. Whereas
+ C++11 and C11 make it clear that trylock operations can fail spuriously,
+ POSIX does not explicitly specify this; it only specifies that failing
+ synchronization operations do not need to have synchronization effects
+ themselves, but a spurious failure is something that could contradict a
+ happens-before established earlier (e.g., that we need to observe that
+ the lock is acquired). Therefore, we emulate a strong CAS by simply
+ checking with a relaxed MO load that the lock is really acquired before
+ returning EBUSY; the additional overhead this may cause is on the slow
+ path. */
+ while (atomic_load_relaxed (lock) == 0);
+#endif
+
+ return EBUSY;
}
diff --git a/nptl/pthread_spin_unlock.c b/nptl/pthread_spin_unlock.c
index 5fd73e5..f83b696 100644
--- a/nptl/pthread_spin_unlock.c
+++ b/nptl/pthread_spin_unlock.c
@@ -23,7 +23,9 @@
int
pthread_spin_unlock (pthread_spinlock_t *lock)
{
- atomic_full_barrier ();
- *lock = 0;
+ /* The atomic_store_release synchronizes-with the atomic_exchange_acquire
+ or atomic_compare_exchange_weak_acquire in pthread_spin_lock /
+ pthread_spin_trylock. */
+ atomic_store_release (lock, 0);
return 0;
}
diff --git a/sysdeps/aarch64/atomic-machine.h b/sysdeps/aarch64/atomic-machine.h
index a5d2213..eb59a5b 100644
--- a/sysdeps/aarch64/atomic-machine.h
+++ b/sysdeps/aarch64/atomic-machine.h
@@ -38,6 +38,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 1
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange succesful. */
diff --git a/sysdeps/aarch64/nptl/pthread_spin_lock.c b/sysdeps/aarch64/nptl/pthread_spin_lock.c
deleted file mode 100644
index fcfcb40..0000000
--- a/sysdeps/aarch64/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
-
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public License as
- published by the Free Software Foundation; either version 2.1 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/alpha/atomic-machine.h b/sysdeps/alpha/atomic-machine.h
index 06e93f2..2cb2290 100644
--- a/sysdeps/alpha/atomic-machine.h
+++ b/sysdeps/alpha/atomic-machine.h
@@ -45,6 +45,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
#ifdef UP
# define __MB /* nothing */
diff --git a/sysdeps/arm/atomic-machine.h b/sysdeps/arm/atomic-machine.h
index eeac7f0..cfa5bf3 100644
--- a/sysdeps/arm/atomic-machine.h
+++ b/sysdeps/arm/atomic-machine.h
@@ -36,6 +36,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
void __arm_link_error (void);
#ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4
diff --git a/sysdeps/arm/nptl/pthread_spin_lock.c b/sysdeps/arm/nptl/pthread_spin_lock.c
deleted file mode 100644
index 037b3b8..0000000
--- a/sysdeps/arm/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/hppa/nptl/pthread_spin_lock.c b/sysdeps/hppa/nptl/pthread_spin_lock.c
deleted file mode 100644
index 14f36a6..0000000
--- a/sysdeps/hppa/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2005-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/i386/atomic-machine.h b/sysdeps/i386/atomic-machine.h
index 77759f7..0e24200 100644
--- a/sysdeps/i386/atomic-machine.h
+++ b/sysdeps/i386/atomic-machine.h
@@ -56,6 +56,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
diff --git a/sysdeps/ia64/atomic-machine.h b/sysdeps/ia64/atomic-machine.h
index ecf9750..f04ac05 100644
--- a/sysdeps/ia64/atomic-machine.h
+++ b/sysdeps/ia64/atomic-machine.h
@@ -46,6 +46,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 0
+
#define __arch_compare_and_exchange_bool_8_acq(mem, newval, oldval) \
(abort (), 0)
diff --git a/sysdeps/m68k/coldfire/atomic-machine.h b/sysdeps/m68k/coldfire/atomic-machine.h
index 9aeb993..d2e4a1f 100644
--- a/sysdeps/m68k/coldfire/atomic-machine.h
+++ b/sysdeps/m68k/coldfire/atomic-machine.h
@@ -53,6 +53,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* The only basic operation needed is compare and exchange. */
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
({ __typeof (mem) __gmemp = (mem); \
diff --git a/sysdeps/m68k/m680x0/m68020/atomic-machine.h b/sysdeps/m68k/m680x0/m68020/atomic-machine.h
index 00dc22d..83238f5 100644
--- a/sysdeps/m68k/m680x0/m68020/atomic-machine.h
+++ b/sysdeps/m68k/m680x0/m68020/atomic-machine.h
@@ -47,6 +47,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
({ __typeof (*(mem)) __ret; \
__asm __volatile ("cas%.b %0,%2,%1" \
diff --git a/sysdeps/m68k/nptl/pthread_spin_lock.c b/sysdeps/m68k/nptl/pthread_spin_lock.c
deleted file mode 100644
index 62795f4..0000000
--- a/sysdeps/m68k/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2010-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
- Contributed by Maxim Kuvyrkov <maxim@codesourcery.com>, 2010.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/microblaze/atomic-machine.h b/sysdeps/microblaze/atomic-machine.h
index dc5309c..d73c69d 100644
--- a/sysdeps/microblaze/atomic-machine.h
+++ b/sysdeps/microblaze/atomic-machine.h
@@ -38,6 +38,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* Microblaze does not have byte and halfword forms of load and reserve and
store conditional. So for microblaze we stub out the 8- and 16-bit forms. */
diff --git a/sysdeps/microblaze/nptl/pthread_spin_lock.c b/sysdeps/microblaze/nptl/pthread_spin_lock.c
deleted file mode 100644
index fcfcb40..0000000
--- a/sysdeps/microblaze/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* Copyright (C) 2008-2017 Free Software Foundation, Inc.
-
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public License as
- published by the Free Software Foundation; either version 2.1 of the
- License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library; if not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/mips/atomic-machine.h b/sysdeps/mips/atomic-machine.h
index 54c182b..16fef6b 100644
--- a/sysdeps/mips/atomic-machine.h
+++ b/sysdeps/mips/atomic-machine.h
@@ -92,7 +92,15 @@ typedef uintmax_t uatomic_max_t;
have no assembly alternative available and want to avoid the __sync_*
builtins if at all possible. */
-#define USE_ATOMIC_COMPILER_BUILTINS 1
+# define USE_ATOMIC_COMPILER_BUILTINS 1
+
+/* MIPS is an LL/SC machine. However, XLP has a direct atomic exchange
+ instruction which will be used by __atomic_exchange_n. */
+# ifdef _MIPS_ARCH_XLP
+# define ATOMIC_EXCHANGE_USES_CAS 0
+# else
+# define ATOMIC_EXCHANGE_USES_CAS 1
+# endif
/* Compare and exchange.
For all "bool" routines, we return FALSE if exchange succesful. */
@@ -213,7 +221,8 @@ typedef uintmax_t uatomic_max_t;
/* This implementation using inline assembly will be removed once glibc
requires GCC 4.8 or later to build. */
-#define USE_ATOMIC_COMPILER_BUILTINS 0
+# define USE_ATOMIC_COMPILER_BUILTINS 0
+# define ATOMIC_EXCHANGE_USES_CAS 1
/* Compare and exchange. For all of the "xxx" routines, we expect a
"__prev" and a "__cmp" variable to be provided by the enclosing scope,
diff --git a/sysdeps/mips/nptl/pthread_spin_lock.c b/sysdeps/mips/nptl/pthread_spin_lock.c
deleted file mode 100644
index 19d87a5..0000000
--- a/sysdeps/mips/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (C) 2012-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/nios2/nptl/pthread_spin_lock.c b/sysdeps/nios2/nptl/pthread_spin_lock.c
deleted file mode 100644
index b203469..0000000
--- a/sysdeps/nios2/nptl/pthread_spin_lock.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* pthread spin-lock implementation for Nios II.
- Copyright (C) 2005-2017 Free Software Foundation, Inc.
- This file is part of the GNU C Library.
-
- The GNU C Library is free software; you can redistribute it and/or
- modify it under the terms of the GNU Lesser General Public
- License as published by the Free Software Foundation; either
- version 2.1 of the License, or (at your option) any later version.
-
- The GNU C Library is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- Lesser General Public License for more details.
-
- You should have received a copy of the GNU Lesser General Public
- License along with the GNU C Library. If not, see
- <http://www.gnu.org/licenses/>. */
-
-#define SPIN_LOCK_READS_BETWEEN_CMPXCHG 1000
-
-/* We can't use the normal "#include <nptl/pthread_spin_lock.c>" because
- it will resolve to this very file. Using "sysdeps/.." as reference to the
- top level directory does the job. */
-#include <sysdeps/../nptl/pthread_spin_lock.c>
diff --git a/sysdeps/powerpc/powerpc32/atomic-machine.h b/sysdeps/powerpc/powerpc32/atomic-machine.h
index 20d5e85..96c7d81 100644
--- a/sysdeps/powerpc/powerpc32/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc32/atomic-machine.h
@@ -35,6 +35,7 @@
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/*
* The 32-bit exchange_bool is different on powerpc64 because the subf
diff --git a/sysdeps/powerpc/powerpc64/atomic-machine.h b/sysdeps/powerpc/powerpc64/atomic-machine.h
index 40c308e..46df488 100644
--- a/sysdeps/powerpc/powerpc64/atomic-machine.h
+++ b/sysdeps/powerpc/powerpc64/atomic-machine.h
@@ -35,6 +35,7 @@
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 1
/* The 32-bit exchange_bool is different on powerpc64 because the subf
does signed 64-bit arithmetic while the lwarx is 32-bit unsigned
diff --git a/sysdeps/s390/atomic-machine.h b/sysdeps/s390/atomic-machine.h
index 690d2e3..adaca40 100644
--- a/sysdeps/s390/atomic-machine.h
+++ b/sysdeps/s390/atomic-machine.h
@@ -67,6 +67,8 @@ typedef uintmax_t uatomic_max_t;
# define __HAVE_64B_ATOMICS 0
#endif
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* Implement some of the non-C11 atomic macros from include/atomic.h
with help of the C11 atomic builtins. The other non-C11 atomic macros
are using the macros defined here. */
diff --git a/sysdeps/sparc/sparc32/atomic-machine.h b/sysdeps/sparc/sparc32/atomic-machine.h
index acd029e..a2fe848 100644
--- a/sysdeps/sparc/sparc32/atomic-machine.h
+++ b/sysdeps/sparc/sparc32/atomic-machine.h
@@ -50,6 +50,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* We have no compare and swap, just test and set.
The following implementation contends on 64 global locks
diff --git a/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h b/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
index 7f7895e..6a19721 100644
--- a/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
+++ b/sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
@@ -47,6 +47,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
diff --git a/sysdeps/sparc/sparc64/atomic-machine.h b/sysdeps/sparc/sparc64/atomic-machine.h
index 44a43ff..7200932 100644
--- a/sysdeps/sparc/sparc64/atomic-machine.h
+++ b/sysdeps/sparc/sparc64/atomic-machine.h
@@ -47,6 +47,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
diff --git a/sysdeps/tile/tilegx/atomic-machine.h b/sysdeps/tile/tilegx/atomic-machine.h
index 6345251..e77f670 100644
--- a/sysdeps/tile/tilegx/atomic-machine.h
+++ b/sysdeps/tile/tilegx/atomic-machine.h
@@ -31,6 +31,7 @@
#endif
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* Pick appropriate 8- or 4-byte instruction. */
#define __atomic_update(mem, v, op) \
diff --git a/sysdeps/tile/tilepro/atomic-machine.h b/sysdeps/tile/tilepro/atomic-machine.h
index 33a8b85..45e36de 100644
--- a/sysdeps/tile/tilepro/atomic-machine.h
+++ b/sysdeps/tile/tilepro/atomic-machine.h
@@ -23,6 +23,7 @@
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+#define ATOMIC_EXCHANGE_USES_CAS 0
/* 32-bit integer compare-and-exchange. */
static __inline __attribute__ ((always_inline))
diff --git a/sysdeps/unix/sysv/linux/hppa/atomic-machine.h b/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
index 2cd2235..59581bd 100644
--- a/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/hppa/atomic-machine.h
@@ -39,6 +39,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* prev = *addr;
if (prev == old)
*addr = new;
diff --git a/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h b/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
index 6755a05..1daac51 100644
--- a/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/m68k/coldfire/atomic-machine.h
@@ -39,6 +39,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* The only basic operation needed is compare and exchange. */
/* For ColdFire we'll have to trap into the kernel mode anyway,
so trap from the library rather then from the kernel wrapper. */
diff --git a/sysdeps/unix/sysv/linux/nios2/atomic-machine.h b/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
index 6111ccf..d4dd025 100644
--- a/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/nios2/atomic-machine.h
@@ -34,6 +34,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
#define __arch_compare_and_exchange_val_8_acq(mem, newval, oldval) \
(abort (), (__typeof (*mem)) 0)
#define __arch_compare_and_exchange_val_16_acq(mem, newval, oldval) \
diff --git a/sysdeps/unix/sysv/linux/sh/atomic-machine.h b/sysdeps/unix/sysv/linux/sh/atomic-machine.h
index 3c58b70..5a7e953 100644
--- a/sysdeps/unix/sysv/linux/sh/atomic-machine.h
+++ b/sysdeps/unix/sysv/linux/sh/atomic-machine.h
@@ -47,6 +47,9 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 0
#define USE_ATOMIC_COMPILER_BUILTINS 0
+/* XXX Is this actually correct? */
+#define ATOMIC_EXCHANGE_USES_CAS 1
+
/* SH kernel has implemented a gUSA ("g" User Space Atomicity) support
for the user space atomicity. The atomicity macros use this scheme.
diff --git a/sysdeps/x86_64/atomic-machine.h b/sysdeps/x86_64/atomic-machine.h
index 2e8a9aa..c454734 100644
--- a/sysdeps/x86_64/atomic-machine.h
+++ b/sysdeps/x86_64/atomic-machine.h
@@ -59,6 +59,7 @@ typedef uintmax_t uatomic_max_t;
#define __HAVE_64B_ATOMICS 1
#define USE_ATOMIC_COMPILER_BUILTINS 1
+#define ATOMIC_EXCHANGE_USES_CAS 0
#define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \
__sync_val_compare_and_swap (mem, oldval, newval)
--
2.7.4
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-05-31 8:29 ` Stefan Liebler
@ 2017-05-31 16:48 ` Torvald Riegel
2017-06-01 13:40 ` Joseph Myers
2017-06-06 7:51 ` [PATCH 1/2] [COMMITTED] " Stefan Liebler
0 siblings, 2 replies; 63+ messages in thread
From: Torvald Riegel @ 2017-05-31 16:48 UTC (permalink / raw)
To: Stefan Liebler; +Cc: libc-alpha, Joseph S. Myers
On Wed, 2017-05-31 at 10:29 +0200, Stefan Liebler wrote:
> On 05/30/2017 09:18 AM, Torvald Riegel wrote:
> > On Wed, 2017-05-10 at 15:00 +0200, Stefan Liebler wrote:
> >> On 05/03/2017 01:38 PM, Stefan Liebler wrote:
> >>> On 04/25/2017 08:46 AM, Stefan Liebler wrote:
> >>>> On 04/18/2017 03:09 PM, Stefan Liebler wrote:
> >>>>> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
> >>>>>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
> >>>>>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
> >>>>>>>> @architecture maintainers:
> >>>>>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
> >>>>>>>> specific atomic-machine.h files.
> >>>>>>>> See comment in include/atomic.h:
> >>>>>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange
> >>>>>>>> operations
> >>>>>>>> are implemented based on a CAS loop; otherwise, this is 0 and we
> >>>>>>>> assume
> >>>>>>>> that the atomic_exchange operations could provide better
> >>>>>>>> performance
> >>>>>>>> than a CAS loop. */
> >>>>>>>>
> >>>>>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
> >>>>>>>> your
> >>>>>>>> architecture, please?
> >>>>>
> >>>>>
> >>>>> PING
> >>>>>
> >>>> PING
> >>>
> >>> PING
> >>
> >> PING
> >>
> >> @Torvald:
> >> I'm not sure if we will get answers from everybody.
> >> What do you propose how to proceed with the definitions of
> >> ATOMIC_EXCHANGE_USES_CAS?
> >
> > Which archs are still missing? If maintainers don't reply, I suggest we
> > do our best to figure out what's the case for each missing arch, and add
> > a note that it should be checked eventually (eg, /* XXX Is this actually
> > correct? */) to the code, and then commit. Please CC: me on such a
> > patch, so I can have a last look at it.
> >
>
> We are sure for these archs:
> -aarch64: #define ATOMIC_EXCHANGE_USES_CAS 0
> -i386/x86: #define ATOMIC_EXCHANGE_USES_CAS 0
> -mips: #define ATOMIC_EXCHANGE_USES_CAS 0/1
> -powerpc: #define ATOMIC_EXCHANGE_USES_CAS 1
> -s390: #define ATOMIC_EXCHANGE_USES_CAS 1
> -tile: #define ATOMIC_EXCHANGE_USES_CAS 0
>
> Nobody answered for these archs:
> -alpha: #define ATOMIC_EXCHANGE_USES_CAS 1
> -arm: #define ATOMIC_EXCHANGE_USES_CAS 1
> -hppa: #define ATOMIC_EXCHANGE_USES_CAS 1
> -ia64: #define ATOMIC_EXCHANGE_USES_CAS 0
> -m68k: #define ATOMIC_EXCHANGE_USES_CAS 1
> -microblaze: #define ATOMIC_EXCHANGE_USES_CAS 1
> -nios2: #define ATOMIC_EXCHANGE_USES_CAS 1
> -sh: #define ATOMIC_EXCHANGE_USES_CAS 1
> -sparc: #define ATOMIC_EXCHANGE_USES_CAS 1
Joseph, can you clarify for arm?
> In the two of three sparc files ...
> ./sysdeps/sparc/sparc64/atomic-machine.h
> ./sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
> ... there is the swap instruction in macro atomic_exchange_acq
> for 4 bytes. Other sizes are aborted or done by CAS.
> Shall we use #define ATOMIC_EXCHANGE_USES_CAS 0 here?
I suggest we let the sparc maintainer take care of that (though we could
set it to 0 for sparc32 I guess).
>
> I've attached the current version with
> /* XXX Is this actually correct? */
> for all architecture for which we didn't get an answer.
>
> The second patch "S390: Use generic spinlock code." remains the same.
I'd wait for a few more days to give Joseph time to respond, and then
commit if there are no objections or further input. I think maintainers
had enough time to comment, and you pinged them often enough already.
Thanks for being patient! :)
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-05-31 16:48 ` Torvald Riegel
@ 2017-06-01 13:40 ` Joseph Myers
2017-06-01 14:33 ` Torvald Riegel
2017-06-06 7:51 ` [PATCH 1/2] [COMMITTED] " Stefan Liebler
1 sibling, 1 reply; 63+ messages in thread
From: Joseph Myers @ 2017-06-01 13:40 UTC (permalink / raw)
To: Torvald Riegel; +Cc: Stefan Liebler, libc-alpha
On Wed, 31 May 2017, Torvald Riegel wrote:
> > Nobody answered for these archs:
> > -alpha: #define ATOMIC_EXCHANGE_USES_CAS 1
> > -arm: #define ATOMIC_EXCHANGE_USES_CAS 1
> > -hppa: #define ATOMIC_EXCHANGE_USES_CAS 1
> > -ia64: #define ATOMIC_EXCHANGE_USES_CAS 0
> > -m68k: #define ATOMIC_EXCHANGE_USES_CAS 1
> > -microblaze: #define ATOMIC_EXCHANGE_USES_CAS 1
> > -nios2: #define ATOMIC_EXCHANGE_USES_CAS 1
> > -sh: #define ATOMIC_EXCHANGE_USES_CAS 1
> > -sparc: #define ATOMIC_EXCHANGE_USES_CAS 1
>
> Joseph, can you clarify for arm?
You already answered for ARM
<https://sourceware.org/ml/libc-alpha/2017-04/msg00109.html>.
--
Joseph S. Myers
joseph@codesourcery.com
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [PING] Optimize generic spinlock code and use C11 like atomic macros.
2017-06-01 13:40 ` Joseph Myers
@ 2017-06-01 14:33 ` Torvald Riegel
0 siblings, 0 replies; 63+ messages in thread
From: Torvald Riegel @ 2017-06-01 14:33 UTC (permalink / raw)
To: Joseph Myers; +Cc: Stefan Liebler, libc-alpha
On Thu, 2017-06-01 at 13:39 +0000, Joseph Myers wrote:
> On Wed, 31 May 2017, Torvald Riegel wrote:
>
> > > Nobody answered for these archs:
> > > -alpha: #define ATOMIC_EXCHANGE_USES_CAS 1
> > > -arm: #define ATOMIC_EXCHANGE_USES_CAS 1
> > > -hppa: #define ATOMIC_EXCHANGE_USES_CAS 1
> > > -ia64: #define ATOMIC_EXCHANGE_USES_CAS 0
> > > -m68k: #define ATOMIC_EXCHANGE_USES_CAS 1
> > > -microblaze: #define ATOMIC_EXCHANGE_USES_CAS 1
> > > -nios2: #define ATOMIC_EXCHANGE_USES_CAS 1
> > > -sh: #define ATOMIC_EXCHANGE_USES_CAS 1
> > > -sparc: #define ATOMIC_EXCHANGE_USES_CAS 1
> >
> > Joseph, can you clarify for arm?
>
> You already answered for ARM
> <https://sourceware.org/ml/libc-alpha/2017-04/msg00109.html>.
>
What I wrote there was just my understanding, and I wasn't sure. I'll
assume that you are saying that this is indeed correct. If so, the
patch should remove the XXX comment.
^ permalink raw reply [flat|nested] 63+ messages in thread
* Re: [PATCH 1/2] [COMMITTED] Optimize generic spinlock code and use C11 like atomic macros.
2017-05-31 16:48 ` Torvald Riegel
2017-06-01 13:40 ` Joseph Myers
@ 2017-06-06 7:51 ` Stefan Liebler
1 sibling, 0 replies; 63+ messages in thread
From: Stefan Liebler @ 2017-06-06 7:51 UTC (permalink / raw)
To: libc-alpha; +Cc: Torvald Riegel
On 05/31/2017 06:48 PM, Torvald Riegel wrote:
> On Wed, 2017-05-31 at 10:29 +0200, Stefan Liebler wrote:
>> On 05/30/2017 09:18 AM, Torvald Riegel wrote:
>>> On Wed, 2017-05-10 at 15:00 +0200, Stefan Liebler wrote:
>>>> On 05/03/2017 01:38 PM, Stefan Liebler wrote:
>>>>> On 04/25/2017 08:46 AM, Stefan Liebler wrote:
>>>>>> On 04/18/2017 03:09 PM, Stefan Liebler wrote:
>>>>>>> On 04/10/2017 01:59 PM, Stefan Liebler wrote:
>>>>>>>> On 04/09/2017 03:51 PM, Torvald Riegel wrote:
>>>>>>>>> On Fri, 2017-04-07 at 18:22 +0200, Stefan Liebler wrote:
>>>>>>>>>> @architecture maintainers:
>>>>>>>>>> I've added defines of ATOMIC_EXCHANGE_USES_CAS in the architecture
>>>>>>>>>> specific atomic-machine.h files.
>>>>>>>>>> See comment in include/atomic.h:
>>>>>>>>>> /* ATOMIC_EXCHANGE_USES_CAS is equal to 1 if atomic_exchange
>>>>>>>>>> operations
>>>>>>>>>> are implemented based on a CAS loop; otherwise, this is 0 and we
>>>>>>>>>> assume
>>>>>>>>>> that the atomic_exchange operations could provide better
>>>>>>>>>> performance
>>>>>>>>>> than a CAS loop. */
>>>>>>>>>>
>>>>>>>>>> Can review the definition to 0 or 1 in the atomic-machine.h file of
>>>>>>>>>> your
>>>>>>>>>> architecture, please?
>>>>>>>
>>>>>>>
>>>>>>> PING
>>>>>>>
>>>>>> PING
>>>>>
>>>>> PING
>>>>
>>>> PING
>>>>
>>>> @Torvald:
>>>> I'm not sure if we will get answers from everybody.
>>>> What do you propose how to proceed with the definitions of
>>>> ATOMIC_EXCHANGE_USES_CAS?
>>>
>>> Which archs are still missing? If maintainers don't reply, I suggest we
>>> do our best to figure out what's the case for each missing arch, and add
>>> a note that it should be checked eventually (eg, /* XXX Is this actually
>>> correct? */) to the code, and then commit. Please CC: me on such a
>>> patch, so I can have a last look at it.
>>>
>>
>> We are sure for these archs:
>> -aarch64: #define ATOMIC_EXCHANGE_USES_CAS 0
>> -i386/x86: #define ATOMIC_EXCHANGE_USES_CAS 0
>> -mips: #define ATOMIC_EXCHANGE_USES_CAS 0/1
>> -powerpc: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -s390: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -tile: #define ATOMIC_EXCHANGE_USES_CAS 0
>>
>> Nobody answered for these archs:
>> -alpha: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -arm: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -hppa: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -ia64: #define ATOMIC_EXCHANGE_USES_CAS 0
>> -m68k: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -microblaze: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -nios2: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -sh: #define ATOMIC_EXCHANGE_USES_CAS 1
>> -sparc: #define ATOMIC_EXCHANGE_USES_CAS 1
>
> Joseph, can you clarify for arm?
>
removed the XXX comment for arm (see post
https://www.sourceware.org/ml/libc-alpha/2017-06/msg00028.html)
>> In the two of three sparc files ...
>> ./sysdeps/sparc/sparc64/atomic-machine.h
>> ./sysdeps/sparc/sparc32/sparcv9/atomic-machine.h
>> ... there is the swap instruction in macro atomic_exchange_acq
>> for 4 bytes. Other sizes are aborted or done by CAS.
>> Shall we use #define ATOMIC_EXCHANGE_USES_CAS 0 here?
>
> I suggest we let the sparc maintainer take care of that (though we could
> set it to 0 for sparc32 I guess).
>
Set it to 0 in ./sysdeps/sparc/sparc32/sparcv9/atomic-machine.h.
>>
>> I've attached the current version with
>> /* XXX Is this actually correct? */
>> for all architecture for which we didn't get an answer.
>>
>> The second patch "S390: Use generic spinlock code." remains the same.
>
> I'd wait for a few more days to give Joseph time to respond, and then
> commit if there are no objections or further input. I think maintainers
> had enough time to comment, and you pinged them often enough already.
>
> Thanks for being patient! :)
>
Committed.
Thanks.
Stefan
^ permalink raw reply [flat|nested] 63+ messages in thread
end of thread, other threads:[~2017-06-06 7:51 UTC | newest]
Thread overview: 63+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-12-16 16:32 [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros Stefan Liebler
2016-12-16 16:32 ` [PATCH 2/2] S390: Use generic spinlock code Stefan Liebler
2017-02-08 14:49 ` Stefan Liebler
2017-02-13 20:39 ` Torvald Riegel
2017-02-15 16:26 ` Stefan Liebler
2017-02-18 17:05 ` Torvald Riegel
2017-03-14 15:55 ` Stefan Liebler
2017-03-21 15:43 ` Stefan Liebler
2017-04-06 12:27 ` Torvald Riegel
2016-12-19 12:14 ` [PATCH 1/2] Optimize generic spinlock code and use C11 like atomic macros Szabolcs Nagy
2017-02-08 14:49 ` Stefan Liebler
2017-02-13 20:29 ` Torvald Riegel
2017-02-15 9:36 ` Stefan Liebler
2017-02-18 16:57 ` Torvald Riegel
2017-02-19 9:20 ` Florian Weimer
2017-02-20 13:11 ` Torvald Riegel
2017-02-26 7:55 ` Florian Weimer
2017-02-26 20:06 ` Torvald Riegel
2017-02-26 20:29 ` Florian Weimer
2017-02-26 20:35 ` Torvald Riegel
2017-02-27 17:57 ` Szabolcs Nagy
2017-02-28 7:15 ` Torvald Riegel
2017-03-14 15:55 ` Stefan Liebler
2017-02-20 12:15 ` Stefan Liebler
2017-02-20 13:51 ` Torvald Riegel
2017-03-14 15:55 ` Stefan Liebler
2017-03-21 15:43 ` Stefan Liebler
2017-03-22 12:56 ` Szabolcs Nagy
2017-03-23 16:16 ` Stefan Liebler
2017-03-23 17:52 ` Szabolcs Nagy
2017-04-06 12:04 ` Torvald Riegel
2017-03-27 13:08 ` Stefan Liebler
2017-04-04 10:29 ` [PING] " Stefan Liebler
2017-03-29 14:16 ` Stefan Liebler
2017-04-06 14:00 ` Torvald Riegel
2017-04-07 16:23 ` Stefan Liebler
2017-04-09 13:51 ` Torvald Riegel
2017-04-10 12:00 ` Stefan Liebler
2017-04-18 13:09 ` Stefan Liebler
2017-04-25 6:47 ` Stefan Liebler
2017-05-03 11:38 ` [PATCH 1/2] [PING] " Stefan Liebler
2017-05-10 13:00 ` Stefan Liebler
2017-05-17 13:09 ` Stefan Liebler
2017-05-24 6:37 ` Stefan Liebler
2017-05-30 7:18 ` Torvald Riegel
2017-05-31 8:29 ` Stefan Liebler
2017-05-31 16:48 ` Torvald Riegel
2017-06-01 13:40 ` Joseph Myers
2017-06-01 14:33 ` Torvald Riegel
2017-06-06 7:51 ` [PATCH 1/2] [COMMITTED] " Stefan Liebler
2017-04-10 8:17 ` [PATCH 1/2] " Andreas Schwab
2017-04-10 12:00 ` Stefan Liebler
2017-04-10 13:36 ` Andreas Schwab
2017-04-11 7:06 ` Stefan Liebler
2017-04-11 8:45 ` Andreas Schwab
2017-04-11 10:15 ` Stefan Liebler
2017-04-11 12:05 ` Andreas Schwab
2017-04-11 12:19 ` Stefan Liebler
2017-04-11 13:08 ` Zack Weinberg
2017-04-13 16:36 ` Torvald Riegel
2017-05-30 21:00 ` Tulio Magno Quites Machado Filho
2017-04-18 21:17 ` Joseph Myers
2017-04-19 8:27 ` Stefan Liebler
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