* [PATCH 1/3] LoongArch: Unify Register Names.
@ 2023-10-26 13:01 caiyinyu
2023-10-26 13:01 ` [PATCH 2/3] LoongArch: Update hwcap.h to sync with LoongArch kernel caiyinyu
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: caiyinyu @ 2023-10-26 13:01 UTC (permalink / raw)
To: libc-alpha; +Cc: adhemerval.zanella, xry111, caiyinyu
---
sysdeps/loongarch/__longjmp.S | 20 ++++++++++----------
sysdeps/loongarch/setjmp.S | 18 +++++++++---------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/sysdeps/loongarch/__longjmp.S b/sysdeps/loongarch/__longjmp.S
index cbde1946a0..e87ce31194 100644
--- a/sysdeps/loongarch/__longjmp.S
+++ b/sysdeps/loongarch/__longjmp.S
@@ -43,18 +43,18 @@ ENTRY (__longjmp)
REG_L s8, a0, 12*SZREG
#ifndef __loongarch_soft_float
- FREG_L $f24, a0, 13*SZREG + 0*SZFREG
- FREG_L $f25, a0, 13*SZREG + 1*SZFREG
- FREG_L $f26, a0, 13*SZREG + 2*SZFREG
- FREG_L $f27, a0, 13*SZREG + 3*SZFREG
- FREG_L $f28, a0, 13*SZREG + 4*SZFREG
- FREG_L $f29, a0, 13*SZREG + 5*SZFREG
- FREG_L $f30, a0, 13*SZREG + 6*SZFREG
- FREG_L $f31, a0, 13*SZREG + 7*SZFREG
+ FREG_L fs0, a0, 13*SZREG + 0*SZFREG
+ FREG_L fs1, a0, 13*SZREG + 1*SZFREG
+ FREG_L fs2, a0, 13*SZREG + 2*SZFREG
+ FREG_L fs3, a0, 13*SZREG + 3*SZFREG
+ FREG_L fs4, a0, 13*SZREG + 4*SZFREG
+ FREG_L fs5, a0, 13*SZREG + 5*SZFREG
+ FREG_L fs6, a0, 13*SZREG + 6*SZFREG
+ FREG_L fs7, a0, 13*SZREG + 7*SZFREG
#endif
- sltui a0,a1,1
+ sltui a0, a1, 1
ADD a0, a0, a1 # a0 = (a1 == 0) ? 1 : a1
- jirl zero,ra,0
+ jirl zero, ra, 0
END (__longjmp)
diff --git a/sysdeps/loongarch/setjmp.S b/sysdeps/loongarch/setjmp.S
index 6c7065cdbb..b6e4f727cd 100644
--- a/sysdeps/loongarch/setjmp.S
+++ b/sysdeps/loongarch/setjmp.S
@@ -52,19 +52,19 @@ ENTRY (__sigsetjmp)
REG_S s8, a0, 12*SZREG
#ifndef __loongarch_soft_float
- FREG_S $f24, a0, 13*SZREG + 0*SZFREG
- FREG_S $f25, a0, 13*SZREG + 1*SZFREG
- FREG_S $f26, a0, 13*SZREG + 2*SZFREG
- FREG_S $f27, a0, 13*SZREG + 3*SZFREG
- FREG_S $f28, a0, 13*SZREG + 4*SZFREG
- FREG_S $f29, a0, 13*SZREG + 5*SZFREG
- FREG_S $f30, a0, 13*SZREG + 6*SZFREG
- FREG_S $f31, a0, 13*SZREG + 7*SZFREG
+ FREG_S fs0, a0, 13*SZREG + 0*SZFREG
+ FREG_S fs1, a0, 13*SZREG + 1*SZFREG
+ FREG_S fs2, a0, 13*SZREG + 2*SZFREG
+ FREG_S fs3, a0, 13*SZREG + 3*SZFREG
+ FREG_S fs4, a0, 13*SZREG + 4*SZFREG
+ FREG_S fs5, a0, 13*SZREG + 5*SZFREG
+ FREG_S fs6, a0, 13*SZREG + 6*SZFREG
+ FREG_S fs7, a0, 13*SZREG + 7*SZFREG
#endif
#if !IS_IN (libc) && IS_IN(rtld)
li.w v0, 0
- jirl zero,ra,0
+ jirl zero, ra, 0
#else
b __sigjmp_save
#endif
--
2.31.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/3] LoongArch: Update hwcap.h to sync with LoongArch kernel.
2023-10-26 13:01 [PATCH 1/3] LoongArch: Unify Register Names caiyinyu
@ 2023-10-26 13:01 ` caiyinyu
2023-10-26 13:01 ` [PATCH 3/3] LoongArch: Delete excessively allocated memory caiyinyu
2023-10-26 13:14 ` [PATCH 1/3] LoongArch: Unify Register Names Adhemerval Zanella Netto
2 siblings, 0 replies; 4+ messages in thread
From: caiyinyu @ 2023-10-26 13:01 UTC (permalink / raw)
To: libc-alpha; +Cc: adhemerval.zanella, xry111, caiyinyu
---
sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h b/sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h
index 5104b69cbc..7acec23d9c 100644
--- a/sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h
+++ b/sysdeps/unix/sysv/linux/loongarch/bits/hwcap.h
@@ -35,3 +35,4 @@
#define HWCAP_LOONGARCH_LBT_X86 (1 << 10)
#define HWCAP_LOONGARCH_LBT_ARM (1 << 11)
#define HWCAP_LOONGARCH_LBT_MIPS (1 << 12)
+#define HWCAP_LOONGARCH_PTW (1 << 13)
--
2.31.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 3/3] LoongArch: Delete excessively allocated memory.
2023-10-26 13:01 [PATCH 1/3] LoongArch: Unify Register Names caiyinyu
2023-10-26 13:01 ` [PATCH 2/3] LoongArch: Update hwcap.h to sync with LoongArch kernel caiyinyu
@ 2023-10-26 13:01 ` caiyinyu
2023-10-26 13:14 ` [PATCH 1/3] LoongArch: Unify Register Names Adhemerval Zanella Netto
2 siblings, 0 replies; 4+ messages in thread
From: caiyinyu @ 2023-10-26 13:01 UTC (permalink / raw)
To: libc-alpha; +Cc: adhemerval.zanella, xry111, caiyinyu
---
sysdeps/loongarch/dl-trampoline.h | 68 +++++++++++++++----------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/sysdeps/loongarch/dl-trampoline.h b/sysdeps/loongarch/dl-trampoline.h
index cb4a287c65..e298439d39 100644
--- a/sysdeps/loongarch/dl-trampoline.h
+++ b/sysdeps/loongarch/dl-trampoline.h
@@ -19,9 +19,9 @@
/* Assembler veneer called from the PLT header code for lazy loading.
The PLT header passes its own args in t0-t2. */
#ifdef USE_LASX
-# define FRAME_SIZE (-((-9 * SZREG - 8 * SZFREG - 8 * SZXREG) & ALMASK))
+# define FRAME_SIZE (-((-9 * SZREG - 8 * SZXREG) & ALMASK))
#elif defined USE_LSX
-# define FRAME_SIZE (-((-9 * SZREG - 8 * SZFREG - 8 * SZVREG) & ALMASK))
+# define FRAME_SIZE (-((-9 * SZREG - 8 * SZVREG) & ALMASK))
#elif !defined __loongarch_soft_float
# define FRAME_SIZE (-((-9 * SZREG - 8 * SZFREG) & ALMASK))
#else
@@ -44,23 +44,23 @@ ENTRY (_dl_runtime_resolve)
REG_S a7, sp, 8*SZREG
#ifdef USE_LASX
- xvst xr0, sp, 9*SZREG + 8*SZFREG + 0*SZXREG
- xvst xr1, sp, 9*SZREG + 8*SZFREG + 1*SZXREG
- xvst xr2, sp, 9*SZREG + 8*SZFREG + 2*SZXREG
- xvst xr3, sp, 9*SZREG + 8*SZFREG + 3*SZXREG
- xvst xr4, sp, 9*SZREG + 8*SZFREG + 4*SZXREG
- xvst xr5, sp, 9*SZREG + 8*SZFREG + 5*SZXREG
- xvst xr6, sp, 9*SZREG + 8*SZFREG + 6*SZXREG
- xvst xr7, sp, 9*SZREG + 8*SZFREG + 7*SZXREG
+ xvst xr0, sp, 9*SZREG + 0*SZXREG
+ xvst xr1, sp, 9*SZREG + 1*SZXREG
+ xvst xr2, sp, 9*SZREG + 2*SZXREG
+ xvst xr3, sp, 9*SZREG + 3*SZXREG
+ xvst xr4, sp, 9*SZREG + 4*SZXREG
+ xvst xr5, sp, 9*SZREG + 5*SZXREG
+ xvst xr6, sp, 9*SZREG + 6*SZXREG
+ xvst xr7, sp, 9*SZREG + 7*SZXREG
#elif defined USE_LSX
- vst vr0, sp, 9*SZREG + 8*SZFREG + 0*SZVREG
- vst vr1, sp, 9*SZREG + 8*SZFREG + 1*SZVREG
- vst vr2, sp, 9*SZREG + 8*SZFREG + 2*SZVREG
- vst vr3, sp, 9*SZREG + 8*SZFREG + 3*SZVREG
- vst vr4, sp, 9*SZREG + 8*SZFREG + 4*SZVREG
- vst vr5, sp, 9*SZREG + 8*SZFREG + 5*SZVREG
- vst vr6, sp, 9*SZREG + 8*SZFREG + 6*SZVREG
- vst vr7, sp, 9*SZREG + 8*SZFREG + 7*SZVREG
+ vst vr0, sp, 9*SZREG + 0*SZVREG
+ vst vr1, sp, 9*SZREG + 1*SZVREG
+ vst vr2, sp, 9*SZREG + 2*SZVREG
+ vst vr3, sp, 9*SZREG + 3*SZVREG
+ vst vr4, sp, 9*SZREG + 4*SZVREG
+ vst vr5, sp, 9*SZREG + 5*SZVREG
+ vst vr6, sp, 9*SZREG + 6*SZVREG
+ vst vr7, sp, 9*SZREG + 7*SZVREG
#elif !defined __loongarch_soft_float
FREG_S fa0, sp, 9*SZREG + 0*SZFREG
FREG_S fa1, sp, 9*SZREG + 1*SZFREG
@@ -92,23 +92,23 @@ ENTRY (_dl_runtime_resolve)
REG_L a7, sp, 8*SZREG
#ifdef USE_LASX
- xvld xr0, sp, 9*SZREG + 8*SZFREG + 0*SZXREG
- xvld xr1, sp, 9*SZREG + 8*SZFREG + 1*SZXREG
- xvld xr2, sp, 9*SZREG + 8*SZFREG + 2*SZXREG
- xvld xr3, sp, 9*SZREG + 8*SZFREG + 3*SZXREG
- xvld xr4, sp, 9*SZREG + 8*SZFREG + 4*SZXREG
- xvld xr5, sp, 9*SZREG + 8*SZFREG + 5*SZXREG
- xvld xr6, sp, 9*SZREG + 8*SZFREG + 6*SZXREG
- xvld xr7, sp, 9*SZREG + 8*SZFREG + 7*SZXREG
+ xvld xr0, sp, 9*SZREG + 0*SZXREG
+ xvld xr1, sp, 9*SZREG + 1*SZXREG
+ xvld xr2, sp, 9*SZREG + 2*SZXREG
+ xvld xr3, sp, 9*SZREG + 3*SZXREG
+ xvld xr4, sp, 9*SZREG + 4*SZXREG
+ xvld xr5, sp, 9*SZREG + 5*SZXREG
+ xvld xr6, sp, 9*SZREG + 6*SZXREG
+ xvld xr7, sp, 9*SZREG + 7*SZXREG
#elif defined USE_LSX
- vld vr0, sp, 9*SZREG + 8*SZFREG + 0*SZVREG
- vld vr1, sp, 9*SZREG + 8*SZFREG + 1*SZVREG
- vld vr2, sp, 9*SZREG + 8*SZFREG + 2*SZVREG
- vld vr3, sp, 9*SZREG + 8*SZFREG + 3*SZVREG
- vld vr4, sp, 9*SZREG + 8*SZFREG + 4*SZVREG
- vld vr5, sp, 9*SZREG + 8*SZFREG + 5*SZVREG
- vld vr6, sp, 9*SZREG + 8*SZFREG + 6*SZVREG
- vld vr7, sp, 9*SZREG + 8*SZFREG + 7*SZVREG
+ vld vr0, sp, 9*SZREG + 0*SZVREG
+ vld vr1, sp, 9*SZREG + 1*SZVREG
+ vld vr2, sp, 9*SZREG + 2*SZVREG
+ vld vr3, sp, 9*SZREG + 3*SZVREG
+ vld vr4, sp, 9*SZREG + 4*SZVREG
+ vld vr5, sp, 9*SZREG + 5*SZVREG
+ vld vr6, sp, 9*SZREG + 6*SZVREG
+ vld vr7, sp, 9*SZREG + 7*SZVREG
#elif !defined __loongarch_soft_float
FREG_L fa0, sp, 9*SZREG + 0*SZFREG
FREG_L fa1, sp, 9*SZREG + 1*SZFREG
--
2.31.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] LoongArch: Unify Register Names.
2023-10-26 13:01 [PATCH 1/3] LoongArch: Unify Register Names caiyinyu
2023-10-26 13:01 ` [PATCH 2/3] LoongArch: Update hwcap.h to sync with LoongArch kernel caiyinyu
2023-10-26 13:01 ` [PATCH 3/3] LoongArch: Delete excessively allocated memory caiyinyu
@ 2023-10-26 13:14 ` Adhemerval Zanella Netto
2 siblings, 0 replies; 4+ messages in thread
From: Adhemerval Zanella Netto @ 2023-10-26 13:14 UTC (permalink / raw)
To: caiyinyu, libc-alpha; +Cc: xry111
On 26/10/23 10:01, caiyinyu wrote:
> ---
> sysdeps/loongarch/__longjmp.S | 20 ++++++++++----------
> sysdeps/loongarch/setjmp.S | 18 +++++++++---------
> 2 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/sysdeps/loongarch/__longjmp.S b/sysdeps/loongarch/__longjmp.S
> index cbde1946a0..e87ce31194 100644
> --- a/sysdeps/loongarch/__longjmp.S
> +++ b/sysdeps/loongarch/__longjmp.S
> @@ -43,18 +43,18 @@ ENTRY (__longjmp)
> REG_L s8, a0, 12*SZREG
>
> #ifndef __loongarch_soft_float
> - FREG_L $f24, a0, 13*SZREG + 0*SZFREG
> - FREG_L $f25, a0, 13*SZREG + 1*SZFREG
> - FREG_L $f26, a0, 13*SZREG + 2*SZFREG
> - FREG_L $f27, a0, 13*SZREG + 3*SZFREG
> - FREG_L $f28, a0, 13*SZREG + 4*SZFREG
> - FREG_L $f29, a0, 13*SZREG + 5*SZFREG
> - FREG_L $f30, a0, 13*SZREG + 6*SZFREG
> - FREG_L $f31, a0, 13*SZREG + 7*SZFREG
> + FREG_L fs0, a0, 13*SZREG + 0*SZFREG
> + FREG_L fs1, a0, 13*SZREG + 1*SZFREG
> + FREG_L fs2, a0, 13*SZREG + 2*SZFREG
> + FREG_L fs3, a0, 13*SZREG + 3*SZFREG
> + FREG_L fs4, a0, 13*SZREG + 4*SZFREG
> + FREG_L fs5, a0, 13*SZREG + 5*SZFREG
> + FREG_L fs6, a0, 13*SZREG + 6*SZFREG
> + FREG_L fs7, a0, 13*SZREG + 7*SZFREG
> #endif
>
> - sltui a0,a1,1
> + sltui a0, a1, 1
> ADD a0, a0, a1 # a0 = (a1 == 0) ? 1 : a1
> - jirl zero,ra,0
> + jirl zero, ra, 0
>
These both seems superfluous and I think we should avoid such changes
since they just make harder to follow git blame.
> END (__longjmp)
> diff --git a/sysdeps/loongarch/setjmp.S b/sysdeps/loongarch/setjmp.S
> index 6c7065cdbb..b6e4f727cd 100644
> --- a/sysdeps/loongarch/setjmp.S
> +++ b/sysdeps/loongarch/setjmp.S
> @@ -52,19 +52,19 @@ ENTRY (__sigsetjmp)
> REG_S s8, a0, 12*SZREG
>
> #ifndef __loongarch_soft_float
> - FREG_S $f24, a0, 13*SZREG + 0*SZFREG
> - FREG_S $f25, a0, 13*SZREG + 1*SZFREG
> - FREG_S $f26, a0, 13*SZREG + 2*SZFREG
> - FREG_S $f27, a0, 13*SZREG + 3*SZFREG
> - FREG_S $f28, a0, 13*SZREG + 4*SZFREG
> - FREG_S $f29, a0, 13*SZREG + 5*SZFREG
> - FREG_S $f30, a0, 13*SZREG + 6*SZFREG
> - FREG_S $f31, a0, 13*SZREG + 7*SZFREG
> + FREG_S fs0, a0, 13*SZREG + 0*SZFREG
> + FREG_S fs1, a0, 13*SZREG + 1*SZFREG
> + FREG_S fs2, a0, 13*SZREG + 2*SZFREG
> + FREG_S fs3, a0, 13*SZREG + 3*SZFREG
> + FREG_S fs4, a0, 13*SZREG + 4*SZFREG
> + FREG_S fs5, a0, 13*SZREG + 5*SZFREG
> + FREG_S fs6, a0, 13*SZREG + 6*SZFREG
> + FREG_S fs7, a0, 13*SZREG + 7*SZFREG
> #endif
>
> #if !IS_IN (libc) && IS_IN(rtld)
> li.w v0, 0
> - jirl zero,ra,0
> + jirl zero, ra, 0
> #else
> b __sigjmp_save
> #endif
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-10-26 13:14 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-10-26 13:01 [PATCH 1/3] LoongArch: Unify Register Names caiyinyu
2023-10-26 13:01 ` [PATCH 2/3] LoongArch: Update hwcap.h to sync with LoongArch kernel caiyinyu
2023-10-26 13:01 ` [PATCH 3/3] LoongArch: Delete excessively allocated memory caiyinyu
2023-10-26 13:14 ` [PATCH 1/3] LoongArch: Unify Register Names Adhemerval Zanella Netto
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