From: Hau Hsu <hau.hsu@sifive.com>
To: libc-alpha@sourceware.org, hongrong.hsu@sifive.com,
jerry.shih@sifive.com, nick.knight@sifive.com,
kito.cheng@sifive.com
Cc: greentime.hu@sifive.com, alice.chan@sifive.com,
andrew@sifive.com, vincent.chen@sifive.com, hau.hsu@sifive.com
Subject: [PATCH v2 1/5] riscv: Enabling vectorized mem*/str* functions in build time
Date: Fri, 21 Apr 2023 15:29:02 +0800 [thread overview]
Message-ID: <20230421072902.14122-1-hau.hsu@sifive.com> (raw)
From: Vincent Chen <vincent.chen@sifive.com>
Let the build selects the vectorized mem*/str* functions when it detects
the compiler supports RISC-V V extension and enables it in this build.
We agree that the these vectorized mem*/str* functions should be
selected by IFUNC. Therefore, this patch is intended as a
**temporary solution** to enable reviewers to evaluate the effectiveness
of these vectorized mem*/str* functions.
---
scripts/build-many-glibcs.py | 10 ++++++++++
sysdeps/riscv/preconfigure | 19 +++++++++++++++++++
sysdeps/riscv/preconfigure.ac | 18 ++++++++++++++++++
sysdeps/riscv/rv32/rvv/Implies | 2 ++
sysdeps/riscv/rv64/rvv/Implies | 2 ++
5 files changed, 51 insertions(+)
create mode 100644 sysdeps/riscv/rv32/rvv/Implies
create mode 100644 sysdeps/riscv/rv64/rvv/Implies
diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py
index 82f8d97281..2fbb91a028 100755
--- a/scripts/build-many-glibcs.py
+++ b/scripts/build-many-glibcs.py
@@ -381,6 +381,11 @@ class Context(object):
variant='rv32imafdc-ilp32d',
gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32d',
'--disable-multilib'])
+ self.add_config(arch='riscv32',
+ os_name='linux-gnu',
+ variant='rv32imafdcv-ilp32d',
+ gcc_cfg=['--with-arch=rv32imafdcv', '--with-abi=ilp32d',
+ '--disable-multilib'])
self.add_config(arch='riscv64',
os_name='linux-gnu',
variant='rv64imac-lp64',
@@ -396,6 +401,11 @@ class Context(object):
variant='rv64imafdc-lp64d',
gcc_cfg=['--with-arch=rv64imafdc', '--with-abi=lp64d',
'--disable-multilib'])
+ self.add_config(arch='riscv64',
+ os_name='linux-gnu',
+ variant='rv64imafdcv-lp64d',
+ gcc_cfg=['--with-arch=rv64imafdcv', '--with-abi=lp64d',
+ '--disable-multilib'])
self.add_config(arch='s390x',
os_name='linux-gnu',
glibcs=[{},
diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure
index 4dedf4b0bb..5ddc195b46 100644
--- a/sysdeps/riscv/preconfigure
+++ b/sysdeps/riscv/preconfigure
@@ -7,6 +7,7 @@ riscv*)
flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'`
float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'`
atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2`
+ vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2`
case "$xlen" in
64 | 32)
@@ -32,6 +33,24 @@ riscv*)
;;
esac
+ case "$vector" in
+ __riscv_vector)
+ case "$flen" in
+ 64)
+ float_machine=rvv
+ ;;
+ *)
+ # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only.
+ ;;
+ esac
+ ;;
+ *)
+ ;;
+ esac
+
+ { $as_echo "$as_me:${as_lineno-$LINENO}: vector $vector flen $flen float_machine $float_machine" >&5
+$as_echo "$as_me: vector $vector flen $flen float_machine $float_machine" >&6;}
+
case "$float_abi" in
soft)
abi_flen=0
diff --git a/sysdeps/riscv/preconfigure.ac b/sysdeps/riscv/preconfigure.ac
index a5c30e0dbf..b6b8bb46e4 100644
--- a/sysdeps/riscv/preconfigure.ac
+++ b/sysdeps/riscv/preconfigure.ac
@@ -7,6 +7,7 @@ riscv*)
flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'`
float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'`
atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2`
+ vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2`
case "$xlen" in
64 | 32)
@@ -32,6 +33,23 @@ riscv*)
;;
esac
+ case "$vector" in
+ __riscv_vector)
+ case "$flen" in
+ 64)
+ float_machine=rvv
+ ;;
+ *)
+ # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only.
+ ;;
+ esac
+ ;;
+ *)
+ ;;
+ esac
+
+ AC_MSG_NOTICE([vector $vector flen $flen float_machine $float_machine])
+
case "$float_abi" in
soft)
abi_flen=0
diff --git a/sysdeps/riscv/rv32/rvv/Implies b/sysdeps/riscv/rv32/rvv/Implies
new file mode 100644
index 0000000000..25ce1df222
--- /dev/null
+++ b/sysdeps/riscv/rv32/rvv/Implies
@@ -0,0 +1,2 @@
+riscv/rv32/rvd
+riscv/rvv
diff --git a/sysdeps/riscv/rv64/rvv/Implies b/sysdeps/riscv/rv64/rvv/Implies
new file mode 100644
index 0000000000..9993bb30e3
--- /dev/null
+++ b/sysdeps/riscv/rv64/rvv/Implies
@@ -0,0 +1,2 @@
+riscv/rv64/rvd
+riscv/rvv
--
2.37.1
next reply other threads:[~2023-04-21 7:29 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-21 7:29 Hau Hsu [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-04-21 7:54 [PATCH v2 0/5] riscv: Vectorized mem*/str* function Hau Hsu
2023-04-21 7:54 ` [PATCH v2 1/5] riscv: Enabling vectorized mem*/str* functions in build time Hau Hsu
[not found] <20230421072733.14047-1-hau.hsu@sifive.com>
2023-04-21 7:27 ` Hau Hsu
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