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* [PATCH v2 1/5] riscv: Enabling vectorized mem*/str* functions in build time
@ 2023-04-21  7:29 Hau Hsu
  0 siblings, 0 replies; 3+ messages in thread
From: Hau Hsu @ 2023-04-21  7:29 UTC (permalink / raw)
  To: libc-alpha, hongrong.hsu, jerry.shih, nick.knight, kito.cheng
  Cc: greentime.hu, alice.chan, andrew, vincent.chen, hau.hsu

From: Vincent Chen <vincent.chen@sifive.com>

Let the build selects the vectorized mem*/str* functions when it detects
the compiler supports RISC-V V extension and enables it in this build.

We agree that the these vectorized mem*/str* functions should be
selected by IFUNC. Therefore, this patch is intended as a
**temporary solution** to enable reviewers to evaluate the effectiveness
of these vectorized mem*/str* functions.
---
 scripts/build-many-glibcs.py   | 10 ++++++++++
 sysdeps/riscv/preconfigure     | 19 +++++++++++++++++++
 sysdeps/riscv/preconfigure.ac  | 18 ++++++++++++++++++
 sysdeps/riscv/rv32/rvv/Implies |  2 ++
 sysdeps/riscv/rv64/rvv/Implies |  2 ++
 5 files changed, 51 insertions(+)
 create mode 100644 sysdeps/riscv/rv32/rvv/Implies
 create mode 100644 sysdeps/riscv/rv64/rvv/Implies

diff --git a/scripts/build-many-glibcs.py b/scripts/build-many-glibcs.py
index 82f8d97281..2fbb91a028 100755
--- a/scripts/build-many-glibcs.py
+++ b/scripts/build-many-glibcs.py
@@ -381,6 +381,11 @@ class Context(object):
                         variant='rv32imafdc-ilp32d',
                         gcc_cfg=['--with-arch=rv32imafdc', '--with-abi=ilp32d',
                                  '--disable-multilib'])
+        self.add_config(arch='riscv32',
+                        os_name='linux-gnu',
+                        variant='rv32imafdcv-ilp32d',
+                        gcc_cfg=['--with-arch=rv32imafdcv', '--with-abi=ilp32d',
+                                 '--disable-multilib'])
         self.add_config(arch='riscv64',
                         os_name='linux-gnu',
                         variant='rv64imac-lp64',
@@ -396,6 +401,11 @@ class Context(object):
                         variant='rv64imafdc-lp64d',
                         gcc_cfg=['--with-arch=rv64imafdc', '--with-abi=lp64d',
                                  '--disable-multilib'])
+        self.add_config(arch='riscv64',
+                        os_name='linux-gnu',
+                        variant='rv64imafdcv-lp64d',
+                        gcc_cfg=['--with-arch=rv64imafdcv', '--with-abi=lp64d',
+                                 '--disable-multilib'])
         self.add_config(arch='s390x',
                         os_name='linux-gnu',
                         glibcs=[{},
diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure
index 4dedf4b0bb..5ddc195b46 100644
--- a/sysdeps/riscv/preconfigure
+++ b/sysdeps/riscv/preconfigure
@@ -7,6 +7,7 @@ riscv*)
     flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'`
     float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'`
     atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2`
+    vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2`
 
     case "$xlen" in
     64 | 32)
@@ -32,6 +33,24 @@ riscv*)
 	;;
     esac
 
+    case "$vector" in
+    __riscv_vector)
+        case "$flen" in
+        64)
+        float_machine=rvv
+        ;;
+        *)
+        # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only.
+        ;;
+        esac
+    ;;
+    *)
+    ;;
+    esac
+
+    { $as_echo "$as_me:${as_lineno-$LINENO}: vector $vector flen $flen float_machine $float_machine" >&5
+$as_echo "$as_me: vector $vector flen $flen float_machine $float_machine" >&6;}
+
     case "$float_abi" in
     soft)
 	abi_flen=0
diff --git a/sysdeps/riscv/preconfigure.ac b/sysdeps/riscv/preconfigure.ac
index a5c30e0dbf..b6b8bb46e4 100644
--- a/sysdeps/riscv/preconfigure.ac
+++ b/sysdeps/riscv/preconfigure.ac
@@ -7,6 +7,7 @@ riscv*)
     flen=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_flen \(.*\)/\1/p'`
     float_abi=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | sed -n 's/^#define __riscv_float_abi_\([^ ]*\) .*/\1/p'`
     atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2`
+    vector=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_vector' | cut -d' ' -f2`
 
     case "$xlen" in
     64 | 32)
@@ -32,6 +33,23 @@ riscv*)
 	;;
     esac
 
+    case "$vector" in
+    __riscv_vector)
+        case "$flen" in
+        64)
+        float_machine=rvv
+        ;;
+        *)
+        # V 1.0 spec requires both F and D extensions, but this may be an older version. Degrade to scalar only.
+        ;;
+        esac
+    ;;
+    *)
+    ;;
+    esac
+
+    AC_MSG_NOTICE([vector $vector flen $flen float_machine $float_machine])
+
     case "$float_abi" in
     soft)
 	abi_flen=0
diff --git a/sysdeps/riscv/rv32/rvv/Implies b/sysdeps/riscv/rv32/rvv/Implies
new file mode 100644
index 0000000000..25ce1df222
--- /dev/null
+++ b/sysdeps/riscv/rv32/rvv/Implies
@@ -0,0 +1,2 @@
+riscv/rv32/rvd
+riscv/rvv
diff --git a/sysdeps/riscv/rv64/rvv/Implies b/sysdeps/riscv/rv64/rvv/Implies
new file mode 100644
index 0000000000..9993bb30e3
--- /dev/null
+++ b/sysdeps/riscv/rv64/rvv/Implies
@@ -0,0 +1,2 @@
+riscv/rv64/rvd
+riscv/rvv
-- 
2.37.1


^ permalink raw reply	[flat|nested] 3+ messages in thread
* [PATCH v2 0/5] riscv: Vectorized mem*/str* function
@ 2023-04-21  7:54 Hau Hsu
  2023-04-21  7:54 ` [PATCH v2 1/5] riscv: Enabling vectorized mem*/str* functions in build time Hau Hsu
  0 siblings, 1 reply; 3+ messages in thread
From: Hau Hsu @ 2023-04-21  7:54 UTC (permalink / raw)
  To: libc-alpha, hongrong.hsu, jerry.shih, nick.knight, kito.cheng
  Cc: greentime.hu, alice.chan, andrew, vincent.chen, hau.hsu

I am submitting version 2 of the patch for adding vectorized mem*/str*
functions for RISC-V. This patch builds upon the previous version (v1)
available at
https://patchwork.sourceware.org/project/glibc/list/?series=17710.

In this version, we have included the __memcmpeq function and set lmul=1
for memcmp, which improves its generality.


Jerry Shih (2):
  riscv: vectorized mem* functions
  riscv: vectorized str* functions

Nick Knight (1):
  riscv: vectorized strchr and strnlen functions

Vincent Chen (1):
  riscv: Enabling vectorized mem*/str* functions in build time

Yun Hsiang (1):
  riscv: add vectorized __memcmpeq

 scripts/build-many-glibcs.py   | 10 ++++
 sysdeps/riscv/preconfigure     | 19 +++++++
 sysdeps/riscv/preconfigure.ac  | 18 +++++++
 sysdeps/riscv/rv32/rvv/Implies |  2 +
 sysdeps/riscv/rv64/rvv/Implies |  2 +
 sysdeps/riscv/rvv/memchr.S     | 63 +++++++++++++++++++++++
 sysdeps/riscv/rvv/memcmp.S     | 71 ++++++++++++++++++++++++++
 sysdeps/riscv/rvv/memcmpeq.S   | 69 +++++++++++++++++++++++++
 sysdeps/riscv/rvv/memcpy.S     | 51 +++++++++++++++++++
 sysdeps/riscv/rvv/memmove.S    | 72 ++++++++++++++++++++++++++
 sysdeps/riscv/rvv/memset.S     | 51 +++++++++++++++++++
 sysdeps/riscv/rvv/strcat.S     | 72 ++++++++++++++++++++++++++
 sysdeps/riscv/rvv/strchr.S     | 53 +++++++++++++++++++
 sysdeps/riscv/rvv/strcmp.S     | 93 ++++++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/strcpy.S     | 56 ++++++++++++++++++++
 sysdeps/riscv/rvv/strlen.S     | 54 ++++++++++++++++++++
 sysdeps/riscv/rvv/strncat.S    | 83 ++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/strncmp.S    | 85 +++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/strncpy.S    | 86 +++++++++++++++++++++++++++++++
 sysdeps/riscv/rvv/strnlen.S    | 56 ++++++++++++++++++++
 20 files changed, 1066 insertions(+)
 create mode 100644 sysdeps/riscv/rv32/rvv/Implies
 create mode 100644 sysdeps/riscv/rv64/rvv/Implies
 create mode 100644 sysdeps/riscv/rvv/memchr.S
 create mode 100644 sysdeps/riscv/rvv/memcmp.S
 create mode 100644 sysdeps/riscv/rvv/memcmpeq.S
 create mode 100644 sysdeps/riscv/rvv/memcpy.S
 create mode 100644 sysdeps/riscv/rvv/memmove.S
 create mode 100644 sysdeps/riscv/rvv/memset.S
 create mode 100644 sysdeps/riscv/rvv/strcat.S
 create mode 100644 sysdeps/riscv/rvv/strchr.S
 create mode 100644 sysdeps/riscv/rvv/strcmp.S
 create mode 100644 sysdeps/riscv/rvv/strcpy.S
 create mode 100644 sysdeps/riscv/rvv/strlen.S
 create mode 100644 sysdeps/riscv/rvv/strncat.S
 create mode 100644 sysdeps/riscv/rvv/strncmp.S
 create mode 100644 sysdeps/riscv/rvv/strncpy.S
 create mode 100644 sysdeps/riscv/rvv/strnlen.S

-- 
2.37.1


^ permalink raw reply	[flat|nested] 3+ messages in thread
[parent not found: <20230421072733.14047-1-hau.hsu@sifive.com>]
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