Re: [PATCH 2/2] riscv: vectorised mem* and str* functions

[Florian Weimer <fweimer@redhat.com>]

* Jeff Law via Libc-alpha:

> On 2/1/23 02:52, Sergei Lewis wrote:
>> Initial implementations of memchr, memcmp, memcpy, memmove, memset, strchr,
>> strcmp, strcpy, strlen, strncmp, strncpy, strnlen, strrchr, strspn
>> targeting the riscv "V" extension, version 1.0
>> The vectorised implementations assume VLENB of at least 128 and at
>> least 32
>> registers (as mandated by the "V" extension spec). They also assume that
>> VLENB is a power of two which is no larger than the page size, and (as
>> vectorised code in glibc for other platforms does) that it is safe to read
>> past null terminators / buffer ends provided one does not cross a page
>> boundary.
>> Signed-off-by: Sergei Lewis <slewis@rivosinc.com>
>> ---
>>   sysdeps/riscv/rv64/rvv/Implies     |   2 +
>>   sysdeps/riscv/rv64/rvv/memchr.S    | 127 +++++++++++++++++++
>>   sysdeps/riscv/rv64/rvv/memcmp.S    |  93 ++++++++++++++
>>   sysdeps/riscv/rv64/rvv/memcpy.S    | 154 +++++++++++++++++++++++
>>   sysdeps/riscv/rv64/rvv/memmove.c   |  22 ++++
>>   sysdeps/riscv/rv64/rvv/memset.S    |  89 ++++++++++++++
>>   sysdeps/riscv/rv64/rvv/strchr.S    |  92 ++++++++++++++
>>   sysdeps/riscv/rv64/rvv/strchrnul.c |  22 ++++
>>   sysdeps/riscv/rv64/rvv/strcmp.S    | 108 +++++++++++++++++
>>   sysdeps/riscv/rv64/rvv/strcpy.S    |  72 +++++++++++
>>   sysdeps/riscv/rv64/rvv/strcspn.c   |  22 ++++
>>   sysdeps/riscv/rv64/rvv/strlen.S    |  67 ++++++++++
>>   sysdeps/riscv/rv64/rvv/strncmp.S   | 104 ++++++++++++++++
>>   sysdeps/riscv/rv64/rvv/strncpy.S   |  96 +++++++++++++++
>>   sysdeps/riscv/rv64/rvv/strnlen.S   |  81 +++++++++++++
>>   sysdeps/riscv/rv64/rvv/strrchr.S   |  88 ++++++++++++++
>>   sysdeps/riscv/rv64/rvv/strspn.S    | 189 +++++++++++++++++++++++++++++
> Does this need to be revamped given the recent push to do more with
> generic code and target specific hooks for mem* and str*?
>
> Shouldn't the implementations be in a multiarch directory?  I would
> fully expect we're going to need both a vector and scalar
> implementation selected by an ifunc.

I think most RISC-V GCC compilers won't have enabled IFUNC support?
Looking at gcc/config.gcc in GCC 12, I see this:

*-*-linux* | *-*-gnu*)
        case ${target} in
        aarch64*-* | arm*-* | i[34567]86-* | powerpc*-* | s390*-* | sparc*-* | x86_64-* | loongarch*-*)
                default_gnu_indirect_function=yes
                ;;
        esac

But maybe that's not the right place to look at?

We have an assembler hack to be able to still build IFUNC resolvers
written in C, but I don't know if this works on RISC-V.

Ideally the GCC defaults would change, too, and well before IFUNCs are
in common use.

Thanks,
Florian