From: Alexey Lapshin <alexey.lapshin@espressif.com>
To: "jjohnstn@redhat.com" <jjohnstn@redhat.com>
Cc: Alexey Gerenkov <alexey.gerenkov@espressif.com>,
"newlib@sourceware.org" <newlib@sourceware.org>,
"jcmvbkbc@gmail.com" <jcmvbkbc@gmail.com>,
Ivan Grokhotkov <ivan@espressif.com>
Subject: Re: [PATCH, RFC v3 0/3] add xtensa port
Date: Tue, 15 Aug 2023 15:07:57 +0000 [thread overview]
Message-ID: <e09e11fb3102fb3f8fa76a6a707805f2157bc738.camel@espressif.com> (raw)
In-Reply-To: <CAOox84uuEamO0FKDu8aQ6uU5ZO5xXk_s8rg0cSn73f4FX=NpNw@mail.gmail.com>
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See in attached files
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[-- Attachment #2: 0002-newlib-add-Xtensa-port.patch --]
[-- Type: text/x-patch; name="0002-newlib-add-Xtensa-port.patch", Size: 294741 bytes --]
From 6024b70c26e6cf662547fda122ac2b08580db150 Mon Sep 17 00:00:00 2001
From: Alexey Lapshin <alexey.lapshin@espressif.com>
Date: Wed, 9 Aug 2023 00:06:30 +0400
Subject: [PATCH 2/3] newlib: add Xtensa port
---
include/xtensa-config.h | 176 ----
include/xtensa-isa-internal.h | 234 -----
include/xtensa-isa.h | 813 ------------------
newlib/Makefile.am | 4 +-
newlib/Makefile.in | 729 ++++++++++------
newlib/configure | 55 ++
newlib/configure.host | 13 +
newlib/libc/acinclude.m4 | 4 +-
newlib/libc/include/machine/ieeefp.h | 4 +
newlib/libc/include/machine/setjmp.h | 29 +
newlib/libc/machine/Makefile.inc | 3 +
newlib/libc/machine/xtensa/Makefile.inc | 8 +
newlib/libc/machine/xtensa/acinclude.m4 | 1 +
newlib/libc/machine/xtensa/memcpy.S | 343 ++++++++
newlib/libc/machine/xtensa/memset.S | 193 +++++
newlib/libc/machine/xtensa/setjmp.S | 252 ++++++
newlib/libc/machine/xtensa/strcmp.S | 353 ++++++++
newlib/libc/machine/xtensa/strcpy.S | 274 ++++++
newlib/libc/machine/xtensa/strlen.S | 115 +++
newlib/libc/machine/xtensa/strncpy.S | 274 ++++++
newlib/libc/machine/xtensa/xtensa-asm.h | 72 ++
newlib/libc/machine/xtensa/xtensa.tex | 72 ++
newlib/libc/sys/Makefile.inc | 3 +
newlib/libc/sys/xtensa/Makefile.inc | 1 +
newlib/libc/sys/xtensa/clibrary_init.c | 42 +
newlib/libc/sys/xtensa/creat.c | 9 +
newlib/libc/sys/xtensa/crt0.c | 16 +
newlib/libc/sys/xtensa/include/fenv.h | 88 ++
newlib/libc/sys/xtensa/include/unistd.h | 13 +
.../xtensa/include/xtensa/config/core-isa.h | 115 +++
newlib/libc/sys/xtensa/isatty.c | 18 +
newlib/libc/sys/xtensa/sys/file.h | 33 +
newlib/libm/acinclude.m4 | 2 +-
newlib/libm/machine/xtensa/Makefile.inc | 6 +
newlib/libm/machine/xtensa/feclearexcept.c | 48 ++
newlib/libm/machine/xtensa/fegetenv.c | 55 ++
newlib/libm/machine/xtensa/fegetexcept.c | 67 ++
newlib/libm/machine/xtensa/fegetexceptflag.c | 63 ++
newlib/libm/machine/xtensa/fegetround.c | 50 ++
newlib/libm/machine/xtensa/feholdexcept.c | 54 ++
newlib/libm/machine/xtensa/feraiseexcept.c | 49 ++
newlib/libm/machine/xtensa/fetestexcept.c | 41 +
newlib/libm/machine/xtensa/feupdateenv.c | 46 +
newlib/libm/math/ef_sqrt.c | 7 +
44 files changed, 3365 insertions(+), 1482 deletions(-)
delete mode 100644 include/xtensa-config.h
delete mode 100644 include/xtensa-isa-internal.h
delete mode 100644 include/xtensa-isa.h
create mode 100644 newlib/libc/machine/xtensa/Makefile.inc
create mode 100644 newlib/libc/machine/xtensa/acinclude.m4
create mode 100644 newlib/libc/machine/xtensa/memcpy.S
create mode 100644 newlib/libc/machine/xtensa/memset.S
create mode 100644 newlib/libc/machine/xtensa/setjmp.S
create mode 100644 newlib/libc/machine/xtensa/strcmp.S
create mode 100644 newlib/libc/machine/xtensa/strcpy.S
create mode 100644 newlib/libc/machine/xtensa/strlen.S
create mode 100644 newlib/libc/machine/xtensa/strncpy.S
create mode 100644 newlib/libc/machine/xtensa/xtensa-asm.h
create mode 100644 newlib/libc/machine/xtensa/xtensa.tex
create mode 100644 newlib/libc/sys/xtensa/Makefile.inc
create mode 100644 newlib/libc/sys/xtensa/clibrary_init.c
create mode 100644 newlib/libc/sys/xtensa/creat.c
create mode 100644 newlib/libc/sys/xtensa/crt0.c
create mode 100644 newlib/libc/sys/xtensa/include/fenv.h
create mode 100644 newlib/libc/sys/xtensa/include/unistd.h
create mode 100644 newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h
create mode 100644 newlib/libc/sys/xtensa/isatty.c
create mode 100644 newlib/libc/sys/xtensa/sys/file.h
create mode 100644 newlib/libm/machine/xtensa/Makefile.inc
create mode 100644 newlib/libm/machine/xtensa/feclearexcept.c
create mode 100644 newlib/libm/machine/xtensa/fegetenv.c
create mode 100644 newlib/libm/machine/xtensa/fegetexcept.c
create mode 100644 newlib/libm/machine/xtensa/fegetexceptflag.c
create mode 100644 newlib/libm/machine/xtensa/fegetround.c
create mode 100644 newlib/libm/machine/xtensa/feholdexcept.c
create mode 100644 newlib/libm/machine/xtensa/feraiseexcept.c
create mode 100644 newlib/libm/machine/xtensa/fetestexcept.c
create mode 100644 newlib/libm/machine/xtensa/feupdateenv.c
diff --git a/include/xtensa-config.h b/include/xtensa-config.h
deleted file mode 100644
index 5ae4c8060..000000000
--- a/include/xtensa-config.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/* Xtensa configuration settings.
- Copyright (C) 2001-2015 Free Software Foundation, Inc.
- Contributed by Bob Wilson (bob.wilson@acm.org) at Tensilica.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but
- WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-
-#ifndef XTENSA_CONFIG_H
-#define XTENSA_CONFIG_H
-
-/* The macros defined here match those with the same names in the Xtensa
- compile-time HAL (Hardware Abstraction Layer). Please refer to the
- Xtensa System Software Reference Manual for documentation of these
- macros. */
-
-#undef XCHAL_HAVE_BE
-#define XCHAL_HAVE_BE 1
-
-#undef XCHAL_HAVE_DENSITY
-#define XCHAL_HAVE_DENSITY 1
-
-#undef XCHAL_HAVE_CONST16
-#define XCHAL_HAVE_CONST16 0
-
-#undef XCHAL_HAVE_ABS
-#define XCHAL_HAVE_ABS 1
-
-#undef XCHAL_HAVE_ADDX
-#define XCHAL_HAVE_ADDX 1
-
-#undef XCHAL_HAVE_L32R
-#define XCHAL_HAVE_L32R 1
-
-#undef XSHAL_USE_ABSOLUTE_LITERALS
-#define XSHAL_USE_ABSOLUTE_LITERALS 0
-
-#undef XSHAL_HAVE_TEXT_SECTION_LITERALS
-#define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */
-
-#undef XCHAL_HAVE_MAC16
-#define XCHAL_HAVE_MAC16 0
-
-#undef XCHAL_HAVE_MUL16
-#define XCHAL_HAVE_MUL16 1
-
-#undef XCHAL_HAVE_MUL32
-#define XCHAL_HAVE_MUL32 1
-
-#undef XCHAL_HAVE_MUL32_HIGH
-#define XCHAL_HAVE_MUL32_HIGH 0
-
-#undef XCHAL_HAVE_DIV32
-#define XCHAL_HAVE_DIV32 1
-
-#undef XCHAL_HAVE_NSA
-#define XCHAL_HAVE_NSA 1
-
-#undef XCHAL_HAVE_MINMAX
-#define XCHAL_HAVE_MINMAX 1
-
-#undef XCHAL_HAVE_SEXT
-#define XCHAL_HAVE_SEXT 1
-
-#undef XCHAL_HAVE_LOOPS
-#define XCHAL_HAVE_LOOPS 1
-
-#undef XCHAL_HAVE_THREADPTR
-#define XCHAL_HAVE_THREADPTR 1
-
-#undef XCHAL_HAVE_RELEASE_SYNC
-#define XCHAL_HAVE_RELEASE_SYNC 1
-
-#undef XCHAL_HAVE_S32C1I
-#define XCHAL_HAVE_S32C1I 1
-
-#undef XCHAL_HAVE_BOOLEANS
-#define XCHAL_HAVE_BOOLEANS 0
-
-#undef XCHAL_HAVE_FP
-#define XCHAL_HAVE_FP 0
-
-#undef XCHAL_HAVE_FP_DIV
-#define XCHAL_HAVE_FP_DIV 0
-
-#undef XCHAL_HAVE_FP_RECIP
-#define XCHAL_HAVE_FP_RECIP 0
-
-#undef XCHAL_HAVE_FP_SQRT
-#define XCHAL_HAVE_FP_SQRT 0
-
-#undef XCHAL_HAVE_FP_RSQRT
-#define XCHAL_HAVE_FP_RSQRT 0
-
-#undef XCHAL_HAVE_DFP_accel
-#define XCHAL_HAVE_DFP_accel 0
-#undef XCHAL_HAVE_WINDOWED
-#define XCHAL_HAVE_WINDOWED 1
-
-#undef XCHAL_NUM_AREGS
-#define XCHAL_NUM_AREGS 32
-
-#undef XCHAL_HAVE_WIDE_BRANCHES
-#define XCHAL_HAVE_WIDE_BRANCHES 0
-
-#undef XCHAL_HAVE_PREDICTED_BRANCHES
-#define XCHAL_HAVE_PREDICTED_BRANCHES 0
-
-
-#undef XCHAL_ICACHE_SIZE
-#define XCHAL_ICACHE_SIZE 16384
-
-#undef XCHAL_DCACHE_SIZE
-#define XCHAL_DCACHE_SIZE 16384
-
-#undef XCHAL_ICACHE_LINESIZE
-#define XCHAL_ICACHE_LINESIZE 32
-
-#undef XCHAL_DCACHE_LINESIZE
-#define XCHAL_DCACHE_LINESIZE 32
-
-#undef XCHAL_ICACHE_LINEWIDTH
-#define XCHAL_ICACHE_LINEWIDTH 5
-
-#undef XCHAL_DCACHE_LINEWIDTH
-#define XCHAL_DCACHE_LINEWIDTH 5
-
-#undef XCHAL_DCACHE_IS_WRITEBACK
-#define XCHAL_DCACHE_IS_WRITEBACK 1
-
-
-#undef XCHAL_HAVE_MMU
-#define XCHAL_HAVE_MMU 1
-
-#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE
-#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12
-
-
-#undef XCHAL_HAVE_DEBUG
-#define XCHAL_HAVE_DEBUG 1
-
-#undef XCHAL_NUM_IBREAK
-#define XCHAL_NUM_IBREAK 2
-
-#undef XCHAL_NUM_DBREAK
-#define XCHAL_NUM_DBREAK 2
-
-#undef XCHAL_DEBUGLEVEL
-#define XCHAL_DEBUGLEVEL 6
-
-
-#undef XCHAL_MAX_INSTRUCTION_SIZE
-#define XCHAL_MAX_INSTRUCTION_SIZE 3
-
-#undef XCHAL_INST_FETCH_WIDTH
-#define XCHAL_INST_FETCH_WIDTH 4
-
-
-#undef XSHAL_ABI
-#undef XTHAL_ABI_WINDOWED
-#undef XTHAL_ABI_CALL0
-#define XSHAL_ABI XTHAL_ABI_WINDOWED
-#define XTHAL_ABI_WINDOWED 0
-#define XTHAL_ABI_CALL0 1
-
-#endif /* !XTENSA_CONFIG_H */
diff --git a/include/xtensa-isa-internal.h b/include/xtensa-isa-internal.h
deleted file mode 100644
index 6c727366b..000000000
--- a/include/xtensa-isa-internal.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/* Internal definitions for configurable Xtensa ISA support.
- Copyright 2003, 2004, 2005, 2008, 2010 Free Software Foundation, Inc.
-
- This file is part of BFD, the Binary File Descriptor library.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
- USA. */
-
-#ifndef XTENSA_ISA_INTERNAL_H
-#define XTENSA_ISA_INTERNAL_H
-
-/* Flags. */
-
-#define XTENSA_OPERAND_IS_REGISTER 0x00000001
-#define XTENSA_OPERAND_IS_PCRELATIVE 0x00000002
-#define XTENSA_OPERAND_IS_INVISIBLE 0x00000004
-#define XTENSA_OPERAND_IS_UNKNOWN 0x00000008
-
-#define XTENSA_OPCODE_IS_BRANCH 0x00000001
-#define XTENSA_OPCODE_IS_JUMP 0x00000002
-#define XTENSA_OPCODE_IS_LOOP 0x00000004
-#define XTENSA_OPCODE_IS_CALL 0x00000008
-
-#define XTENSA_STATE_IS_EXPORTED 0x00000001
-#define XTENSA_STATE_IS_SHARED_OR 0x00000002
-
-#define XTENSA_INTERFACE_HAS_SIDE_EFFECT 0x00000001
-
-/* Function pointer typedefs */
-typedef void (*xtensa_format_encode_fn) (xtensa_insnbuf);
-typedef void (*xtensa_get_slot_fn) (const xtensa_insnbuf, xtensa_insnbuf);
-typedef void (*xtensa_set_slot_fn) (xtensa_insnbuf, const xtensa_insnbuf);
-typedef int (*xtensa_opcode_decode_fn) (const xtensa_insnbuf);
-typedef uint32 (*xtensa_get_field_fn) (const xtensa_insnbuf);
-typedef void (*xtensa_set_field_fn) (xtensa_insnbuf, uint32);
-typedef int (*xtensa_immed_decode_fn) (uint32 *);
-typedef int (*xtensa_immed_encode_fn) (uint32 *);
-typedef int (*xtensa_do_reloc_fn) (uint32 *, uint32);
-typedef int (*xtensa_undo_reloc_fn) (uint32 *, uint32);
-typedef void (*xtensa_opcode_encode_fn) (xtensa_insnbuf);
-typedef int (*xtensa_format_decode_fn) (const xtensa_insnbuf);
-typedef int (*xtensa_length_decode_fn) (const unsigned char *);
-
-typedef struct xtensa_format_internal_struct
-{
- const char *name; /* Instruction format name. */
- int length; /* Instruction length in bytes. */
- xtensa_format_encode_fn encode_fn;
- int num_slots;
- int *slot_id; /* Array[num_slots] of slot IDs. */
-} xtensa_format_internal;
-
-typedef struct xtensa_slot_internal_struct
-{
- const char *name; /* Not necessarily unique. */
- const char *format;
- int position;
- xtensa_get_slot_fn get_fn;
- xtensa_set_slot_fn set_fn;
- xtensa_get_field_fn *get_field_fns; /* Array[field_id]. */
- xtensa_set_field_fn *set_field_fns; /* Array[field_id]. */
- xtensa_opcode_decode_fn opcode_decode_fn;
- const char *nop_name;
-} xtensa_slot_internal;
-
-typedef struct xtensa_operand_internal_struct
-{
- const char *name;
- int field_id;
- xtensa_regfile regfile; /* Register file. */
- int num_regs; /* Usually 1; 2 for reg pairs, etc. */
- uint32 flags; /* See XTENSA_OPERAND_* flags. */
- xtensa_immed_encode_fn encode; /* Encode the operand value. */
- xtensa_immed_decode_fn decode; /* Decode the value from the field. */
- xtensa_do_reloc_fn do_reloc; /* Perform a PC-relative reloc. */
- xtensa_undo_reloc_fn undo_reloc; /* Undo a PC-relative relocation. */
-} xtensa_operand_internal;
-
-typedef struct xtensa_arg_internal_struct
-{
- union {
- int operand_id; /* For normal operands. */
- xtensa_state state; /* For stateOperands. */
- } u;
- char inout; /* Direction: 'i', 'o', or 'm'. */
-} xtensa_arg_internal;
-
-typedef struct xtensa_iclass_internal_struct
-{
- int num_operands; /* Size of "operands" array. */
- xtensa_arg_internal *operands; /* Array[num_operands]. */
-
- int num_stateOperands; /* Size of "stateOperands" array. */
- xtensa_arg_internal *stateOperands; /* Array[num_stateOperands]. */
-
- int num_interfaceOperands; /* Size of "interfaceOperands". */
- xtensa_interface *interfaceOperands; /* Array[num_interfaceOperands]. */
-} xtensa_iclass_internal;
-
-typedef struct xtensa_opcode_internal_struct
-{
- const char *name; /* Opcode mnemonic. */
- int iclass_id; /* Iclass for this opcode. */
- uint32 flags; /* See XTENSA_OPCODE_* flags. */
- xtensa_opcode_encode_fn *encode_fns; /* Array[slot_id]. */
- int num_funcUnit_uses; /* Number of funcUnit_use entries. */
- xtensa_funcUnit_use *funcUnit_uses; /* Array[num_funcUnit_uses]. */
-} xtensa_opcode_internal;
-
-typedef struct xtensa_regfile_internal_struct
-{
- const char *name; /* Full name of the regfile. */
- const char *shortname; /* Abbreviated name. */
- xtensa_regfile parent; /* View parent (or identity). */
- int num_bits; /* Width of the registers. */
- int num_entries; /* Number of registers. */
-} xtensa_regfile_internal;
-
-typedef struct xtensa_interface_internal_struct
-{
- const char *name; /* Interface name. */
- int num_bits; /* Width of the interface. */
- uint32 flags; /* See XTENSA_INTERFACE_* flags. */
- int class_id; /* Class of related interfaces. */
- char inout; /* "i" or "o". */
-} xtensa_interface_internal;
-
-typedef struct xtensa_funcUnit_internal_struct
-{
- const char *name; /* Functional unit name. */
- int num_copies; /* Number of instances. */
-} xtensa_funcUnit_internal;
-
-typedef struct xtensa_state_internal_struct
-{
- const char *name; /* State name. */
- int num_bits; /* Number of state bits. */
- uint32 flags; /* See XTENSA_STATE_* flags. */
-} xtensa_state_internal;
-
-typedef struct xtensa_sysreg_internal_struct
-{
- const char *name; /* Register name. */
- int number; /* Register number. */
- int is_user; /* Non-zero if a "user register". */
-} xtensa_sysreg_internal;
-
-typedef struct xtensa_lookup_entry_struct
-{
- const char *key;
- union
- {
- xtensa_opcode opcode; /* Internal opcode number. */
- xtensa_sysreg sysreg; /* Internal sysreg number. */
- xtensa_state state; /* Internal state number. */
- xtensa_interface intf; /* Internal interface number. */
- xtensa_funcUnit fun; /* Internal funcUnit number. */
- } u;
-} xtensa_lookup_entry;
-
-typedef struct xtensa_isa_internal_struct
-{
- int is_big_endian; /* Endianness. */
- int insn_size; /* Maximum length in bytes. */
- int insnbuf_size; /* Number of insnbuf_words. */
-
- int num_formats;
- xtensa_format_internal *formats;
- xtensa_format_decode_fn format_decode_fn;
- xtensa_length_decode_fn length_decode_fn;
-
- int num_slots;
- xtensa_slot_internal *slots;
-
- int num_fields;
-
- int num_operands;
- xtensa_operand_internal *operands;
-
- int num_iclasses;
- xtensa_iclass_internal *iclasses;
-
- int num_opcodes;
- xtensa_opcode_internal *opcodes;
- xtensa_lookup_entry *opname_lookup_table;
-
- int num_regfiles;
- xtensa_regfile_internal *regfiles;
-
- int num_states;
- xtensa_state_internal *states;
- xtensa_lookup_entry *state_lookup_table;
-
- int num_sysregs;
- xtensa_sysreg_internal *sysregs;
- xtensa_lookup_entry *sysreg_lookup_table;
-
- /* The current Xtensa ISA only supports 256 of each kind of sysreg so
- we can get away with implementing lookups with tables indexed by
- the register numbers. If we ever allow larger sysreg numbers, this
- may have to be reimplemented. The first entry in the following
- arrays corresponds to "special" registers and the second to "user"
- registers. */
- int max_sysreg_num[2];
- xtensa_sysreg *sysreg_table[2];
-
- int num_interfaces;
- xtensa_interface_internal *interfaces;
- xtensa_lookup_entry *interface_lookup_table;
-
- int num_funcUnits;
- xtensa_funcUnit_internal *funcUnits;
- xtensa_lookup_entry *funcUnit_lookup_table;
-
-} xtensa_isa_internal;
-
-extern int xtensa_isa_name_compare (const void *, const void *);
-
-extern xtensa_isa_status xtisa_errno;
-extern char xtisa_error_msg[];
-
-#endif /* !XTENSA_ISA_INTERNAL_H */
diff --git a/include/xtensa-isa.h b/include/xtensa-isa.h
deleted file mode 100644
index c3c740da4..000000000
--- a/include/xtensa-isa.h
+++ /dev/null
@@ -1,813 +0,0 @@
-/* Interface definition for configurable Xtensa ISA support.
- Copyright 2003, 2004, 2005, 2006, 2008, 2010 Free Software Foundation, Inc.
-
- This file is part of BFD, the Binary File Descriptor library.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301,
- USA. */
-
-#ifndef XTENSA_LIBISA_H
-#define XTENSA_LIBISA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Version number: This is intended to help support code that works with
- versions of this library from multiple Xtensa releases. */
-
-#define XTENSA_ISA_VERSION 7000
-
-#ifndef uint32
-#define uint32 unsigned int
-#endif
-
-/* This file defines the interface to the Xtensa ISA library. This
- library contains most of the ISA-specific information for a
- particular Xtensa processor. For example, the set of valid
- instructions, their opcode encodings and operand fields are all
- included here.
-
- This interface basically defines a number of abstract data types.
-
- . an instruction buffer - for holding the raw instruction bits
- . ISA info - information about the ISA as a whole
- . instruction formats - instruction size and slot structure
- . opcodes - information about individual instructions
- . operands - information about register and immediate instruction operands
- . stateOperands - information about processor state instruction operands
- . interfaceOperands - information about interface instruction operands
- . register files - register file information
- . processor states - internal processor state information
- . system registers - "special registers" and "user registers"
- . interfaces - TIE interfaces that are external to the processor
- . functional units - TIE shared functions
-
- The interface defines a set of functions to access each data type.
- With the exception of the instruction buffer, the internal
- representations of the data structures are hidden. All accesses must
- be made through the functions defined here. */
-
-typedef struct xtensa_isa_opaque { int unused; } *xtensa_isa;
-
-
-/* Most of the Xtensa ISA entities (e.g., opcodes, regfiles, etc.) are
- represented here using sequential integers beginning with 0. The
- specific values are only fixed for a particular instantiation of an
- xtensa_isa structure, so these values should only be used
- internally. */
-
-typedef int xtensa_opcode;
-typedef int xtensa_format;
-typedef int xtensa_regfile;
-typedef int xtensa_state;
-typedef int xtensa_sysreg;
-typedef int xtensa_interface;
-typedef int xtensa_funcUnit;
-
-
-/* Define a unique value for undefined items. */
-
-#define XTENSA_UNDEFINED -1
-
-
-/* Overview of using this interface to decode/encode instructions:
-
- Each Xtensa instruction is associated with a particular instruction
- format, where the format defines a fixed number of slots for
- operations. The formats for the core Xtensa ISA have only one slot,
- but FLIX instructions may have multiple slots. Within each slot,
- there is a single opcode and some number of associated operands.
-
- The encoding and decoding functions operate on instruction buffers,
- not on the raw bytes of the instructions. The same instruction
- buffer data structure is used for both entire instructions and
- individual slots in those instructions -- the contents of a slot need
- to be extracted from or inserted into the buffer for the instruction
- as a whole.
-
- Decoding an instruction involves first finding the format, which
- identifies the number of slots, and then decoding each slot
- separately. A slot is decoded by finding the opcode and then using
- the opcode to determine how many operands there are. For example:
-
- xtensa_insnbuf_from_chars
- xtensa_format_decode
- for each slot {
- xtensa_format_get_slot
- xtensa_opcode_decode
- for each operand {
- xtensa_operand_get_field
- xtensa_operand_decode
- }
- }
-
- Encoding an instruction is roughly the same procedure in reverse:
-
- xtensa_format_encode
- for each slot {
- xtensa_opcode_encode
- for each operand {
- xtensa_operand_encode
- xtensa_operand_set_field
- }
- xtensa_format_set_slot
- }
- xtensa_insnbuf_to_chars
-*/
-
-\f
-/* Error handling. */
-
-/* Error codes. The code for the most recent error condition can be
- retrieved with the "errno" function. For any result other than
- xtensa_isa_ok, an error message containing additional information
- about the problem can be retrieved using the "error_msg" function.
- The error messages are stored in an internal buffer, which should
- not be freed and may be overwritten by subsequent operations. */
-
-typedef enum xtensa_isa_status_enum
-{
- xtensa_isa_ok = 0,
- xtensa_isa_bad_format,
- xtensa_isa_bad_slot,
- xtensa_isa_bad_opcode,
- xtensa_isa_bad_operand,
- xtensa_isa_bad_field,
- xtensa_isa_bad_iclass,
- xtensa_isa_bad_regfile,
- xtensa_isa_bad_sysreg,
- xtensa_isa_bad_state,
- xtensa_isa_bad_interface,
- xtensa_isa_bad_funcUnit,
- xtensa_isa_wrong_slot,
- xtensa_isa_no_field,
- xtensa_isa_out_of_memory,
- xtensa_isa_buffer_overflow,
- xtensa_isa_internal_error,
- xtensa_isa_bad_value
-} xtensa_isa_status;
-
-extern xtensa_isa_status
-xtensa_isa_errno (xtensa_isa isa);
-
-extern char *
-xtensa_isa_error_msg (xtensa_isa isa);
-
-
-\f
-/* Instruction buffers. */
-
-typedef uint32 xtensa_insnbuf_word;
-typedef xtensa_insnbuf_word *xtensa_insnbuf;
-
-
-/* Get the size in "insnbuf_words" of the xtensa_insnbuf array. */
-
-extern int
-xtensa_insnbuf_size (xtensa_isa isa);
-
-
-/* Allocate an xtensa_insnbuf of the right size. */
-
-extern xtensa_insnbuf
-xtensa_insnbuf_alloc (xtensa_isa isa);
-
-
-/* Release an xtensa_insnbuf. */
-
-extern void
-xtensa_insnbuf_free (xtensa_isa isa, xtensa_insnbuf buf);
-
-
-/* Conversion between raw memory (char arrays) and our internal
- instruction representation. This is complicated by the Xtensa ISA's
- variable instruction lengths. When converting to chars, the buffer
- must contain a valid instruction so we know how many bytes to copy;
- thus, the "to_chars" function returns the number of bytes copied or
- XTENSA_UNDEFINED on error. The "from_chars" function first reads the
- minimal number of bytes required to decode the instruction length and
- then proceeds to copy the entire instruction into the buffer; if the
- memory does not contain a valid instruction, it copies the maximum
- number of bytes required for the longest Xtensa instruction. The
- "num_chars" argument may be used to limit the number of bytes that
- can be read or written. Otherwise, if "num_chars" is zero, the
- functions may read or write past the end of the code. */
-
-extern int
-xtensa_insnbuf_to_chars (xtensa_isa isa, const xtensa_insnbuf insn,
- unsigned char *cp, int num_chars);
-
-extern void
-xtensa_insnbuf_from_chars (xtensa_isa isa, xtensa_insnbuf insn,
- const unsigned char *cp, int num_chars);
-
-
-\f
-/* ISA information. */
-
-/* Initialize the ISA information. */
-
-extern xtensa_isa
-xtensa_isa_init (xtensa_isa_status *errno_p, char **error_msg_p);
-
-
-/* Deallocate an xtensa_isa structure. */
-
-extern void
-xtensa_isa_free (xtensa_isa isa);
-
-
-/* Get the maximum instruction size in bytes. */
-
-extern int
-xtensa_isa_maxlength (xtensa_isa isa);
-
-
-/* Decode the length in bytes of an instruction in raw memory (not an
- insnbuf). This function reads only the minimal number of bytes
- required to decode the instruction length. Returns
- XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_isa_length_from_chars (xtensa_isa isa, const unsigned char *cp);
-
-
-/* Get the number of stages in the processor's pipeline. The pipeline
- stage values returned by other functions in this library will range
- from 0 to N-1, where N is the value returned by this function.
- Note that the stage numbers used here may not correspond to the
- actual processor hardware, e.g., the hardware may have additional
- stages before stage 0. Returns XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_isa_num_pipe_stages (xtensa_isa isa);
-
-
-/* Get the number of various entities that are defined for this processor. */
-
-extern int
-xtensa_isa_num_formats (xtensa_isa isa);
-
-extern int
-xtensa_isa_num_opcodes (xtensa_isa isa);
-
-extern int
-xtensa_isa_num_regfiles (xtensa_isa isa);
-
-extern int
-xtensa_isa_num_states (xtensa_isa isa);
-
-extern int
-xtensa_isa_num_sysregs (xtensa_isa isa);
-
-extern int
-xtensa_isa_num_interfaces (xtensa_isa isa);
-
-extern int
-xtensa_isa_num_funcUnits (xtensa_isa isa);
-
-
-\f
-/* Instruction formats. */
-
-/* Get the name of a format. Returns null on error. */
-
-extern const char *
-xtensa_format_name (xtensa_isa isa, xtensa_format fmt);
-
-
-/* Given a format name, return the format number. Returns
- XTENSA_UNDEFINED if the name is not a valid format. */
-
-extern xtensa_format
-xtensa_format_lookup (xtensa_isa isa, const char *fmtname);
-
-
-/* Decode the instruction format from a binary instruction buffer.
- Returns XTENSA_UNDEFINED if the format is not recognized. */
-
-extern xtensa_format
-xtensa_format_decode (xtensa_isa isa, const xtensa_insnbuf insn);
-
-
-/* Set the instruction format field(s) in a binary instruction buffer.
- All the other fields are set to zero. Returns non-zero on error. */
-
-extern int
-xtensa_format_encode (xtensa_isa isa, xtensa_format fmt, xtensa_insnbuf insn);
-
-
-/* Find the length (in bytes) of an instruction. Returns
- XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_format_length (xtensa_isa isa, xtensa_format fmt);
-
-
-/* Get the number of slots in an instruction. Returns XTENSA_UNDEFINED
- on error. */
-
-extern int
-xtensa_format_num_slots (xtensa_isa isa, xtensa_format fmt);
-
-
-/* Get the opcode for a no-op in a particular slot.
- Returns XTENSA_UNDEFINED on error. */
-
-extern xtensa_opcode
-xtensa_format_slot_nop_opcode (xtensa_isa isa, xtensa_format fmt, int slot);
-
-
-/* Get the bits for a specified slot out of an insnbuf for the
- instruction as a whole and put them into an insnbuf for that one
- slot, and do the opposite to set a slot. Return non-zero on error. */
-
-extern int
-xtensa_format_get_slot (xtensa_isa isa, xtensa_format fmt, int slot,
- const xtensa_insnbuf insn, xtensa_insnbuf slotbuf);
-
-extern int
-xtensa_format_set_slot (xtensa_isa isa, xtensa_format fmt, int slot,
- xtensa_insnbuf insn, const xtensa_insnbuf slotbuf);
-
-
-\f
-/* Opcode information. */
-
-/* Translate a mnemonic name to an opcode. Returns XTENSA_UNDEFINED if
- the name is not a valid opcode mnemonic. */
-
-extern xtensa_opcode
-xtensa_opcode_lookup (xtensa_isa isa, const char *opname);
-
-
-/* Decode the opcode for one instruction slot from a binary instruction
- buffer. Returns the opcode or XTENSA_UNDEFINED if the opcode is
- illegal. */
-
-extern xtensa_opcode
-xtensa_opcode_decode (xtensa_isa isa, xtensa_format fmt, int slot,
- const xtensa_insnbuf slotbuf);
-
-
-/* Set the opcode field(s) for an instruction slot. All other fields
- in the slot are set to zero. Returns non-zero if the opcode cannot
- be encoded. */
-
-extern int
-xtensa_opcode_encode (xtensa_isa isa, xtensa_format fmt, int slot,
- xtensa_insnbuf slotbuf, xtensa_opcode opc);
-
-
-/* Get the mnemonic name for an opcode. Returns null on error. */
-
-extern const char *
-xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc);
-
-
-/* Check various properties of opcodes. These functions return 0 if
- the condition is false, 1 if the condition is true, and
- XTENSA_UNDEFINED on error. The instructions are classified as
- follows:
-
- branch: conditional branch; may fall through to next instruction (B*)
- jump: unconditional branch (J, JX, RET*, RF*)
- loop: zero-overhead loop (LOOP*)
- call: unconditional call; control returns to next instruction (CALL*)
-
- For the opcodes that affect control flow in some way, the branch
- target may be specified by an immediate operand or it may be an
- address stored in a register. You can distinguish these by
- checking if the instruction has a PC-relative immediate
- operand. */
-
-extern int
-xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc);
-
-extern int
-xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc);
-
-extern int
-xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc);
-
-extern int
-xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc);
-
-
-/* Find the number of ordinary operands, state operands, and interface
- operands for an instruction. These return XTENSA_UNDEFINED on
- error. */
-
-extern int
-xtensa_opcode_num_operands (xtensa_isa isa, xtensa_opcode opc);
-
-extern int
-xtensa_opcode_num_stateOperands (xtensa_isa isa, xtensa_opcode opc);
-
-extern int
-xtensa_opcode_num_interfaceOperands (xtensa_isa isa, xtensa_opcode opc);
-
-
-/* Get functional unit usage requirements for an opcode. Each "use"
- is identified by a <functional unit, pipeline stage> pair. The
- "num_funcUnit_uses" function returns the number of these "uses" or
- XTENSA_UNDEFINED on error. The "funcUnit_use" function returns
- a pointer to a "use" pair or null on error. */
-
-typedef struct xtensa_funcUnit_use_struct
-{
- xtensa_funcUnit unit;
- int stage;
-} xtensa_funcUnit_use;
-
-extern int
-xtensa_opcode_num_funcUnit_uses (xtensa_isa isa, xtensa_opcode opc);
-
-extern xtensa_funcUnit_use *
-xtensa_opcode_funcUnit_use (xtensa_isa isa, xtensa_opcode opc, int u);
-
-
-\f
-/* Operand information. */
-
-/* Get the name of an operand. Returns null on error. */
-
-extern const char *
-xtensa_operand_name (xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/* Some operands are "invisible", i.e., not explicitly specified in
- assembly language. When assembling an instruction, you need not set
- the values of invisible operands, since they are either hardwired or
- derived from other field values. The values of invisible operands
- can be examined in the same way as other operands, but remember that
- an invisible operand may get its value from another visible one, so
- the entire instruction must be available before examining the
- invisible operand values. This function returns 1 if an operand is
- visible, 0 if it is invisible, or XTENSA_UNDEFINED on error. Note
- that whether an operand is visible is orthogonal to whether it is
- "implicit", i.e., whether it is encoded in a field in the
- instruction. */
-
-extern int
-xtensa_operand_is_visible (xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/* Check if an operand is an input ('i'), output ('o'), or inout ('m')
- operand. Note: The output operand of a conditional assignment
- (e.g., movnez) appears here as an inout ('m') even if it is declared
- in the TIE code as an output ('o'); this allows the compiler to
- properly handle register allocation for conditional assignments.
- Returns 0 on error. */
-
-extern char
-xtensa_operand_inout (xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/* Get and set the raw (encoded) value of the field for the specified
- operand. The "set" function does not check if the value fits in the
- field; that is done by the "encode" function below. Both of these
- functions return non-zero on error, e.g., if the field is not defined
- for the specified slot. */
-
-extern int
-xtensa_operand_get_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
- xtensa_format fmt, int slot,
- const xtensa_insnbuf slotbuf, uint32 *valp);
-
-extern int
-xtensa_operand_set_field (xtensa_isa isa, xtensa_opcode opc, int opnd,
- xtensa_format fmt, int slot,
- xtensa_insnbuf slotbuf, uint32 val);
-
-
-/* Encode and decode operands. The raw bits in the operand field may
- be encoded in a variety of different ways. These functions hide
- the details of that encoding. The result values are returned through
- the argument pointer. The return value is non-zero on error. */
-
-extern int
-xtensa_operand_encode (xtensa_isa isa, xtensa_opcode opc, int opnd,
- uint32 *valp);
-
-extern int
-xtensa_operand_decode (xtensa_isa isa, xtensa_opcode opc, int opnd,
- uint32 *valp);
-
-
-/* An operand may be either a register operand or an immediate of some
- sort (e.g., PC-relative or not). The "is_register" function returns
- 0 if the operand is an immediate, 1 if it is a register, and
- XTENSA_UNDEFINED on error. The "regfile" function returns the
- regfile for a register operand, or XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_operand_is_register (xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-extern xtensa_regfile
-xtensa_operand_regfile (xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/* Register operands may span multiple consecutive registers, e.g., a
- 64-bit data type may occupy two 32-bit registers. Only the first
- register is encoded in the operand field. This function specifies
- the number of consecutive registers occupied by this operand. For
- non-register operands, the return value is undefined. Returns
- XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_operand_num_regs (xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/* Some register operands do not completely identify the register being
- accessed. For example, the operand value may be added to an internal
- state value. By definition, this implies that the corresponding
- regfile is not allocatable. Unknown registers should generally be
- treated with worst-case assumptions. The function returns 0 if the
- register value is unknown, 1 if known, and XTENSA_UNDEFINED on
- error. */
-
-extern int
-xtensa_operand_is_known_reg (xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/* Check if an immediate operand is PC-relative. Returns 0 for register
- operands and non-PC-relative immediates, 1 for PC-relative
- immediates, and XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_operand_is_PCrelative (xtensa_isa isa, xtensa_opcode opc, int opnd);
-
-
-/* For PC-relative offset operands, the interpretation of the offset may
- vary between opcodes, e.g., is it relative to the current PC or that
- of the next instruction? The following functions are defined to
- perform PC-relative relocations and to undo them (as in the
- disassembler). The "do_reloc" function takes the desired address
- value and the PC of the current instruction and sets the value to the
- corresponding PC-relative offset (which can then be encoded and
- stored into the operand field). The "undo_reloc" function takes the
- unencoded offset value and the current PC and sets the value to the
- appropriate address. The return values are non-zero on error. Note
- that these functions do not replace the encode/decode functions; the
- operands must be encoded/decoded separately and the encode functions
- are responsible for detecting invalid operand values. */
-
-extern int
-xtensa_operand_do_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
- uint32 *valp, uint32 pc);
-
-extern int
-xtensa_operand_undo_reloc (xtensa_isa isa, xtensa_opcode opc, int opnd,
- uint32 *valp, uint32 pc);
-
-
-\f
-/* State Operands. */
-
-/* Get the state accessed by a state operand. Returns XTENSA_UNDEFINED
- on error. */
-
-extern xtensa_state
-xtensa_stateOperand_state (xtensa_isa isa, xtensa_opcode opc, int stOp);
-
-
-/* Check if a state operand is an input ('i'), output ('o'), or inout
- ('m') operand. Returns 0 on error. */
-
-extern char
-xtensa_stateOperand_inout (xtensa_isa isa, xtensa_opcode opc, int stOp);
-
-
-\f
-/* Interface Operands. */
-
-/* Get the external interface accessed by an interface operand.
- Returns XTENSA_UNDEFINED on error. */
-
-extern xtensa_interface
-xtensa_interfaceOperand_interface (xtensa_isa isa, xtensa_opcode opc,
- int ifOp);
-
-
-\f
-/* Register Files. */
-
-/* Regfiles include both "real" regfiles and "views", where a view
- allows a group of adjacent registers in a real "parent" regfile to be
- viewed as a single register. A regfile view has all the same
- properties as its parent except for its (long) name, bit width, number
- of entries, and default ctype. You can use the parent function to
- distinguish these two classes. */
-
-/* Look up a regfile by either its name or its abbreviated "short name".
- Returns XTENSA_UNDEFINED on error. The "lookup_shortname" function
- ignores "view" regfiles since they always have the same shortname as
- their parents. */
-
-extern xtensa_regfile
-xtensa_regfile_lookup (xtensa_isa isa, const char *name);
-
-extern xtensa_regfile
-xtensa_regfile_lookup_shortname (xtensa_isa isa, const char *shortname);
-
-
-/* Get the name or abbreviated "short name" of a regfile.
- Returns null on error. */
-
-extern const char *
-xtensa_regfile_name (xtensa_isa isa, xtensa_regfile rf);
-
-extern const char *
-xtensa_regfile_shortname (xtensa_isa isa, xtensa_regfile rf);
-
-
-/* Get the parent regfile of a "view" regfile. If the regfile is not a
- view, the result is the same as the input parameter. Returns
- XTENSA_UNDEFINED on error. */
-
-extern xtensa_regfile
-xtensa_regfile_view_parent (xtensa_isa isa, xtensa_regfile rf);
-
-
-/* Get the bit width of a regfile or regfile view.
- Returns XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_regfile_num_bits (xtensa_isa isa, xtensa_regfile rf);
-
-
-/* Get the number of regfile entries. Returns XTENSA_UNDEFINED on
- error. */
-
-extern int
-xtensa_regfile_num_entries (xtensa_isa isa, xtensa_regfile rf);
-
-
-\f
-/* Processor States. */
-
-/* Look up a state by name. Returns XTENSA_UNDEFINED on error. */
-
-extern xtensa_state
-xtensa_state_lookup (xtensa_isa isa, const char *name);
-
-
-/* Get the name for a processor state. Returns null on error. */
-
-extern const char *
-xtensa_state_name (xtensa_isa isa, xtensa_state st);
-
-
-/* Get the bit width for a processor state.
- Returns XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_state_num_bits (xtensa_isa isa, xtensa_state st);
-
-
-/* Check if a state is exported from the processor core. Returns 0 if
- the condition is false, 1 if the condition is true, and
- XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_state_is_exported (xtensa_isa isa, xtensa_state st);
-
-
-/* Check for a "shared_or" state. Returns 0 if the condition is false,
- 1 if the condition is true, and XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_state_is_shared_or (xtensa_isa isa, xtensa_state st);
-
-
-\f
-/* Sysregs ("special registers" and "user registers"). */
-
-/* Look up a register by its number and whether it is a "user register"
- or a "special register". Returns XTENSA_UNDEFINED if the sysreg does
- not exist. */
-
-extern xtensa_sysreg
-xtensa_sysreg_lookup (xtensa_isa isa, int num, int is_user);
-
-
-/* Check if there exists a sysreg with a given name.
- If not, this function returns XTENSA_UNDEFINED. */
-
-extern xtensa_sysreg
-xtensa_sysreg_lookup_name (xtensa_isa isa, const char *name);
-
-
-/* Get the name of a sysreg. Returns null on error. */
-
-extern const char *
-xtensa_sysreg_name (xtensa_isa isa, xtensa_sysreg sysreg);
-
-
-/* Get the register number. Returns XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_sysreg_number (xtensa_isa isa, xtensa_sysreg sysreg);
-
-
-/* Check if a sysreg is a "special register" or a "user register".
- Returns 0 for special registers, 1 for user registers and
- XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_sysreg_is_user (xtensa_isa isa, xtensa_sysreg sysreg);
-
-
-\f
-/* Interfaces. */
-
-/* Find an interface by name. The return value is XTENSA_UNDEFINED if
- the specified interface is not found. */
-
-extern xtensa_interface
-xtensa_interface_lookup (xtensa_isa isa, const char *ifname);
-
-
-/* Get the name of an interface. Returns null on error. */
-
-extern const char *
-xtensa_interface_name (xtensa_isa isa, xtensa_interface intf);
-
-
-/* Get the bit width for an interface.
- Returns XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_interface_num_bits (xtensa_isa isa, xtensa_interface intf);
-
-
-/* Check if an interface is an input ('i') or output ('o') with respect
- to the Xtensa processor core. Returns 0 on error. */
-
-extern char
-xtensa_interface_inout (xtensa_isa isa, xtensa_interface intf);
-
-
-/* Check if accessing an interface has potential side effects.
- Currently "data" interfaces have side effects and "control"
- interfaces do not. Returns 1 if there are side effects, 0 if not,
- and XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_interface_has_side_effect (xtensa_isa isa, xtensa_interface intf);
-
-
-/* Some interfaces may be related such that accessing one interface
- has side effects on a set of related interfaces. The interfaces
- are partitioned into equivalence classes of related interfaces, and
- each class is assigned a unique identifier number. This function
- returns the class identifier for an interface, or XTENSA_UNDEFINED
- on error. These identifiers can be compared to determine if two
- interfaces are related; the specific values of the identifiers have
- no particular meaning otherwise. */
-
-extern int
-xtensa_interface_class_id (xtensa_isa isa, xtensa_interface intf);
-
-
-\f
-/* Functional Units. */
-
-/* Find a functional unit by name. The return value is XTENSA_UNDEFINED if
- the specified unit is not found. */
-
-extern xtensa_funcUnit
-xtensa_funcUnit_lookup (xtensa_isa isa, const char *fname);
-
-
-/* Get the name of a functional unit. Returns null on error. */
-
-extern const char *
-xtensa_funcUnit_name (xtensa_isa isa, xtensa_funcUnit fun);
-
-
-/* Functional units may be replicated. See how many instances of a
- particular function unit exist. Returns XTENSA_UNDEFINED on error. */
-
-extern int
-xtensa_funcUnit_num_copies (xtensa_isa isa, xtensa_funcUnit fun);
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* XTENSA_LIBISA_H */
diff --git a/newlib/Makefile.am b/newlib/Makefile.am
index 126cf24c1..e29607ccd 100644
--- a/newlib/Makefile.am
+++ b/newlib/Makefile.am
@@ -240,7 +240,7 @@ stmp-targ-include: config.status
$(AM_V_at)s=machine/$(machine_dir)/include d= $(TARG_INCLUDE_CP_DIR)
$(AM_V_at)s=sys/$(sys_dir)/include d= $(TARG_INCLUDE_CP_DIR)
$(AM_V_at)for i in $(call rwildcard,$(srcdir)/libc/sys/$(sys_dir)/include/,*.h); do \
- f=`echo $$i | sed s:$(srcdir)/libc/sys/$(sys_dir)/include/::`; \
+ f=`echo $$i | sed s:^$(srcdir)/libc/sys/$(sys_dir)/include/::`; \
$(MKDIR_P) targ-include/`dirname $$f`; \
cp $$i targ-include/$$f; \
done
@@ -334,7 +334,7 @@ install-data-local: install-toollibLIBRARIES install-multi $(INSTALL_DATA_LOCAL)
else true; fi ; \
done ; \
for i in $(call rwildcard,$(srcdir)/libc/sys/$(sys_dir)/include/,*.h); do \
- f=`echo $$i | sed s:$(srcdir)/libc/sys/$(sys_dir)/include/::`; \
+ f=`echo $$i | sed s:^$(srcdir)/libc/sys/$(sys_dir)/include/::`; \
$(MKDIR_P) $(DESTDIR)$(tooldir)/`dirname $$f`; \
$(INSTALL_DATA) $$i $(DESTDIR)$(tooldir)/`dirname $$f`; \
done ; \
diff --git a/newlib/Makefile.in b/newlib/Makefile.in
index bfbc2c227..b374c913f 100644
--- a/newlib/Makefile.in
+++ b/newlib/Makefile.in
@@ -585,8 +585,9 @@ check_PROGRAMS =
@HAVE_LIBC_SYS_TIRTOS_DIR_TRUE@am__append_62 = libc/sys/tirtos/lock.c
@HAVE_LIBC_SYS_W65_DIR_TRUE@am__append_63 = libc/sys/w65/syscalls.c libc/sys/w65/trap.c
-@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__append_64 = libc/sys/z8ksim/glue.c
-@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__append_65 = \
+@HAVE_LIBC_SYS_XTENSA_DIR_TRUE@am__append_64 = libc/sys/xtensa/creat.c libc/sys/xtensa/isatty.c libc/sys/xtensa/clibrary_init.c
+@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__append_65 = libc/sys/z8ksim/glue.c
+@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__append_66 = \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memchr-stub.c \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memchr.S \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memcmp-stub.c \
@@ -619,7 +620,7 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/strrchr-stub.c \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/strrchr.S
-@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__append_66 = \
+@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__append_67 = \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/abort.c \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/exit.c \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/atexit.c \
@@ -627,7 +628,7 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/getreent.c \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/signal.c
-@HAVE_LIBC_MACHINE_ARC_TRUE@am__append_67 = \
+@HAVE_LIBC_MACHINE_ARC_TRUE@am__append_68 = \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp.S \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp-bs-norm.S \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp-stub.c \
@@ -659,7 +660,7 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/strncpy-stub.c \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/strncpy-bs.S
-@HAVE_LIBC_MACHINE_ARM_TRUE@am__append_68 = \
+@HAVE_LIBC_MACHINE_ARM_TRUE@am__append_69 = \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/setjmp.S libc/machine/arm/strcmp.S libc/machine/arm/strcpy.c \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/aeabi_memcpy.c libc/machine/arm/aeabi_memcpy-armv7a.S \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/aeabi_memmove.c libc/machine/arm/aeabi_memmove-soft.S \
@@ -671,39 +672,39 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/strlen-stub.c \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/strlen.S
-@HAVE_LIBC_MACHINE_BFIN_TRUE@am__append_69 = libc/machine/bfin/setjmp.S libc/machine/bfin/longjmp.S
-@HAVE_LIBC_MACHINE_CR16_TRUE@am__append_70 = libc/machine/cr16/setjmp.S libc/machine/cr16/getenv.c
-@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_71 = libc/machine/cris/setjmp.c libc/machine/cris/memcpy.c libc/machine/cris/memset.c libc/machine/cris/memmove.c libc/machine/cris/libcdtor.c
+@HAVE_LIBC_MACHINE_BFIN_TRUE@am__append_70 = libc/machine/bfin/setjmp.S libc/machine/bfin/longjmp.S
+@HAVE_LIBC_MACHINE_CR16_TRUE@am__append_71 = libc/machine/cr16/setjmp.S libc/machine/cr16/getenv.c
+@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_72 = libc/machine/cris/setjmp.c libc/machine/cris/memcpy.c libc/machine/cris/memset.c libc/machine/cris/memmove.c libc/machine/cris/libcdtor.c
# We also make a library with just the useful
# machine-but-not-system-specific functions, usable as an add-on
# by itself together with e.g. uclibc.
-@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_72 = libc/machine/cris/libic.a
-@HAVE_LIBC_MACHINE_CRX_TRUE@am__append_73 = libc/machine/crx/setjmp.S libc/machine/crx/getenv.c
-@HAVE_LIBC_MACHINE_CSKY_TRUE@am__append_74 = libc/machine/csky/setjmp.S
-@HAVE_LIBC_MACHINE_D10V_TRUE@am__append_75 = libc/machine/d10v/setjmp.S
-@HAVE_LIBC_MACHINE_D30V_TRUE@am__append_76 = libc/machine/d30v/setjmp.S
-@HAVE_LIBC_MACHINE_EPIPHANY_TRUE@am__append_77 = libc/machine/epiphany/setjmp.S
-@HAVE_LIBC_MACHINE_FR30_TRUE@am__append_78 = libc/machine/fr30/setjmp.S
-@HAVE_LIBC_MACHINE_FRV_TRUE@am__append_79 = libc/machine/frv/setjmp.S
-@HAVE_LIBC_MACHINE_FT32_TRUE@am__append_80 = libc/machine/ft32/setjmp.S libc/machine/ft32/strlen.S libc/machine/ft32/memcpy.S libc/machine/ft32/strcmp.S libc/machine/ft32/memset.S libc/machine/ft32/strcpy.S
-@HAVE_LIBC_MACHINE_H8300_TRUE@am__append_81 = \
+@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_73 = libc/machine/cris/libic.a
+@HAVE_LIBC_MACHINE_CRX_TRUE@am__append_74 = libc/machine/crx/setjmp.S libc/machine/crx/getenv.c
+@HAVE_LIBC_MACHINE_CSKY_TRUE@am__append_75 = libc/machine/csky/setjmp.S
+@HAVE_LIBC_MACHINE_D10V_TRUE@am__append_76 = libc/machine/d10v/setjmp.S
+@HAVE_LIBC_MACHINE_D30V_TRUE@am__append_77 = libc/machine/d30v/setjmp.S
+@HAVE_LIBC_MACHINE_EPIPHANY_TRUE@am__append_78 = libc/machine/epiphany/setjmp.S
+@HAVE_LIBC_MACHINE_FR30_TRUE@am__append_79 = libc/machine/fr30/setjmp.S
+@HAVE_LIBC_MACHINE_FRV_TRUE@am__append_80 = libc/machine/frv/setjmp.S
+@HAVE_LIBC_MACHINE_FT32_TRUE@am__append_81 = libc/machine/ft32/setjmp.S libc/machine/ft32/strlen.S libc/machine/ft32/memcpy.S libc/machine/ft32/strcmp.S libc/machine/ft32/memset.S libc/machine/ft32/strcpy.S
+@HAVE_LIBC_MACHINE_H8300_TRUE@am__append_82 = \
@HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/reg_memcpy.S libc/machine/h8300/reg_memset.S libc/machine/h8300/strcmp.S libc/machine/h8300/memcpy.S libc/machine/h8300/memset.S \
@HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/setjmp.S libc/machine/h8300/h8sx_strcpy.S
-@HAVE_LIBC_MACHINE_H8500_TRUE@am__append_82 = libc/machine/h8500/divsi3.c libc/machine/h8500/mulsi3.c libc/machine/h8500/divhi3.S libc/machine/h8500/shifts.c libc/machine/h8500/cmpsi.c libc/machine/h8500/psi.S libc/machine/h8500/setjmp.S
-@HAVE_LIBC_MACHINE_HPPA_TRUE@am__append_83 = \
+@HAVE_LIBC_MACHINE_H8500_TRUE@am__append_83 = libc/machine/h8500/divsi3.c libc/machine/h8500/mulsi3.c libc/machine/h8500/divhi3.S libc/machine/h8500/shifts.c libc/machine/h8500/cmpsi.c libc/machine/h8500/psi.S libc/machine/h8500/setjmp.S
+@HAVE_LIBC_MACHINE_HPPA_TRUE@am__append_84 = \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/memchr.S libc/machine/hppa/memcmp.S libc/machine/hppa/memcpy.S libc/machine/hppa/memset.S \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/setjmp.S \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/strcat.S libc/machine/hppa/strcmp.S \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/strcpy.S libc/machine/hppa/strlen.S libc/machine/hppa/strncat.S libc/machine/hppa/strncmp.S libc/machine/hppa/strncpy.S
-@HAVE_LIBC_MACHINE_I386_TRUE@@MACH_ADD_SETJMP_TRUE@am__append_84 = libc/machine/i386/setjmp.S
-@HAVE_LIBC_MACHINE_I386_TRUE@am__append_85 = \
+@HAVE_LIBC_MACHINE_I386_TRUE@@MACH_ADD_SETJMP_TRUE@am__append_85 = libc/machine/i386/setjmp.S
+@HAVE_LIBC_MACHINE_I386_TRUE@am__append_86 = \
@HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/memchr.S libc/machine/i386/memcmp.S libc/machine/i386/memcpy.S libc/machine/i386/memset.S libc/machine/i386/strchr.S \
@HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/memmove.S libc/machine/i386/strlen.S libc/machine/i386/i386mach.h
-@HAVE_LIBC_MACHINE_I960_TRUE@am__append_86 = \
+@HAVE_LIBC_MACHINE_I960_TRUE@am__append_87 = \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memccpy_ca.S \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memccpy.S \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memchr_ca.S \
@@ -733,43 +734,43 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/strpbrk.S \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/strrchr.S
-@HAVE_LIBC_MACHINE_IQ2000_TRUE@am__append_87 = libc/machine/iq2000/setjmp.S
-@HAVE_LIBC_MACHINE_LM32_TRUE@am__append_88 = libc/machine/lm32/setjmp.S
-@HAVE_LIBC_MACHINE_M32C_TRUE@am__append_89 = libc/machine/m32c/setjmp.S
-@HAVE_LIBC_MACHINE_M32R_TRUE@am__append_90 = libc/machine/m32r/setjmp.S
-@HAVE_LIBC_MACHINE_M68HC11_TRUE@am__append_91 = libc/machine/m68hc11/setjmp.S
-@HAVE_LIBC_MACHINE_M68K_TRUE@am__append_92 = libc/machine/m68k/setjmp.S libc/machine/m68k/strcpy.c libc/machine/m68k/strlen.c libc/machine/m68k/memcpy.S libc/machine/m68k/memset.S
-@HAVE_LIBC_MACHINE_M88K_TRUE@am__append_93 = libc/machine/m88k/setjmp.S
-@HAVE_LIBC_MACHINE_MEP_TRUE@am__append_94 = libc/machine/mep/setjmp.S
-@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@am__append_95 = libc/machine/microblaze/strlen.c libc/machine/microblaze/strcmp.c libc/machine/microblaze/strcpy.c libc/machine/microblaze/setjmp.S libc/machine/microblaze/longjmp.S
-@HAVE_LIBC_MACHINE_MIPS_TRUE@am__append_96 = libc/machine/mips/setjmp.S libc/machine/mips/strlen.c libc/machine/mips/strcmp.S libc/machine/mips/strncpy.c libc/machine/mips/memset.S libc/machine/mips/memcpy.S
-@HAVE_LIBC_MACHINE_MN10200_TRUE@am__append_97 = libc/machine/mn10200/setjmp.S
-@HAVE_LIBC_MACHINE_MN10300_TRUE@am__append_98 = \
+@HAVE_LIBC_MACHINE_IQ2000_TRUE@am__append_88 = libc/machine/iq2000/setjmp.S
+@HAVE_LIBC_MACHINE_LM32_TRUE@am__append_89 = libc/machine/lm32/setjmp.S
+@HAVE_LIBC_MACHINE_M32C_TRUE@am__append_90 = libc/machine/m32c/setjmp.S
+@HAVE_LIBC_MACHINE_M32R_TRUE@am__append_91 = libc/machine/m32r/setjmp.S
+@HAVE_LIBC_MACHINE_M68HC11_TRUE@am__append_92 = libc/machine/m68hc11/setjmp.S
+@HAVE_LIBC_MACHINE_M68K_TRUE@am__append_93 = libc/machine/m68k/setjmp.S libc/machine/m68k/strcpy.c libc/machine/m68k/strlen.c libc/machine/m68k/memcpy.S libc/machine/m68k/memset.S
+@HAVE_LIBC_MACHINE_M88K_TRUE@am__append_94 = libc/machine/m88k/setjmp.S
+@HAVE_LIBC_MACHINE_MEP_TRUE@am__append_95 = libc/machine/mep/setjmp.S
+@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@am__append_96 = libc/machine/microblaze/strlen.c libc/machine/microblaze/strcmp.c libc/machine/microblaze/strcpy.c libc/machine/microblaze/setjmp.S libc/machine/microblaze/longjmp.S
+@HAVE_LIBC_MACHINE_MIPS_TRUE@am__append_97 = libc/machine/mips/setjmp.S libc/machine/mips/strlen.c libc/machine/mips/strcmp.S libc/machine/mips/strncpy.c libc/machine/mips/memset.S libc/machine/mips/memcpy.S
+@HAVE_LIBC_MACHINE_MN10200_TRUE@am__append_98 = libc/machine/mn10200/setjmp.S
+@HAVE_LIBC_MACHINE_MN10300_TRUE@am__append_99 = \
@HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/setjmp.S libc/machine/mn10300/memchr.S libc/machine/mn10300/memcmp.S libc/machine/mn10300/memcpy.S libc/machine/mn10300/memset.S libc/machine/mn10300/strchr.S \
@HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/strcmp.S libc/machine/mn10300/strcpy.S libc/machine/mn10300/strlen.S
-@HAVE_LIBC_MACHINE_MOXIE_TRUE@am__append_99 = libc/machine/moxie/setjmp.S
-@HAVE_LIBC_MACHINE_MSP430_TRUE@am__append_100 = libc/machine/msp430/setjmp.S
-@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@am__append_101 = libc/machine/msp430/tiny-puts.c libc/machine/msp430/tiny-printf.c
-@HAVE_LIBC_MACHINE_MT_TRUE@am__append_102 = libc/machine/mt/setjmp.S
-@HAVE_LIBC_MACHINE_NDS32_TRUE@am__append_103 = \
+@HAVE_LIBC_MACHINE_MOXIE_TRUE@am__append_100 = libc/machine/moxie/setjmp.S
+@HAVE_LIBC_MACHINE_MSP430_TRUE@am__append_101 = libc/machine/msp430/setjmp.S
+@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@am__append_102 = libc/machine/msp430/tiny-puts.c libc/machine/msp430/tiny-printf.c
+@HAVE_LIBC_MACHINE_MT_TRUE@am__append_103 = libc/machine/mt/setjmp.S
+@HAVE_LIBC_MACHINE_NDS32_TRUE@am__append_104 = \
@HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/abort.c \
@HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/setjmp.S \
@HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/strcmp.S \
@HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/strcpy.S
-@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@am__append_104 = libc/machine/nds32/memcpy.S libc/machine/nds32/memset.S
-@HAVE_LIBC_MACHINE_NECV70_TRUE@am__append_105 = libc/machine/necv70/fastmath.S libc/machine/necv70/setjmp.S
-@HAVE_LIBC_MACHINE_NIOS2_TRUE@am__append_106 = libc/machine/nios2/setjmp.s
-@HAVE_LIBC_MACHINE_NVPTX_TRUE@am__append_107 = \
+@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@am__append_105 = libc/machine/nds32/memcpy.S libc/machine/nds32/memset.S
+@HAVE_LIBC_MACHINE_NECV70_TRUE@am__append_106 = libc/machine/necv70/fastmath.S libc/machine/necv70/setjmp.S
+@HAVE_LIBC_MACHINE_NIOS2_TRUE@am__append_107 = libc/machine/nios2/setjmp.s
+@HAVE_LIBC_MACHINE_NVPTX_TRUE@am__append_108 = \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/_exit.c \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/calloc.c libc/machine/nvptx/callocr.c libc/machine/nvptx/malloc.c libc/machine/nvptx/mallocr.c libc/machine/nvptx/realloc.c libc/machine/nvptx/reallocr.c \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/free.c libc/machine/nvptx/write.c libc/machine/nvptx/assert.c libc/machine/nvptx/puts.c libc/machine/nvptx/putchar.c libc/machine/nvptx/printf.c libc/machine/nvptx/abort.c \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/misc.c libc/machine/nvptx/clock.c
-@HAVE_LIBC_MACHINE_OR1K_TRUE@am__append_108 = libc/machine/or1k/setjmp.S
-@HAVE_LIBC_MACHINE_POWERPC_TRUE@am__append_109 = libc/machine/powerpc/setjmp.S
-@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@am__append_110 = \
+@HAVE_LIBC_MACHINE_OR1K_TRUE@am__append_109 = libc/machine/or1k/setjmp.S
+@HAVE_LIBC_MACHINE_POWERPC_TRUE@am__append_110 = libc/machine/powerpc/setjmp.S
+@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@am__append_111 = \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vfprintf.c \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vfscanf.c \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_malloc.c \
@@ -780,7 +781,7 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_callocr.c \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_reallocr.c
-@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@am__append_111 = \
+@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@am__append_112 = \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix16.c \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix32.c \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix64.c \
@@ -798,21 +799,21 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/vfprintf.c \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/vfscanf.c
-@HAVE_LIBC_MACHINE_PRU_TRUE@am__append_112 = libc/machine/pru/setjmp.s
-@HAVE_LIBC_MACHINE_RISCV_TRUE@am__append_113 = \
+@HAVE_LIBC_MACHINE_PRU_TRUE@am__append_113 = libc/machine/pru/setjmp.s
+@HAVE_LIBC_MACHINE_RISCV_TRUE@am__append_114 = \
@HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/memmove.S libc/machine/riscv/memmove-stub.c libc/machine/riscv/memset.S libc/machine/riscv/memcpy-asm.S libc/machine/riscv/memcpy.c libc/machine/riscv/strlen.c \
@HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/strcpy.c libc/machine/riscv/strcmp.S libc/machine/riscv/setjmp.S libc/machine/riscv/ieeefp.c libc/machine/riscv/ffs.c
-@HAVE_LIBC_MACHINE_RL78_TRUE@am__append_114 = libc/machine/rl78/setjmp.S
-@HAVE_LIBC_MACHINE_RX_TRUE@am__append_115 = \
+@HAVE_LIBC_MACHINE_RL78_TRUE@am__append_115 = libc/machine/rl78/setjmp.S
+@HAVE_LIBC_MACHINE_RX_TRUE@am__append_116 = \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/setjmp.S \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/strncmp.S libc/machine/rx/strcmp.S libc/machine/rx/strncpy.S libc/machine/rx/strcpy.S libc/machine/rx/strlen.S libc/machine/rx/strcat.S libc/machine/rx/strncat.S \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/memset.S libc/machine/rx/mempcpy.S libc/machine/rx/memcpy.S libc/machine/rx/memmove.S libc/machine/rx/memchr.S
-@HAVE_LIBC_MACHINE_SH_TRUE@am__append_116 = libc/machine/sh/memcpy.S libc/machine/sh/memset.S libc/machine/sh/setjmp.S libc/machine/sh/strcpy.S libc/machine/sh/strlen.S libc/machine/sh/strcmp.S
-@HAVE_LIBC_MACHINE_SH_TRUE@@SH64_TRUE@am__append_117 = libc/machine/sh/strncpy.S
-@HAVE_LIBC_MACHINE_SPARC_TRUE@am__append_118 = libc/machine/sparc/scan.c libc/machine/sparc/shuffle.c libc/machine/sparc/setjmp.S
-@HAVE_LIBC_MACHINE_SPU_TRUE@am__append_119 = \
+@HAVE_LIBC_MACHINE_SH_TRUE@am__append_117 = libc/machine/sh/memcpy.S libc/machine/sh/memset.S libc/machine/sh/setjmp.S libc/machine/sh/strcpy.S libc/machine/sh/strlen.S libc/machine/sh/strcmp.S
+@HAVE_LIBC_MACHINE_SH_TRUE@@SH64_TRUE@am__append_118 = libc/machine/sh/strncpy.S
+@HAVE_LIBC_MACHINE_SPARC_TRUE@am__append_119 = libc/machine/sparc/scan.c libc/machine/sparc/shuffle.c libc/machine/sparc/setjmp.S
+@HAVE_LIBC_MACHINE_SPU_TRUE@am__append_120 = \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/setjmp.S libc/machine/spu/assert.c libc/machine/spu/clearerr.c libc/machine/spu/creat.c libc/machine/spu/fclose.c libc/machine/spu/feof.c \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/ferror.c libc/machine/spu/fflush.c libc/machine/spu/fgetc.c libc/machine/spu/fgetpos.c libc/machine/spu/fgets.c libc/machine/spu/fileno.c libc/machine/spu/fiprintf.S \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/fiscanf.S libc/machine/spu/fopen.c libc/machine/spu/fprintf.S libc/machine/spu/fputc.c libc/machine/spu/fputs.c libc/machine/spu/fread.c libc/machine/spu/freopen.c \
@@ -830,7 +831,7 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/spu_timer_slih.c libc/machine/spu/spu_timer_slih_reg.c libc/machine/spu/spu_timer_svcs.c \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/spu_timer_stop.c libc/machine/spu/spu_timer_free.c libc/machine/spu/spu_timebase.c libc/machine/spu/fdopen.c
-@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@am__append_120 = \
+@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@am__append_121 = \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/calloc_ea.c libc/machine/spu/free_ea.c libc/machine/spu/malloc_ea.c libc/machine/spu/memchr_ea.c libc/machine/spu/memcmp_ea.c \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/memcpy_ea.c libc/machine/spu/memmove_ea.c libc/machine/spu/memset_ea.c libc/machine/spu/mmap_ea.c libc/machine/spu/mremap_ea.c libc/machine/spu/msync_ea.c \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/munmap_ea.c libc/machine/spu/posix_memalign_ea.c libc/machine/spu/realloc_ea.c libc/machine/spu/strcat_ea.c libc/machine/spu/strchr_ea.c \
@@ -839,18 +840,18 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/pread_ea.c libc/machine/spu/readv_ea.c libc/machine/spu/write_ea.c libc/machine/spu/pwrite_ea.c libc/machine/spu/writev_ea.c libc/machine/spu/spu-mcount.S \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/spu-gmon.c
-@HAVE_LIBC_MACHINE_TIC4X_TRUE@am__append_121 = libc/machine/tic4x/setjmp.S
-@HAVE_LIBC_MACHINE_TIC6X_TRUE@am__append_122 = libc/machine/tic6x/setjmp.S
-@HAVE_LIBC_MACHINE_TIC80_TRUE@am__append_123 = libc/machine/tic80/setjmp.S
-@HAVE_LIBC_MACHINE_V850_TRUE@am__append_124 = libc/machine/v850/setjmp.S
-@HAVE_LIBC_MACHINE_VISIUM_TRUE@am__append_125 = libc/machine/visium/memcpy.c libc/machine/visium/memset.c libc/machine/visium/memmove.c libc/machine/visium/setjmp.S
-@HAVE_LIBC_MACHINE_W65_TRUE@am__append_126 = \
+@HAVE_LIBC_MACHINE_TIC4X_TRUE@am__append_122 = libc/machine/tic4x/setjmp.S
+@HAVE_LIBC_MACHINE_TIC6X_TRUE@am__append_123 = libc/machine/tic6x/setjmp.S
+@HAVE_LIBC_MACHINE_TIC80_TRUE@am__append_124 = libc/machine/tic80/setjmp.S
+@HAVE_LIBC_MACHINE_V850_TRUE@am__append_125 = libc/machine/v850/setjmp.S
+@HAVE_LIBC_MACHINE_VISIUM_TRUE@am__append_126 = libc/machine/visium/memcpy.c libc/machine/visium/memset.c libc/machine/visium/memmove.c libc/machine/visium/setjmp.S
+@HAVE_LIBC_MACHINE_W65_TRUE@am__append_127 = \
@HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/udivhi3.S libc/machine/w65/umodhi3.S libc/machine/w65/smulhi3.S libc/machine/w65/lshrhi.S libc/machine/w65/sdivhi3.S libc/machine/w65/mulsi3.c \
@HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/divsi3.c libc/machine/w65/cmpsi.c
-@HAVE_LIBC_MACHINE_X86_64_TRUE@am__append_127 = libc/machine/x86_64/setjmp.S libc/machine/x86_64/memcpy.S libc/machine/x86_64/memset.S
-@HAVE_LIBC_MACHINE_XC16X_TRUE@am__append_128 = libc/machine/xc16x/setjmp.S libc/machine/xc16x/puts.c libc/machine/xc16x/putchar.c
-@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@am__append_129 = \
+@HAVE_LIBC_MACHINE_X86_64_TRUE@am__append_128 = libc/machine/x86_64/setjmp.S libc/machine/x86_64/memcpy.S libc/machine/x86_64/memset.S
+@HAVE_LIBC_MACHINE_XC16X_TRUE@am__append_129 = libc/machine/xc16x/setjmp.S libc/machine/xc16x/puts.c libc/machine/xc16x/putchar.c
+@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@am__append_130 = \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/setjmp.S \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/calloc.c \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/callocr.c \
@@ -865,9 +866,13 @@ check_PROGRAMS =
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/reallocr.c \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/valloc.c
-@HAVE_LIBC_MACHINE_Z8K_TRUE@am__append_130 = libc/machine/z8k/setjmp.S libc/machine/z8k/memset.S libc/machine/z8k/memcpy.S libc/machine/z8k/memmove.S libc/machine/z8k/memcmp.S
-@NEWLIB_HW_FP_TRUE@am__append_131 = $(libm_mathfp_src) $(libm_mathfp_fsrc)
-@NEWLIB_HW_FP_TRUE@am__append_132 = \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@am__append_131 = \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/memcpy.S libc/machine/xtensa/memset.S libc/machine/xtensa/setjmp.S libc/machine/xtensa/strcmp.S libc/machine/xtensa/strcpy.S \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/strlen.S libc/machine/xtensa/strncpy.S
+
+@HAVE_LIBC_MACHINE_Z8K_TRUE@am__append_132 = libc/machine/z8k/setjmp.S libc/machine/z8k/memset.S libc/machine/z8k/memcpy.S libc/machine/z8k/memmove.S libc/machine/z8k/memcmp.S
+@NEWLIB_HW_FP_TRUE@am__append_133 = $(libm_mathfp_src) $(libm_mathfp_fsrc)
+@NEWLIB_HW_FP_TRUE@am__append_134 = \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/e_acosh.def \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/e_atanh.def \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/e_hypot.def \
@@ -897,9 +902,9 @@ check_PROGRAMS =
@NEWLIB_HW_FP_TRUE@ libm/mathfp/s_tanh.def \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/w_jn.def
-@NEWLIB_HW_FP_TRUE@am__append_133 = libm/mathfp/mathfp.tex
-@NEWLIB_HW_FP_FALSE@am__append_134 = $(libm_math_src) $(libm_math_fsrc) $(libm_math_lsrc)
-@NEWLIB_HW_FP_FALSE@am__append_135 = \
+@NEWLIB_HW_FP_TRUE@am__append_135 = libm/mathfp/mathfp.tex
+@NEWLIB_HW_FP_FALSE@am__append_136 = $(libm_math_src) $(libm_math_fsrc) $(libm_math_lsrc)
+@NEWLIB_HW_FP_FALSE@am__append_137 = \
@NEWLIB_HW_FP_FALSE@ libm/math/w_acos.def libm/math/w_acosh.def libm/math/w_asin.def libm/math/s_asinh.def \
@NEWLIB_HW_FP_FALSE@ libm/math/s_atan.def libm/math/w_atan2.def libm/math/w_atanh.def libm/math/w_j0.def \
@NEWLIB_HW_FP_FALSE@ libm/math/w_cosh.def libm/math/s_erf.def libm/math/w_exp.def libm/math/w_exp2.def \
@@ -909,34 +914,34 @@ check_PROGRAMS =
@NEWLIB_HW_FP_FALSE@ libm/math/w_pow.def libm/math/w_remainder.def libm/math/s_sin.def libm/math/w_sinh.def \
@NEWLIB_HW_FP_FALSE@ libm/math/w_sqrt.def libm/math/s_tan.def libm/math/s_tanh.def
-@NEWLIB_HW_FP_FALSE@am__append_136 = libm/math/math.tex
-@HAVE_LONG_DOUBLE_TRUE@am__append_137 = $(libm_common_lsrc)
-@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_138 = $(libm_ld_lsrc)
-@HAVE_FPMATH_H_TRUE@am__append_139 =
-@HAVE_FPMATH_H_TRUE@am__append_140 =
-@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_141 = $(libm_machine_aarch64_src)
-@HAVE_LIBM_MACHINE_AARCH64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_142 = $(libm_ld128_lsrc)
-@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_143 =
-@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_144 =
-@HAVE_LIBM_MACHINE_AMDGCN_TRUE@am__append_145 = $(libm_machine_amdgcn_src)
-@HAVE_LIBM_MACHINE_ARM_TRUE@am__append_146 = $(libm_machine_arm_src)
-@HAVE_LIBM_MACHINE_I386_TRUE@am__append_147 = $(libm_machine_i386_src)
-@HAVE_LIBM_MACHINE_I386_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_148 = $(libm_ld80_lsrc)
-@HAVE_LIBM_MACHINE_I386_TRUE@am__append_149 =
-@HAVE_LIBM_MACHINE_I386_TRUE@am__append_150 =
-@HAVE_LIBM_MACHINE_MIPS_TRUE@am__append_151 = $(libm_machine_mips_src)
-@HAS_NDS32_FPU_SP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_152 = libm/machine/nds32/wf_sqrt.S
-@HAS_NDS32_FPU_DP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_153 = libm/machine/nds32/w_sqrt.S
-@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_154 = $(libm_machine_nds32_src)
-@HAVE_LIBM_MACHINE_POWERPC_TRUE@am__append_155 = $(libm_machine_powerpc_src)
-@HAVE_LIBM_MACHINE_PRU_TRUE@am__append_156 = $(libm_machine_pru_src)
-@HAVE_LIBM_MACHINE_SPARC_TRUE@am__append_157 = $(libm_machine_sparc_src)
-@HAVE_LIBM_MACHINE_SPU_TRUE@am__append_158 = $(libm_machine_spu_src)
-@HAVE_LIBM_MACHINE_RISCV_TRUE@am__append_159 = $(libm_machine_riscv_src)
-@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_160 = $(libm_machine_x86_64_src)
-@HAVE_LIBM_MACHINE_X86_64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_161 = $(libm_ld80_lsrc)
-@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_162 =
-@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_163 =
+@NEWLIB_HW_FP_FALSE@am__append_138 = libm/math/math.tex
+@HAVE_LONG_DOUBLE_TRUE@am__append_139 = $(libm_common_lsrc)
+@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_140 = $(libm_ld_lsrc)
+@HAVE_FPMATH_H_TRUE@am__append_141 =
+@HAVE_FPMATH_H_TRUE@am__append_142 =
+@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_143 = $(libm_machine_aarch64_src)
+@HAVE_LIBM_MACHINE_AARCH64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_144 = $(libm_ld128_lsrc)
+@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_145 =
+@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_146 =
+@HAVE_LIBM_MACHINE_AMDGCN_TRUE@am__append_147 = $(libm_machine_amdgcn_src)
+@HAVE_LIBM_MACHINE_ARM_TRUE@am__append_148 = $(libm_machine_arm_src)
+@HAVE_LIBM_MACHINE_I386_TRUE@am__append_149 = $(libm_machine_i386_src)
+@HAVE_LIBM_MACHINE_I386_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_150 = $(libm_ld80_lsrc)
+@HAVE_LIBM_MACHINE_I386_TRUE@am__append_151 =
+@HAVE_LIBM_MACHINE_I386_TRUE@am__append_152 =
+@HAVE_LIBM_MACHINE_MIPS_TRUE@am__append_153 = $(libm_machine_mips_src)
+@HAS_NDS32_FPU_SP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_154 = libm/machine/nds32/wf_sqrt.S
+@HAS_NDS32_FPU_DP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_155 = libm/machine/nds32/w_sqrt.S
+@HAVE_LIBM_MACHINE_NDS32_TRUE@am__append_156 = $(libm_machine_nds32_src)
+@HAVE_LIBM_MACHINE_POWERPC_TRUE@am__append_157 = $(libm_machine_powerpc_src)
+@HAVE_LIBM_MACHINE_PRU_TRUE@am__append_158 = $(libm_machine_pru_src)
+@HAVE_LIBM_MACHINE_SPARC_TRUE@am__append_159 = $(libm_machine_sparc_src)
+@HAVE_LIBM_MACHINE_SPU_TRUE@am__append_160 = $(libm_machine_spu_src)
+@HAVE_LIBM_MACHINE_RISCV_TRUE@am__append_161 = $(libm_machine_riscv_src)
+@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_162 = $(libm_machine_x86_64_src)
+@HAVE_LIBM_MACHINE_X86_64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_163 = $(libm_ld80_lsrc)
+@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_164 =
+@HAVE_LIBM_MACHINE_X86_64_TRUE@am__append_165 =
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/depstand.m4 \
@@ -948,6 +953,7 @@ am__aclocal_m4_deps = $(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/libc/machine/powerpc/acinclude.m4 \
$(top_srcdir)/libc/machine/sh/acinclude.m4 \
$(top_srcdir)/libc/machine/spu/acinclude.m4 \
+ $(top_srcdir)/libc/machine/xtensa/acinclude.m4 \
$(top_srcdir)/libm/acinclude.m4 \
$(top_srcdir)/libm/machine/nds32/acinclude.m4 \
$(top_srcdir)/configure.ac
@@ -1824,8 +1830,11 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_SYS_TIRTOS_DIR_TRUE@am__objects_73 = libc/sys/tirtos/libc_a-lock.$(OBJEXT)
@HAVE_LIBC_SYS_W65_DIR_TRUE@am__objects_74 = libc/sys/w65/libc_a-syscalls.$(OBJEXT) \
@HAVE_LIBC_SYS_W65_DIR_TRUE@ libc/sys/w65/libc_a-trap.$(OBJEXT)
-@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__objects_75 = libc/sys/z8ksim/libc_a-glue.$(OBJEXT)
-@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__objects_76 = libc/machine/aarch64/libc_a-memchr-stub.$(OBJEXT) \
+@HAVE_LIBC_SYS_XTENSA_DIR_TRUE@am__objects_75 = libc/sys/xtensa/libc_a-creat.$(OBJEXT) \
+@HAVE_LIBC_SYS_XTENSA_DIR_TRUE@ libc/sys/xtensa/libc_a-isatty.$(OBJEXT) \
+@HAVE_LIBC_SYS_XTENSA_DIR_TRUE@ libc/sys/xtensa/libc_a-clibrary_init.$(OBJEXT)
+@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__objects_76 = libc/sys/z8ksim/libc_a-glue.$(OBJEXT)
+@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__objects_77 = libc/machine/aarch64/libc_a-memchr-stub.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-memchr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-memcmp-stub.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-memcmp.$(OBJEXT) \
@@ -1856,13 +1865,13 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-strnlen.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-strrchr-stub.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/libc_a-strrchr.$(OBJEXT)
-@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__objects_77 = libc/machine/amdgcn/libc_a-abort.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__objects_78 = libc/machine/amdgcn/libc_a-abort.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-exit.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-atexit.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-mlock.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-getreent.$(OBJEXT) \
@HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/libc_a-signal.$(OBJEXT)
-@HAVE_LIBC_MACHINE_ARC_TRUE@am__objects_78 = libc/machine/arc/libc_a-memcmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_ARC_TRUE@am__objects_79 = libc/machine/arc/libc_a-memcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/libc_a-memcmp-bs-norm.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/libc_a-memcmp-stub.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/libc_a-memcpy.$(OBJEXT) \
@@ -1892,7 +1901,7 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/libc_a-strncpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/libc_a-strncpy-stub.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/libc_a-strncpy-bs.$(OBJEXT)
-@HAVE_LIBC_MACHINE_ARM_TRUE@am__objects_79 = libc/machine/arm/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_ARM_TRUE@am__objects_80 = libc/machine/arm/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/libc_a-strcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/libc_a-strcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/libc_a-aeabi_memcpy.$(OBJEXT) \
@@ -1908,44 +1917,44 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/libc_a-strlen-stub.$(OBJEXT) \
@HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/libc_a-strlen.$(OBJEXT)
-@HAVE_LIBC_MACHINE_BFIN_TRUE@am__objects_80 = libc/machine/bfin/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_BFIN_TRUE@am__objects_81 = libc/machine/bfin/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_BFIN_TRUE@ libc/machine/bfin/libc_a-longjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_CR16_TRUE@am__objects_81 = libc/machine/cr16/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_CR16_TRUE@am__objects_82 = libc/machine/cr16/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_CR16_TRUE@ libc/machine/cr16/libc_a-getenv.$(OBJEXT)
-@HAVE_LIBC_MACHINE_CRIS_TRUE@am__objects_82 = libc/machine/cris/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_CRIS_TRUE@am__objects_83 = libc/machine/cris/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_CRIS_TRUE@ libc/machine/cris/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_CRIS_TRUE@ libc/machine/cris/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_CRIS_TRUE@ libc/machine/cris/libc_a-memmove.$(OBJEXT) \
@HAVE_LIBC_MACHINE_CRIS_TRUE@ libc/machine/cris/libc_a-libcdtor.$(OBJEXT)
-@HAVE_LIBC_MACHINE_CRX_TRUE@am__objects_83 = libc/machine/crx/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_CRX_TRUE@am__objects_84 = libc/machine/crx/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_CRX_TRUE@ libc/machine/crx/libc_a-getenv.$(OBJEXT)
-@HAVE_LIBC_MACHINE_CSKY_TRUE@am__objects_84 = libc/machine/csky/libc_a-setjmp.$(OBJEXT)
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-@HAVE_LIBC_MACHINE_FT32_TRUE@am__objects_90 = libc/machine/ft32/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_CSKY_TRUE@am__objects_85 = libc/machine/csky/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_D10V_TRUE@am__objects_86 = libc/machine/d10v/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_D30V_TRUE@am__objects_87 = libc/machine/d30v/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_EPIPHANY_TRUE@am__objects_88 = libc/machine/epiphany/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_FR30_TRUE@am__objects_89 = libc/machine/fr30/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_FRV_TRUE@am__objects_90 = libc/machine/frv/libc_a-setjmp.$(OBJEXT)
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@HAVE_LIBC_MACHINE_FT32_TRUE@ libc/machine/ft32/libc_a-strcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_FT32_TRUE@ libc/machine/ft32/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_FT32_TRUE@ libc/machine/ft32/libc_a-strcpy.$(OBJEXT)
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+@HAVE_LIBC_MACHINE_H8300_TRUE@am__objects_92 = libc/machine/h8300/libc_a-reg_memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/libc_a-reg_memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/libc_a-strcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/libc_a-h8sx_strcpy.$(OBJEXT)
-@HAVE_LIBC_MACHINE_H8500_TRUE@am__objects_92 = libc/machine/h8500/libc_a-divsi3.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_H8500_TRUE@am__objects_93 = libc/machine/h8500/libc_a-divsi3.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8500_TRUE@ libc/machine/h8500/libc_a-mulsi3.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8500_TRUE@ libc/machine/h8500/libc_a-divhi3.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8500_TRUE@ libc/machine/h8500/libc_a-shifts.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8500_TRUE@ libc/machine/h8500/libc_a-cmpsi.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8500_TRUE@ libc/machine/h8500/libc_a-psi.$(OBJEXT) \
@HAVE_LIBC_MACHINE_H8500_TRUE@ libc/machine/h8500/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_HPPA_TRUE@am__objects_93 = libc/machine/hppa/libc_a-memchr.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_HPPA_TRUE@am__objects_94 = libc/machine/hppa/libc_a-memchr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/libc_a-memcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/libc_a-memset.$(OBJEXT) \
@@ -1957,15 +1966,15 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/libc_a-strncat.$(OBJEXT) \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/libc_a-strncmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/libc_a-strncpy.$(OBJEXT)
-@HAVE_LIBC_MACHINE_I386_TRUE@@MACH_ADD_SETJMP_TRUE@am__objects_94 = libc/machine/i386/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_I386_TRUE@am__objects_95 = libc/machine/i386/libc_a-memchr.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_I386_TRUE@@MACH_ADD_SETJMP_TRUE@am__objects_95 = libc/machine/i386/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_I386_TRUE@am__objects_96 = libc/machine/i386/libc_a-memchr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/libc_a-memcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/libc_a-strchr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/libc_a-memmove.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/libc_a-strlen.$(OBJEXT)
-@HAVE_LIBC_MACHINE_I960_TRUE@am__objects_96 = libc/machine/i960/libc_a-memccpy_ca.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_I960_TRUE@am__objects_97 = libc/machine/i960/libc_a-memccpy_ca.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/libc_a-memccpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/libc_a-memchr_ca.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/libc_a-memchr.$(OBJEXT) \
@@ -1993,31 +2002,31 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/libc_a-strncpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/libc_a-strpbrk.$(OBJEXT) \
@HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/libc_a-strrchr.$(OBJEXT)
-@HAVE_LIBC_MACHINE_IQ2000_TRUE@am__objects_97 = libc/machine/iq2000/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_LM32_TRUE@am__objects_98 = libc/machine/lm32/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_M32C_TRUE@am__objects_99 = libc/machine/m32c/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_M32R_TRUE@am__objects_100 = libc/machine/m32r/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_M68HC11_TRUE@am__objects_101 = libc/machine/m68hc11/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_M68K_TRUE@am__objects_102 = libc/machine/m68k/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_IQ2000_TRUE@am__objects_98 = libc/machine/iq2000/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_LM32_TRUE@am__objects_99 = libc/machine/lm32/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_M32C_TRUE@am__objects_100 = libc/machine/m32c/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_M32R_TRUE@am__objects_101 = libc/machine/m32r/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_M68HC11_TRUE@am__objects_102 = libc/machine/m68hc11/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_M68K_TRUE@am__objects_103 = libc/machine/m68k/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_M68K_TRUE@ libc/machine/m68k/libc_a-strcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_M68K_TRUE@ libc/machine/m68k/libc_a-strlen.$(OBJEXT) \
@HAVE_LIBC_MACHINE_M68K_TRUE@ libc/machine/m68k/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_M68K_TRUE@ libc/machine/m68k/libc_a-memset.$(OBJEXT)
-@HAVE_LIBC_MACHINE_M88K_TRUE@am__objects_103 = libc/machine/m88k/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MEP_TRUE@am__objects_104 = libc/machine/mep/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@am__objects_105 = libc/machine/microblaze/libc_a-strlen.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_M88K_TRUE@am__objects_104 = libc/machine/m88k/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_MEP_TRUE@am__objects_105 = libc/machine/mep/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@am__objects_106 = libc/machine/microblaze/libc_a-strlen.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@ libc/machine/microblaze/libc_a-strcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@ libc/machine/microblaze/libc_a-strcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@ libc/machine/microblaze/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@ libc/machine/microblaze/libc_a-longjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MIPS_TRUE@am__objects_106 = libc/machine/mips/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_MIPS_TRUE@am__objects_107 = libc/machine/mips/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MIPS_TRUE@ libc/machine/mips/libc_a-strlen.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MIPS_TRUE@ libc/machine/mips/libc_a-strcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MIPS_TRUE@ libc/machine/mips/libc_a-strncpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MIPS_TRUE@ libc/machine/mips/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MIPS_TRUE@ libc/machine/mips/libc_a-memcpy.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MN10200_TRUE@am__objects_107 = libc/machine/mn10200/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MN10300_TRUE@am__objects_108 = libc/machine/mn10300/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_MN10200_TRUE@am__objects_108 = libc/machine/mn10200/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_MN10300_TRUE@am__objects_109 = libc/machine/mn10300/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/libc_a-memchr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/libc_a-memcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/libc_a-memcpy.$(OBJEXT) \
@@ -2026,21 +2035,21 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/libc_a-strcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/libc_a-strcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/libc_a-strlen.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MOXIE_TRUE@am__objects_109 = libc/machine/moxie/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MSP430_TRUE@am__objects_110 = libc/machine/msp430/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@am__objects_111 = libc/machine/msp430/libc_a-tiny-puts.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_MOXIE_TRUE@am__objects_110 = libc/machine/moxie/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_MSP430_TRUE@am__objects_111 = libc/machine/msp430/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@am__objects_112 = libc/machine/msp430/libc_a-tiny-puts.$(OBJEXT) \
@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@ libc/machine/msp430/libc_a-tiny-printf.$(OBJEXT)
-@HAVE_LIBC_MACHINE_MT_TRUE@am__objects_112 = libc/machine/mt/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_NDS32_TRUE@am__objects_113 = libc/machine/nds32/libc_a-abort.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_MT_TRUE@am__objects_113 = libc/machine/mt/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_NDS32_TRUE@am__objects_114 = libc/machine/nds32/libc_a-abort.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/libc_a-strcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/libc_a-strcpy.$(OBJEXT)
-@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@am__objects_114 = libc/machine/nds32/libc_a-memcpy.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@am__objects_115 = libc/machine/nds32/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@ libc/machine/nds32/libc_a-memset.$(OBJEXT)
-@HAVE_LIBC_MACHINE_NECV70_TRUE@am__objects_115 = libc/machine/necv70/libc_a-fastmath.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_NECV70_TRUE@am__objects_116 = libc/machine/necv70/libc_a-fastmath.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NECV70_TRUE@ libc/machine/necv70/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_NIOS2_TRUE@am__objects_116 = libc/machine/nios2/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_NVPTX_TRUE@am__objects_117 = libc/machine/nvptx/libc_a-_exit.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_NIOS2_TRUE@am__objects_117 = libc/machine/nios2/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_NVPTX_TRUE@am__objects_118 = libc/machine/nvptx/libc_a-_exit.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/libc_a-calloc.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/libc_a-callocr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/libc_a-malloc.$(OBJEXT) \
@@ -2056,9 +2065,9 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/libc_a-abort.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/libc_a-misc.$(OBJEXT) \
@HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/libc_a-clock.$(OBJEXT)
-@HAVE_LIBC_MACHINE_OR1K_TRUE@am__objects_118 = libc/machine/or1k/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_POWERPC_TRUE@am__objects_119 = libc/machine/powerpc/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@am__objects_120 = libc/machine/powerpc/libc_a-vfprintf.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_OR1K_TRUE@am__objects_119 = libc/machine/or1k/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_POWERPC_TRUE@am__objects_120 = libc/machine/powerpc/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@am__objects_121 = libc/machine/powerpc/libc_a-vfprintf.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/libc_a-vfscanf.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/libc_a-vec_malloc.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/libc_a-vec_calloc.$(OBJEXT) \
@@ -2067,7 +2076,7 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/libc_a-vec_mallocr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/libc_a-vec_callocr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/libc_a-vec_reallocr.$(OBJEXT)
-@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@am__objects_121 = libc/machine/powerpc/libc_a-atosfix16.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@am__objects_122 = libc/machine/powerpc/libc_a-atosfix16.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/libc_a-atosfix32.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/libc_a-atosfix64.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/libc_a-atoufix16.$(OBJEXT) \
@@ -2083,8 +2092,8 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/libc_a-ufix64toa.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/libc_a-vfprintf.$(OBJEXT) \
@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/libc_a-vfscanf.$(OBJEXT)
-@HAVE_LIBC_MACHINE_PRU_TRUE@am__objects_122 = libc/machine/pru/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_RISCV_TRUE@am__objects_123 = libc/machine/riscv/libc_a-memmove.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_PRU_TRUE@am__objects_123 = libc/machine/pru/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_RISCV_TRUE@am__objects_124 = libc/machine/riscv/libc_a-memmove.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/libc_a-memmove-stub.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/libc_a-memcpy-asm.$(OBJEXT) \
@@ -2095,8 +2104,8 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/libc_a-ieeefp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/libc_a-ffs.$(OBJEXT)
-@HAVE_LIBC_MACHINE_RL78_TRUE@am__objects_124 = libc/machine/rl78/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_RX_TRUE@am__objects_125 = libc/machine/rx/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_RL78_TRUE@am__objects_125 = libc/machine/rl78/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_RX_TRUE@am__objects_126 = libc/machine/rx/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/libc_a-strncmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/libc_a-strcmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/libc_a-strncpy.$(OBJEXT) \
@@ -2109,17 +2118,17 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/libc_a-memmove.$(OBJEXT) \
@HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/libc_a-memchr.$(OBJEXT)
-@HAVE_LIBC_MACHINE_SH_TRUE@am__objects_126 = libc/machine/sh/libc_a-memcpy.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_SH_TRUE@am__objects_127 = libc/machine/sh/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SH_TRUE@ libc/machine/sh/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SH_TRUE@ libc/machine/sh/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SH_TRUE@ libc/machine/sh/libc_a-strcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SH_TRUE@ libc/machine/sh/libc_a-strlen.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SH_TRUE@ libc/machine/sh/libc_a-strcmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_SH_TRUE@@SH64_TRUE@am__objects_127 = libc/machine/sh/libc_a-strncpy.$(OBJEXT)
-@HAVE_LIBC_MACHINE_SPARC_TRUE@am__objects_128 = libc/machine/sparc/libc_a-scan.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_SH_TRUE@@SH64_TRUE@am__objects_128 = libc/machine/sh/libc_a-strncpy.$(OBJEXT)
+@HAVE_LIBC_MACHINE_SPARC_TRUE@am__objects_129 = libc/machine/sparc/libc_a-scan.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPARC_TRUE@ libc/machine/sparc/libc_a-shuffle.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPARC_TRUE@ libc/machine/sparc/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_SPU_TRUE@am__objects_129 = libc/machine/spu/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_SPU_TRUE@am__objects_130 = libc/machine/spu/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/libc_a-assert.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/libc_a-clearerr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/libc_a-creat.$(OBJEXT) \
@@ -2214,7 +2223,7 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/libc_a-spu_timer_free.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/libc_a-spu_timebase.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/libc_a-fdopen.$(OBJEXT)
-@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@am__objects_130 = libc/machine/spu/libc_a-calloc_ea.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@am__objects_131 = libc/machine/spu/libc_a-calloc_ea.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/libc_a-free_ea.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/libc_a-malloc_ea.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/libc_a-memchr_ea.$(OBJEXT) \
@@ -2249,15 +2258,15 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/libc_a-writev_ea.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/libc_a-spu-mcount.$(OBJEXT) \
@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/libc_a-spu-gmon.$(OBJEXT)
-@HAVE_LIBC_MACHINE_TIC4X_TRUE@am__objects_131 = libc/machine/tic4x/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_TIC6X_TRUE@am__objects_132 = libc/machine/tic6x/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_TIC80_TRUE@am__objects_133 = libc/machine/tic80/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_V850_TRUE@am__objects_134 = libc/machine/v850/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_VISIUM_TRUE@am__objects_135 = libc/machine/visium/libc_a-memcpy.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_TIC4X_TRUE@am__objects_132 = libc/machine/tic4x/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_TIC6X_TRUE@am__objects_133 = libc/machine/tic6x/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_TIC80_TRUE@am__objects_134 = libc/machine/tic80/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_V850_TRUE@am__objects_135 = libc/machine/v850/libc_a-setjmp.$(OBJEXT)
+@HAVE_LIBC_MACHINE_VISIUM_TRUE@am__objects_136 = libc/machine/visium/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_VISIUM_TRUE@ libc/machine/visium/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_VISIUM_TRUE@ libc/machine/visium/libc_a-memmove.$(OBJEXT) \
@HAVE_LIBC_MACHINE_VISIUM_TRUE@ libc/machine/visium/libc_a-setjmp.$(OBJEXT)
-@HAVE_LIBC_MACHINE_W65_TRUE@am__objects_136 = libc/machine/w65/libc_a-udivhi3.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_W65_TRUE@am__objects_137 = libc/machine/w65/libc_a-udivhi3.$(OBJEXT) \
@HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/libc_a-umodhi3.$(OBJEXT) \
@HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/libc_a-smulhi3.$(OBJEXT) \
@HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/libc_a-lshrhi.$(OBJEXT) \
@@ -2265,13 +2274,13 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/libc_a-mulsi3.$(OBJEXT) \
@HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/libc_a-divsi3.$(OBJEXT) \
@HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/libc_a-cmpsi.$(OBJEXT)
-@HAVE_LIBC_MACHINE_X86_64_TRUE@am__objects_137 = libc/machine/x86_64/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_X86_64_TRUE@am__objects_138 = libc/machine/x86_64/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_X86_64_TRUE@ libc/machine/x86_64/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_X86_64_TRUE@ libc/machine/x86_64/libc_a-memset.$(OBJEXT)
-@HAVE_LIBC_MACHINE_XC16X_TRUE@am__objects_138 = libc/machine/xc16x/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XC16X_TRUE@am__objects_139 = libc/machine/xc16x/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_XC16X_TRUE@ libc/machine/xc16x/libc_a-puts.$(OBJEXT) \
@HAVE_LIBC_MACHINE_XC16X_TRUE@ libc/machine/xc16x/libc_a-putchar.$(OBJEXT)
-@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@am__objects_139 = libc/machine/xstormy16/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@am__objects_140 = libc/machine/xstormy16/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/libc_a-calloc.$(OBJEXT) \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/libc_a-callocr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/libc_a-cfree.$(OBJEXT) \
@@ -2284,7 +2293,14 @@ am__objects_51 = libc/ssp/libc_a-chk_fail.$(OBJEXT) \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/libc_a-realloc.$(OBJEXT) \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/libc_a-reallocr.$(OBJEXT) \
@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/libc_a-valloc.$(OBJEXT)
-@HAVE_LIBC_MACHINE_Z8K_TRUE@am__objects_140 = libc/machine/z8k/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@am__objects_141 = libc/machine/xtensa/libc_a-memcpy.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/libc_a-memset.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/libc_a-setjmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/libc_a-strcmp.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/libc_a-strcpy.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/libc_a-strlen.$(OBJEXT) \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@ libc/machine/xtensa/libc_a-strncpy.$(OBJEXT)
+@HAVE_LIBC_MACHINE_Z8K_TRUE@am__objects_142 = libc/machine/z8k/libc_a-setjmp.$(OBJEXT) \
@HAVE_LIBC_MACHINE_Z8K_TRUE@ libc/machine/z8k/libc_a-memset.$(OBJEXT) \
@HAVE_LIBC_MACHINE_Z8K_TRUE@ libc/machine/z8k/libc_a-memcpy.$(OBJEXT) \
@HAVE_LIBC_MACHINE_Z8K_TRUE@ libc/machine/z8k/libc_a-memmove.$(OBJEXT) \
@@ -2578,7 +2594,8 @@ am_libc_a_OBJECTS = $(am__objects_1) \
$(am__objects_129) $(am__objects_130) $(am__objects_131) \
$(am__objects_132) $(am__objects_133) $(am__objects_134) \
$(am__objects_135) $(am__objects_136) $(am__objects_137) \
- $(am__objects_138) $(am__objects_139) $(am__objects_140)
+ $(am__objects_138) $(am__objects_139) $(am__objects_140) \
+ $(am__objects_141) $(am__objects_142)
libc_a_OBJECTS = $(am_libc_a_OBJECTS)
libc_machine_cris_libic_a_AR = $(AR) $(ARFLAGS)
@HAVE_LIBC_MACHINE_CRIS_TRUE@libc_machine_cris_libic_a_DEPENDENCIES = libc/machine/cris/libc_a-setjmp.o \
@@ -2591,7 +2608,7 @@ libc_machine_cris_libic_a_OBJECTS = \
$(am_libc_machine_cris_libic_a_OBJECTS)
libm_a_AR = $(AR) $(ARFLAGS)
libm_a_LIBADD =
-@NEWLIB_HW_FP_TRUE@am__objects_141 = \
+@NEWLIB_HW_FP_TRUE@am__objects_143 = \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-s_acos.$(OBJEXT) \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-s_frexp.$(OBJEXT) \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-s_mathcnst.$(OBJEXT) \
@@ -2639,7 +2656,7 @@ libm_a_LIBADD =
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-s_signif.$(OBJEXT) \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-s_exp2.$(OBJEXT) \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-s_tgamma.$(OBJEXT)
-@NEWLIB_HW_FP_TRUE@am__objects_142 = \
+@NEWLIB_HW_FP_TRUE@am__objects_144 = \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-sf_ceil.$(OBJEXT) \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-sf_acos.$(OBJEXT) \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-sf_frexp.$(OBJEXT) \
@@ -2687,9 +2704,9 @@ libm_a_LIBADD =
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-sf_signif.$(OBJEXT) \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-sf_exp2.$(OBJEXT) \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/libm_a-sf_tgamma.$(OBJEXT)
-@NEWLIB_HW_FP_TRUE@am__objects_143 = $(am__objects_141) \
-@NEWLIB_HW_FP_TRUE@ $(am__objects_142)
-@NEWLIB_HW_FP_FALSE@am__objects_144 = \
+@NEWLIB_HW_FP_TRUE@am__objects_145 = $(am__objects_143) \
+@NEWLIB_HW_FP_TRUE@ $(am__objects_144)
+@NEWLIB_HW_FP_FALSE@am__objects_146 = \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-k_standard.$(OBJEXT) \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-k_rem_pio2.$(OBJEXT) \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-k_cos.$(OBJEXT) \
@@ -2758,7 +2775,7 @@ libm_a_LIBADD =
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-s_tanh.$(OBJEXT) \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-w_exp2.$(OBJEXT) \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-w_tgamma.$(OBJEXT)
-@NEWLIB_HW_FP_FALSE@am__objects_145 = \
+@NEWLIB_HW_FP_FALSE@am__objects_147 = \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-kf_rem_pio2.$(OBJEXT) \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-kf_cos.$(OBJEXT) \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-kf_sin.$(OBJEXT) \
@@ -2826,11 +2843,11 @@ libm_a_LIBADD =
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-wf_exp2.$(OBJEXT) \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-wf_tgamma.$(OBJEXT) \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-wf_log2.$(OBJEXT)
-@NEWLIB_HW_FP_FALSE@am__objects_146 = \
+@NEWLIB_HW_FP_FALSE@am__objects_148 = \
@NEWLIB_HW_FP_FALSE@ libm/math/libm_a-el_hypot.$(OBJEXT)
-@NEWLIB_HW_FP_FALSE@am__objects_147 = $(am__objects_144) \
-@NEWLIB_HW_FP_FALSE@ $(am__objects_145) $(am__objects_146)
-am__objects_148 = libm/common/libm_a-s_finite.$(OBJEXT) \
+@NEWLIB_HW_FP_FALSE@am__objects_149 = $(am__objects_146) \
+@NEWLIB_HW_FP_FALSE@ $(am__objects_147) $(am__objects_148)
+am__objects_150 = libm/common/libm_a-s_finite.$(OBJEXT) \
libm/common/libm_a-s_copysign.$(OBJEXT) \
libm/common/libm_a-s_modf.$(OBJEXT) \
libm/common/libm_a-s_scalbn.$(OBJEXT) \
@@ -2875,7 +2892,7 @@ am__objects_148 = libm/common/libm_a-s_finite.$(OBJEXT) \
libm/common/libm_a-log2_data.$(OBJEXT) \
libm/common/libm_a-pow.$(OBJEXT) \
libm/common/libm_a-pow_log_data.$(OBJEXT)
-am__objects_149 = libm/common/libm_a-sf_finite.$(OBJEXT) \
+am__objects_151 = libm/common/libm_a-sf_finite.$(OBJEXT) \
libm/common/libm_a-sf_copysign.$(OBJEXT) \
libm/common/libm_a-sf_modf.$(OBJEXT) \
libm/common/libm_a-sf_scalbn.$(OBJEXT) \
@@ -2922,7 +2939,7 @@ am__objects_149 = libm/common/libm_a-sf_finite.$(OBJEXT) \
libm/common/libm_a-sincosf.$(OBJEXT) \
libm/common/libm_a-sincosf_data.$(OBJEXT) \
libm/common/libm_a-math_errf.$(OBJEXT)
-am__objects_150 = libm/common/libm_a-atanl.$(OBJEXT) \
+am__objects_152 = libm/common/libm_a-atanl.$(OBJEXT) \
libm/common/libm_a-cosl.$(OBJEXT) \
libm/common/libm_a-sinl.$(OBJEXT) \
libm/common/libm_a-tanl.$(OBJEXT) \
@@ -2982,8 +2999,8 @@ am__objects_150 = libm/common/libm_a-atanl.$(OBJEXT) \
libm/common/libm_a-nexttowardl.$(OBJEXT) \
libm/common/libm_a-log2l.$(OBJEXT) \
libm/common/libm_a-sl_finite.$(OBJEXT)
-@HAVE_LONG_DOUBLE_TRUE@am__objects_151 = $(am__objects_150)
-@HAVE_FPMATH_H_TRUE@am__objects_152 = \
+@HAVE_LONG_DOUBLE_TRUE@am__objects_153 = $(am__objects_152)
+@HAVE_FPMATH_H_TRUE@am__objects_154 = \
@HAVE_FPMATH_H_TRUE@ libm/ld/libm_a-e_acoshl.$(OBJEXT) \
@HAVE_FPMATH_H_TRUE@ libm/ld/libm_a-e_acosl.$(OBJEXT) \
@HAVE_FPMATH_H_TRUE@ libm/ld/libm_a-e_asinl.$(OBJEXT) \
@@ -3029,9 +3046,9 @@ am__objects_150 = libm/common/libm_a-atanl.$(OBJEXT) \
@HAVE_FPMATH_H_TRUE@ libm/ld/libm_a-s_tanhl.$(OBJEXT) \
@HAVE_FPMATH_H_TRUE@ libm/ld/libm_a-s_tanl.$(OBJEXT) \
@HAVE_FPMATH_H_TRUE@ libm/ld/libm_a-s_truncl.$(OBJEXT)
-@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__objects_153 = \
-@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@ $(am__objects_152)
-am__objects_154 = libm/complex/libm_a-cabs.$(OBJEXT) \
+@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__objects_155 = \
+@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@ $(am__objects_154)
+am__objects_156 = libm/complex/libm_a-cabs.$(OBJEXT) \
libm/complex/libm_a-cacos.$(OBJEXT) \
libm/complex/libm_a-cacosh.$(OBJEXT) \
libm/complex/libm_a-carg.$(OBJEXT) \
@@ -3055,7 +3072,7 @@ am__objects_154 = libm/complex/libm_a-cabs.$(OBJEXT) \
libm/complex/libm_a-csqrt.$(OBJEXT) \
libm/complex/libm_a-ctan.$(OBJEXT) \
libm/complex/libm_a-ctanh.$(OBJEXT)
-am__objects_155 = libm/complex/libm_a-cabsf.$(OBJEXT) \
+am__objects_157 = libm/complex/libm_a-cabsf.$(OBJEXT) \
libm/complex/libm_a-casinf.$(OBJEXT) \
libm/complex/libm_a-ccosf.$(OBJEXT) \
libm/complex/libm_a-cimagf.$(OBJEXT) \
@@ -3079,7 +3096,7 @@ am__objects_155 = libm/complex/libm_a-cabsf.$(OBJEXT) \
libm/complex/libm_a-cexpf.$(OBJEXT) \
libm/complex/libm_a-cpowf.$(OBJEXT) \
libm/complex/libm_a-csinhf.$(OBJEXT)
-am__objects_156 = libm/complex/libm_a-cabsl.$(OBJEXT) \
+am__objects_158 = libm/complex/libm_a-cabsl.$(OBJEXT) \
libm/complex/libm_a-creall.$(OBJEXT) \
libm/complex/libm_a-cimagl.$(OBJEXT) \
libm/complex/libm_a-ccoshl.$(OBJEXT) \
@@ -3102,7 +3119,7 @@ am__objects_156 = libm/complex/libm_a-cabsl.$(OBJEXT) \
libm/complex/libm_a-csinhl.$(OBJEXT) \
libm/complex/libm_a-csinl.$(OBJEXT) \
libm/complex/libm_a-catanl.$(OBJEXT)
-am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
+am__objects_159 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
libm/fenv/libm_a-fe_dfl_env.$(OBJEXT) \
libm/fenv/libm_a-fegetenv.$(OBJEXT) \
libm/fenv/libm_a-fegetexceptflag.$(OBJEXT) \
@@ -3114,7 +3131,7 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
libm/fenv/libm_a-fesetround.$(OBJEXT) \
libm/fenv/libm_a-fetestexcept.$(OBJEXT) \
libm/fenv/libm_a-feupdateenv.$(OBJEXT)
-@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__objects_158 = libm/machine/aarch64/libm_a-e_sqrt.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__objects_160 = libm/machine/aarch64/libm_a-e_sqrt.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/machine/aarch64/libm_a-ef_sqrt.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/machine/aarch64/libm_a-s_ceil.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/machine/aarch64/libm_a-s_fabs.$(OBJEXT) \
@@ -3156,8 +3173,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/machine/aarch64/libm_a-fesetround.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/machine/aarch64/libm_a-fetestexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/machine/aarch64/libm_a-feupdateenv.$(OBJEXT)
-@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__objects_159 = $(am__objects_158)
-@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__objects_160 = libm/ld128/libm_a-e_powl.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__objects_161 = $(am__objects_160)
+@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__objects_162 = libm/ld128/libm_a-e_powl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/ld128/libm_a-s_erfl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/ld128/libm_a-s_exp2l.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/ld128/libm_a-s_expl.$(OBJEXT) \
@@ -3167,8 +3184,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/ld128/libm_a-e_lgammal_r.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/ld128/libm_a-k_cosl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AARCH64_TRUE@ libm/ld128/libm_a-k_sinl.$(OBJEXT)
-@HAVE_LIBM_MACHINE_AARCH64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__objects_161 = $(am__objects_160)
-@HAVE_LIBM_MACHINE_AMDGCN_TRUE@am__objects_162 = libm/machine/amdgcn/libm_a-v64_mathcnst.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_AARCH64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__objects_163 = $(am__objects_162)
+@HAVE_LIBM_MACHINE_AMDGCN_TRUE@am__objects_164 = libm/machine/amdgcn/libm_a-v64_mathcnst.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AMDGCN_TRUE@ libm/machine/amdgcn/libm_a-v64_reent.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AMDGCN_TRUE@ libm/machine/amdgcn/libm_a-v64df_acos.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AMDGCN_TRUE@ libm/machine/amdgcn/libm_a-v64df_acosh.$(OBJEXT) \
@@ -3256,8 +3273,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AMDGCN_TRUE@ libm/machine/amdgcn/libm_a-v64sf_tan.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AMDGCN_TRUE@ libm/machine/amdgcn/libm_a-v64sf_tanh.$(OBJEXT) \
@HAVE_LIBM_MACHINE_AMDGCN_TRUE@ libm/machine/amdgcn/libm_a-v64sf_tgamma.$(OBJEXT)
-@HAVE_LIBM_MACHINE_AMDGCN_TRUE@am__objects_163 = $(am__objects_162)
-@HAVE_LIBM_MACHINE_ARM_TRUE@am__objects_164 = libm/machine/arm/libm_a-e_sqrt.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_AMDGCN_TRUE@am__objects_165 = $(am__objects_164)
+@HAVE_LIBM_MACHINE_ARM_TRUE@am__objects_166 = libm/machine/arm/libm_a-e_sqrt.$(OBJEXT) \
@HAVE_LIBM_MACHINE_ARM_TRUE@ libm/machine/arm/libm_a-ef_sqrt.$(OBJEXT) \
@HAVE_LIBM_MACHINE_ARM_TRUE@ libm/machine/arm/libm_a-s_ceil.$(OBJEXT) \
@HAVE_LIBM_MACHINE_ARM_TRUE@ libm/machine/arm/libm_a-s_floor.$(OBJEXT) \
@@ -3288,8 +3305,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_ARM_TRUE@ libm/machine/arm/libm_a-feupdateenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_ARM_TRUE@ libm/machine/arm/libm_a-feenableexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_ARM_TRUE@ libm/machine/arm/libm_a-fedisableexcept.$(OBJEXT)
-@HAVE_LIBM_MACHINE_ARM_TRUE@am__objects_165 = $(am__objects_164)
-@HAVE_LIBM_MACHINE_I386_TRUE@am__objects_166 = libm/machine/i386/libm_a-f_atan2.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_ARM_TRUE@am__objects_167 = $(am__objects_166)
+@HAVE_LIBM_MACHINE_I386_TRUE@am__objects_168 = libm/machine/i386/libm_a-f_atan2.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/machine/i386/libm_a-f_atan2f.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/machine/i386/libm_a-f_exp.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/machine/i386/libm_a-f_expf.$(OBJEXT) \
@@ -3326,8 +3343,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/machine/i386/libm_a-fesetround.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/machine/i386/libm_a-fetestexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/machine/i386/libm_a-feupdateenv.$(OBJEXT)
-@HAVE_LIBM_MACHINE_I386_TRUE@am__objects_167 = $(am__objects_166)
-@HAVE_LIBM_MACHINE_I386_FALSE@@HAVE_LIBM_MACHINE_X86_64_TRUE@am__objects_168 = libm/ld80/libm_a-b_tgammal.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_I386_TRUE@am__objects_169 = $(am__objects_168)
+@HAVE_LIBM_MACHINE_I386_FALSE@@HAVE_LIBM_MACHINE_X86_64_TRUE@am__objects_170 = libm/ld80/libm_a-b_tgammal.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_FALSE@@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/ld80/libm_a-e_powl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_FALSE@@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/ld80/libm_a-s_erfl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_FALSE@@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/ld80/libm_a-s_exp2l.$(OBJEXT) \
@@ -3339,7 +3356,7 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_FALSE@@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/ld80/libm_a-e_lgammal_r.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_FALSE@@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/ld80/libm_a-k_cosl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_FALSE@@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/ld80/libm_a-k_sinl.$(OBJEXT)
-@HAVE_LIBM_MACHINE_I386_TRUE@am__objects_168 = libm/ld80/libm_a-b_tgammal.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_I386_TRUE@am__objects_170 = libm/ld80/libm_a-b_tgammal.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/ld80/libm_a-e_powl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/ld80/libm_a-s_erfl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/ld80/libm_a-s_exp2l.$(OBJEXT) \
@@ -3351,8 +3368,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/ld80/libm_a-e_lgammal_r.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/ld80/libm_a-k_cosl.$(OBJEXT) \
@HAVE_LIBM_MACHINE_I386_TRUE@ libm/ld80/libm_a-k_sinl.$(OBJEXT)
-@HAVE_LIBM_MACHINE_I386_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__objects_169 = $(am__objects_168)
-@HAVE_LIBM_MACHINE_MIPS_TRUE@am__objects_170 = libm/machine/mips/libm_a-feclearexcept.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_I386_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__objects_171 = $(am__objects_170)
+@HAVE_LIBM_MACHINE_MIPS_TRUE@am__objects_172 = libm/machine/mips/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_MIPS_TRUE@ libm/machine/mips/libm_a-fegetenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_MIPS_TRUE@ libm/machine/mips/libm_a-fegetexceptflag.$(OBJEXT) \
@HAVE_LIBM_MACHINE_MIPS_TRUE@ libm/machine/mips/libm_a-fegetround.$(OBJEXT) \
@@ -3364,13 +3381,13 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_MIPS_TRUE@ libm/machine/mips/libm_a-fetestexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_MIPS_TRUE@ libm/machine/mips/libm_a-feupdateenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_MIPS_TRUE@ libm/machine/mips/libm_a-fenv.$(OBJEXT)
-@HAVE_LIBM_MACHINE_MIPS_TRUE@am__objects_171 = $(am__objects_170)
-@HAS_NDS32_FPU_SP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__objects_172 = libm/machine/nds32/libm_a-wf_sqrt.$(OBJEXT)
-@HAS_NDS32_FPU_DP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__objects_173 = libm/machine/nds32/libm_a-w_sqrt.$(OBJEXT)
-@HAVE_LIBM_MACHINE_NDS32_TRUE@am__objects_174 = $(am__objects_172) \
-@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__objects_173)
-@HAVE_LIBM_MACHINE_NDS32_TRUE@am__objects_175 = $(am__objects_174)
-@HAVE_LIBM_MACHINE_POWERPC_TRUE@am__objects_176 = libm/machine/powerpc/libm_a-feclearexcept.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_MIPS_TRUE@am__objects_173 = $(am__objects_172)
+@HAS_NDS32_FPU_SP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__objects_174 = libm/machine/nds32/libm_a-wf_sqrt.$(OBJEXT)
+@HAS_NDS32_FPU_DP_TRUE@@HAVE_LIBM_MACHINE_NDS32_TRUE@am__objects_175 = libm/machine/nds32/libm_a-w_sqrt.$(OBJEXT)
+@HAVE_LIBM_MACHINE_NDS32_TRUE@am__objects_176 = $(am__objects_174) \
+@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__objects_175)
+@HAVE_LIBM_MACHINE_NDS32_TRUE@am__objects_177 = $(am__objects_176)
+@HAVE_LIBM_MACHINE_POWERPC_TRUE@am__objects_178 = libm/machine/powerpc/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/libm_a-fegetenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/libm_a-fegetexceptflag.$(OBJEXT) \
@HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/libm_a-fegetround.$(OBJEXT) \
@@ -3382,8 +3399,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/libm_a-fesetround.$(OBJEXT) \
@HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/libm_a-fetestexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/libm_a-feupdateenv.$(OBJEXT)
-@HAVE_LIBM_MACHINE_POWERPC_TRUE@am__objects_177 = $(am__objects_176)
-@HAVE_LIBM_MACHINE_PRU_TRUE@am__objects_178 = libm/machine/pru/libm_a-fpclassify.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_POWERPC_TRUE@am__objects_179 = $(am__objects_178)
+@HAVE_LIBM_MACHINE_PRU_TRUE@am__objects_180 = libm/machine/pru/libm_a-fpclassify.$(OBJEXT) \
@HAVE_LIBM_MACHINE_PRU_TRUE@ libm/machine/pru/libm_a-fpclassifyf.$(OBJEXT) \
@HAVE_LIBM_MACHINE_PRU_TRUE@ libm/machine/pru/libm_a-isfinite.$(OBJEXT) \
@HAVE_LIBM_MACHINE_PRU_TRUE@ libm/machine/pru/libm_a-isfinitef.$(OBJEXT) \
@@ -3393,8 +3410,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_PRU_TRUE@ libm/machine/pru/libm_a-isnanf.$(OBJEXT) \
@HAVE_LIBM_MACHINE_PRU_TRUE@ libm/machine/pru/libm_a-isnormal.$(OBJEXT) \
@HAVE_LIBM_MACHINE_PRU_TRUE@ libm/machine/pru/libm_a-isnormalf.$(OBJEXT)
-@HAVE_LIBM_MACHINE_PRU_TRUE@am__objects_179 = $(am__objects_178)
-@HAVE_LIBM_MACHINE_SPARC_TRUE@am__objects_180 = libm/machine/sparc/libm_a-feclearexcept.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_PRU_TRUE@am__objects_181 = $(am__objects_180)
+@HAVE_LIBM_MACHINE_SPARC_TRUE@am__objects_182 = libm/machine/sparc/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPARC_TRUE@ libm/machine/sparc/libm_a-fegetenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPARC_TRUE@ libm/machine/sparc/libm_a-fegetexceptflag.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPARC_TRUE@ libm/machine/sparc/libm_a-fegetround.$(OBJEXT) \
@@ -3406,8 +3423,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPARC_TRUE@ libm/machine/sparc/libm_a-fetestexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPARC_TRUE@ libm/machine/sparc/libm_a-feupdateenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPARC_TRUE@ libm/machine/sparc/libm_a-fenv.$(OBJEXT)
-@HAVE_LIBM_MACHINE_SPARC_TRUE@am__objects_181 = $(am__objects_180)
-@HAVE_LIBM_MACHINE_SPU_TRUE@am__objects_182 = libm/machine/spu/libm_a-feclearexcept.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_SPARC_TRUE@am__objects_183 = $(am__objects_182)
+@HAVE_LIBM_MACHINE_SPU_TRUE@am__objects_184 = libm/machine/spu/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPU_TRUE@ libm/machine/spu/libm_a-fe_dfl_env.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPU_TRUE@ libm/machine/spu/libm_a-fegetenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPU_TRUE@ libm/machine/spu/libm_a-fegetexceptflag.$(OBJEXT) \
@@ -3532,8 +3549,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPU_TRUE@ libm/machine/spu/libm_a-w_sinh.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPU_TRUE@ libm/machine/spu/libm_a-w_sqrt.$(OBJEXT) \
@HAVE_LIBM_MACHINE_SPU_TRUE@ libm/machine/spu/libm_a-w_tgamma.$(OBJEXT)
-@HAVE_LIBM_MACHINE_SPU_TRUE@am__objects_183 = $(am__objects_182)
-@HAVE_LIBM_MACHINE_RISCV_TRUE@am__objects_184 = libm/machine/riscv/libm_a-feclearexcept.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_SPU_TRUE@am__objects_185 = $(am__objects_184)
+@HAVE_LIBM_MACHINE_RISCV_TRUE@am__objects_186 = libm/machine/riscv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_RISCV_TRUE@ libm/machine/riscv/libm_a-fe_dfl_env.$(OBJEXT) \
@HAVE_LIBM_MACHINE_RISCV_TRUE@ libm/machine/riscv/libm_a-fegetenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_RISCV_TRUE@ libm/machine/riscv/libm_a-fegetexceptflag.$(OBJEXT) \
@@ -3573,8 +3590,8 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_RISCV_TRUE@ libm/machine/riscv/libm_a-sf_llrint.$(OBJEXT) \
@HAVE_LIBM_MACHINE_RISCV_TRUE@ libm/machine/riscv/libm_a-s_llround.$(OBJEXT) \
@HAVE_LIBM_MACHINE_RISCV_TRUE@ libm/machine/riscv/libm_a-sf_llround.$(OBJEXT)
-@HAVE_LIBM_MACHINE_RISCV_TRUE@am__objects_185 = $(am__objects_184)
-@HAVE_LIBM_MACHINE_X86_64_TRUE@am__objects_186 = libm/machine/x86_64/libm_a-feclearexcept.$(OBJEXT) \
+@HAVE_LIBM_MACHINE_RISCV_TRUE@am__objects_187 = $(am__objects_186)
+@HAVE_LIBM_MACHINE_X86_64_TRUE@am__objects_188 = libm/machine/x86_64/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/machine/x86_64/libm_a-fegetenv.$(OBJEXT) \
@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/machine/x86_64/libm_a-fegetexceptflag.$(OBJEXT) \
@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/machine/x86_64/libm_a-fegetround.$(OBJEXT) \
@@ -3586,17 +3603,17 @@ am__objects_157 = libm/fenv/libm_a-feclearexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/machine/x86_64/libm_a-fesetround.$(OBJEXT) \
@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/machine/x86_64/libm_a-fetestexcept.$(OBJEXT) \
@HAVE_LIBM_MACHINE_X86_64_TRUE@ libm/machine/x86_64/libm_a-feupdateenv.$(OBJEXT)
-@HAVE_LIBM_MACHINE_X86_64_TRUE@am__objects_187 = $(am__objects_186)
-@HAVE_LIBM_MACHINE_X86_64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__objects_188 = $(am__objects_168)
-am_libm_a_OBJECTS = $(am__objects_143) $(am__objects_147) \
- $(am__objects_148) $(am__objects_149) $(am__objects_151) \
- $(am__objects_153) $(am__objects_154) $(am__objects_155) \
- $(am__objects_156) $(am__objects_157) $(am__objects_159) \
- $(am__objects_161) $(am__objects_163) $(am__objects_165) \
- $(am__objects_167) $(am__objects_169) $(am__objects_171) \
- $(am__objects_175) $(am__objects_177) $(am__objects_179) \
- $(am__objects_181) $(am__objects_183) $(am__objects_185) \
- $(am__objects_187) $(am__objects_188)
+@HAVE_LIBM_MACHINE_X86_64_TRUE@am__objects_189 = $(am__objects_188)
+@HAVE_LIBM_MACHINE_X86_64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__objects_190 = $(am__objects_170)
+am_libm_a_OBJECTS = $(am__objects_145) $(am__objects_149) \
+ $(am__objects_150) $(am__objects_151) $(am__objects_153) \
+ $(am__objects_155) $(am__objects_156) $(am__objects_157) \
+ $(am__objects_158) $(am__objects_159) $(am__objects_161) \
+ $(am__objects_163) $(am__objects_165) $(am__objects_167) \
+ $(am__objects_169) $(am__objects_171) $(am__objects_173) \
+ $(am__objects_177) $(am__objects_179) $(am__objects_181) \
+ $(am__objects_183) $(am__objects_185) $(am__objects_187) \
+ $(am__objects_189) $(am__objects_190)
libm_a_OBJECTS = $(am_libm_a_OBJECTS)
am_libm_test_test_OBJECTS = libm/test/test.$(OBJEXT) \
libm/test/string.$(OBJEXT) libm/test/convert.$(OBJEXT) \
@@ -3951,7 +3968,7 @@ AM_CFLAGS = $(AM_CFLAGS_$(subst /,_,$(@D))) $(AM_CFLAGS_$(subst /,_,$(@D)_$(<F))
AM_CCASFLAGS = $(AM_CCASFLAGS_$(subst /,_,$(@D))) $(AM_CCASFLAGS_$(subst /,_,$(@D)_$(<F)))
@HAVE_LIBC_MACHINE_ARM_FALSE@AM_CPPFLAGS = $(NEWLIB_CFLAGS) $(TARGET_CFLAGS) $(AM_CPPFLAGS_$(subst /,_,$(@D))) $(AM_CPPFLAGS_$(subst /,_,$(@D)_$(<F)))
@HAVE_LIBC_MACHINE_ARM_TRUE@AM_CPPFLAGS = $(NEWLIB_CFLAGS) $(TARGET_CFLAGS) $(AM_CPPFLAGS_$(subst /,_,$(@D))) $(AM_CPPFLAGS_$(subst /,_,$(@D)_$(<F))) -idirafter $(srcroot)/include
-toollib_LIBRARIES = libm.a libc.a $(am__append_72)
+toollib_LIBRARIES = libm.a libc.a $(am__append_73)
@HAVE_MULTISUBDIR_TRUE@BUILD_MULTISUBDIR = $(builddir)$(MULTISUBDIR)
toollib_DATA = $(CRT0) $(CRT1)
AWK_UNIQUE_OBJS = $(AWK) '{ \
@@ -4122,7 +4139,7 @@ libc_a_SOURCES = $(am__append_5) libc/stdlib/__adjust.c \
$(am__append_62) $(am__append_63) $(am__append_64) \
$(am__append_65) $(am__append_66) $(am__append_67) \
$(am__append_68) $(am__append_69) $(am__append_70) \
- $(am__append_71) $(am__append_73) $(am__append_74) \
+ $(am__append_71) $(am__append_72) $(am__append_74) \
$(am__append_75) $(am__append_76) $(am__append_77) \
$(am__append_78) $(am__append_79) $(am__append_80) \
$(am__append_81) $(am__append_82) $(am__append_83) \
@@ -4141,20 +4158,21 @@ libc_a_SOURCES = $(am__append_5) libc/stdlib/__adjust.c \
$(am__append_120) $(am__append_121) $(am__append_122) \
$(am__append_123) $(am__append_124) $(am__append_125) \
$(am__append_126) $(am__append_127) $(am__append_128) \
- $(am__append_129) $(am__append_130)
+ $(am__append_129) $(am__append_130) $(am__append_131) \
+ $(am__append_132)
libc_a_CFLAGS = $(AM_CFLAGS) $(libc_a_CFLAGS_$(subst /,_,$(@D))) $(libc_a_CFLAGS_$(subst /,_,$(@D)_$(<F)))
libc_a_CCASFLAGS = $(AM_CCASFLAGS) $(libc_a_CCASFLAGS_$(subst /,_,$(@D))) $(libc_a_CCASFLAGS_$(subst /,_,$(@D)_$(<F)))
libc_a_CPPFLAGS = $(AM_CPPFLAGS) $(libc_a_CPPFLAGS_$(subst /,_,$(@D))) $(libc_a_CPPFLAGS_$(subst /,_,$(@D)_$(<F)))
libc_a_DEPENDENCIES = stamp-libc-math-objects
-libm_a_SOURCES = $(am__append_131) $(am__append_134) \
- $(libm_common_src) $(libm_common_fsrc) $(am__append_137) \
- $(am__append_138) $(libm_complex_src) $(libm_complex_fsrc) \
- $(libm_complex_lsrc) $(libm_fenv_src) $(am__append_141) \
- $(am__append_142) $(am__append_145) $(am__append_146) \
- $(am__append_147) $(am__append_148) $(am__append_151) \
- $(am__append_154) $(am__append_155) $(am__append_156) \
- $(am__append_157) $(am__append_158) $(am__append_159) \
- $(am__append_160) $(am__append_161)
+libm_a_SOURCES = $(am__append_133) $(am__append_136) \
+ $(libm_common_src) $(libm_common_fsrc) $(am__append_139) \
+ $(am__append_140) $(libm_complex_src) $(libm_complex_fsrc) \
+ $(libm_complex_lsrc) $(libm_fenv_src) $(am__append_143) \
+ $(am__append_144) $(am__append_147) $(am__append_148) \
+ $(am__append_149) $(am__append_150) $(am__append_153) \
+ $(am__append_156) $(am__append_157) $(am__append_158) \
+ $(am__append_159) $(am__append_160) $(am__append_161) \
+ $(am__append_162) $(am__append_163)
libm_a_CFLAGS = $(AM_CFLAGS) $(libm_a_CFLAGS_$(subst /,_,$(@D))) $(libm_a_CFLAGS_$(subst /,_,$(@D)_$(<F)))
libm_a_CCASFLAGS = $(AM_CCASFLAGS) $(libm_a_CCASFLAGS_$(subst /,_,$(@D))) $(libm_a_CCASFLAGS_$(subst /,_,$(@D)_$(<F)))
libm_a_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/libm/common $(libm_a_CPPFLAGS_$(subst /,_,$(@D))) $(libm_a_CPPFLAGS_$(subst /,_,$(@D)_$(<F)))
@@ -4583,8 +4601,11 @@ libc_ssp_ELIX_SOURCES = libc/ssp/chk_fail.c libc/ssp/stack_protector.c \
@HAVE_LIBC_MACHINE_MN10300_TRUE@libc_a_CCASFLAGS_libc_machine_mn10300 = -Wa,--gdwarf-2
@HAVE_LIBC_MACHINE_POWERPC_TRUE@libc_a_CPPFLAGS_libc_machine_powerpc = -I$(srcdir)/libc/stdio -I$(srcdir)/libc/stdlib
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@@XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE@libc_a_CPPFLAGS_libc_machine_xtensa = \
+@HAVE_LIBC_MACHINE_XTENSA_TRUE@@XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE@ -DXTENSA_ESP32_PSRAM_CACHE_FIX
+
libm_libm_TEXINFOS = libm/targetdep.tex $(LIBM_CHEWOUT_FILES)
-LIBM_CHEWOUT_FILES = $(am__append_132) $(am__append_135) \
+LIBM_CHEWOUT_FILES = $(am__append_134) $(am__append_137) \
libm/common/s_cbrt.def libm/common/s_copysign.def \
libm/common/s_exp10.def libm/common/s_expm1.def \
libm/common/s_ilogb.def libm/common/s_infinity.def \
@@ -4599,7 +4620,7 @@ LIBM_CHEWOUT_FILES = $(am__append_132) $(am__append_135) \
libm/common/s_remquo.def libm/common/s_rint.def \
libm/common/s_round.def libm/common/s_signbit.def \
libm/common/s_trunc.def libm/common/isgreater.def \
- $(am__append_139) libm/complex/cabs.def libm/complex/cacos.def \
+ $(am__append_141) libm/complex/cabs.def libm/complex/cacos.def \
libm/complex/cacosh.def libm/complex/carg.def \
libm/complex/casin.def libm/complex/casinh.def \
libm/complex/catan.def libm/complex/catanh.def \
@@ -4616,10 +4637,10 @@ LIBM_CHEWOUT_FILES = $(am__append_132) $(am__append_135) \
libm/fenv/feraiseexcept.def libm/fenv/fesetenv.def \
libm/fenv/fesetexceptflag.def libm/fenv/fesetround.def \
libm/fenv/fetestexcept.def libm/fenv/feupdateenv.def \
- $(am__append_143) $(am__append_149) $(am__append_162)
-LIBM_CHAPTERS = $(am__append_133) $(am__append_136) $(am__append_140) \
- libm/complex/complex.tex libm/fenv/fenv.tex $(am__append_144) \
- $(am__append_150) $(am__append_163)
+ $(am__append_145) $(am__append_151) $(am__append_164)
+LIBM_CHAPTERS = $(am__append_135) $(am__append_138) $(am__append_142) \
+ libm/complex/complex.tex libm/fenv/fenv.tex $(am__append_146) \
+ $(am__append_152) $(am__append_165)
LIBM_DOCBOOK_OUT_FILES = $(LIBM_CHEWOUT_FILES:.def=.xml)
@NEWLIB_HW_FP_TRUE@libm_mathfp_src = \
@NEWLIB_HW_FP_TRUE@ libm/mathfp/s_acos.c libm/mathfp/s_frexp.c libm/mathfp/s_mathcnst.c \
@@ -5147,8 +5168,8 @@ libm_test_test_LDADD = $(CRT0) libm.a libc.a
# fenv.c cannot be compiled as mips16 since it uses the cfc1 instruction.
@HAVE_LIBM_MACHINE_MIPS_TRUE@libm_a_CFLAGS_libm_machine_mips_fenv.c = -mno-mips16
@HAVE_LIBM_MACHINE_NDS32_TRUE@libm_machine_nds32_src = \
-@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__append_152) \
-@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__append_153)
+@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__append_154) \
+@HAVE_LIBM_MACHINE_NDS32_TRUE@ $(am__append_155)
@HAVE_LIBM_MACHINE_POWERPC_TRUE@libm_machine_powerpc_src = \
@HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/feclearexcept.c libm/machine/powerpc/fegetenv.c libm/machine/powerpc/fegetexceptflag.c \
@HAVE_LIBM_MACHINE_POWERPC_TRUE@ libm/machine/powerpc/fegetround.c libm/machine/powerpc/feholdexcept.c libm/machine/powerpc/fenv.c libm/machine/powerpc/feraiseexcept.c libm/machine/powerpc/fesetenv.c \
@@ -5217,7 +5238,7 @@ all: newlib.h _newlib_version.h
.SUFFIXES: .def .xml .S .c .dvi .o .obj .ps .s
am--refresh: Makefile
@:
-$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/libc/Makefile.inc $(srcdir)/libc/argz/Makefile.inc $(srcdir)/libc/stdlib/Makefile.inc $(srcdir)/libc/ctype/Makefile.inc $(srcdir)/libc/search/Makefile.inc $(srcdir)/libc/stdio/Makefile.inc $(srcdir)/libc/stdio64/Makefile.inc $(srcdir)/libc/string/Makefile.inc $(srcdir)/libc/signal/Makefile.inc $(srcdir)/libc/time/Makefile.inc $(srcdir)/libc/locale/Makefile.inc $(srcdir)/libc/reent/Makefile.inc $(srcdir)/libc/errno/Makefile.inc $(srcdir)/libc/misc/Makefile.inc $(srcdir)/libc/unix/Makefile.inc $(srcdir)/libc/posix/Makefile.inc $(srcdir)/libc/syscalls/Makefile.inc $(srcdir)/libc/iconv/Makefile.inc $(srcdir)/libc/iconv/ces/Makefile.inc $(srcdir)/libc/iconv/ccs/Makefile.inc $(srcdir)/libc/iconv/ccs/binary/Makefile.inc $(srcdir)/libc/iconv/lib/Makefile.inc $(srcdir)/libc/xdr/Makefile.inc $(srcdir)/libc/ssp/Makefile.inc $(srcdir)/libc/sys/Makefile.inc $(srcdir)/libc/sys/a29khif/Makefile.inc $(srcdir)/libc/sys/amdgcn/Makefile.inc $(srcdir)/libc/sys/arm/Makefile.inc $(srcdir)/libc/sys/d10v/Makefile.inc $(srcdir)/libc/sys/epiphany/Makefile.inc $(srcdir)/libc/sys/h8300hms/Makefile.inc $(srcdir)/libc/sys/h8500hms/Makefile.inc $(srcdir)/libc/sys/m88kbug/Makefile.inc $(srcdir)/libc/sys/mmixware/Makefile.inc $(srcdir)/libc/sys/netware/Makefile.inc $(srcdir)/libc/sys/or1k/Makefile.inc $(srcdir)/libc/sys/rdos/Makefile.inc $(srcdir)/libc/sys/rtems/Makefile.inc $(srcdir)/libc/sys/sh/Makefile.inc $(srcdir)/libc/sys/sysmec/Makefile.inc $(srcdir)/libc/sys/sysnec810/Makefile.inc $(srcdir)/libc/sys/sysnecv850/Makefile.inc $(srcdir)/libc/sys/sysvi386/Makefile.inc $(srcdir)/libc/sys/sysvnecv70/Makefile.inc $(srcdir)/libc/sys/tic80/Makefile.inc $(srcdir)/libc/sys/tirtos/Makefile.inc $(srcdir)/libc/sys/w65/Makefile.inc $(srcdir)/libc/sys/z8ksim/Makefile.inc $(srcdir)/libc/machine/Makefile.inc $(srcdir)/libc/machine/aarch64/Makefile.inc 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$(srcdir)/libm/machine/powerpc/Makefile.inc $(srcdir)/libm/machine/pru/Makefile.inc $(srcdir)/libm/machine/sparc/Makefile.inc $(srcdir)/libm/machine/spu/Makefile.inc $(srcdir)/libm/machine/riscv/Makefile.inc $(srcdir)/libm/machine/x86_64/Makefile.inc $(srcdir)/libm/ld80/Makefile.inc $(am__configure_deps)
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/libc/Makefile.inc $(srcdir)/libc/argz/Makefile.inc $(srcdir)/libc/stdlib/Makefile.inc $(srcdir)/libc/ctype/Makefile.inc $(srcdir)/libc/search/Makefile.inc $(srcdir)/libc/stdio/Makefile.inc $(srcdir)/libc/stdio64/Makefile.inc $(srcdir)/libc/string/Makefile.inc $(srcdir)/libc/signal/Makefile.inc $(srcdir)/libc/time/Makefile.inc $(srcdir)/libc/locale/Makefile.inc $(srcdir)/libc/reent/Makefile.inc $(srcdir)/libc/errno/Makefile.inc $(srcdir)/libc/misc/Makefile.inc $(srcdir)/libc/unix/Makefile.inc $(srcdir)/libc/posix/Makefile.inc $(srcdir)/libc/syscalls/Makefile.inc $(srcdir)/libc/iconv/Makefile.inc $(srcdir)/libc/iconv/ces/Makefile.inc $(srcdir)/libc/iconv/ccs/Makefile.inc $(srcdir)/libc/iconv/ccs/binary/Makefile.inc $(srcdir)/libc/iconv/lib/Makefile.inc $(srcdir)/libc/xdr/Makefile.inc $(srcdir)/libc/ssp/Makefile.inc $(srcdir)/libc/sys/Makefile.inc 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$(srcdir)/libc/machine/aarch64/Makefile.inc $(srcdir)/libc/machine/amdgcn/Makefile.inc $(srcdir)/libc/machine/arc/Makefile.inc $(srcdir)/libc/machine/arm/Makefile.inc $(srcdir)/libc/machine/bfin/Makefile.inc $(srcdir)/libc/machine/cr16/Makefile.inc $(srcdir)/libc/machine/cris/Makefile.inc $(srcdir)/libc/machine/crx/Makefile.inc $(srcdir)/libc/machine/csky/Makefile.inc $(srcdir)/libc/machine/d10v/Makefile.inc $(srcdir)/libc/machine/d30v/Makefile.inc $(srcdir)/libc/machine/epiphany/Makefile.inc $(srcdir)/libc/machine/fr30/Makefile.inc $(srcdir)/libc/machine/frv/Makefile.inc $(srcdir)/libc/machine/ft32/Makefile.inc $(srcdir)/libc/machine/h8300/Makefile.inc $(srcdir)/libc/machine/h8500/Makefile.inc $(srcdir)/libc/machine/hppa/Makefile.inc $(srcdir)/libc/machine/i386/Makefile.inc $(srcdir)/libc/machine/i960/Makefile.inc $(srcdir)/libc/machine/iq2000/Makefile.inc $(srcdir)/libc/machine/lm32/Makefile.inc $(srcdir)/libc/machine/m32c/Makefile.inc $(srcdir)/libc/machine/m32r/Makefile.inc $(srcdir)/libc/machine/m68hc11/Makefile.inc $(srcdir)/libc/machine/m68k/Makefile.inc $(srcdir)/libc/machine/m88k/Makefile.inc $(srcdir)/libc/machine/mep/Makefile.inc $(srcdir)/libc/machine/microblaze/Makefile.inc $(srcdir)/libc/machine/mips/Makefile.inc $(srcdir)/libc/machine/mn10200/Makefile.inc $(srcdir)/libc/machine/mn10300/Makefile.inc $(srcdir)/libc/machine/moxie/Makefile.inc $(srcdir)/libc/machine/msp430/Makefile.inc $(srcdir)/libc/machine/mt/Makefile.inc $(srcdir)/libc/machine/nds32/Makefile.inc $(srcdir)/libc/machine/necv70/Makefile.inc $(srcdir)/libc/machine/nios2/Makefile.inc $(srcdir)/libc/machine/nvptx/Makefile.inc $(srcdir)/libc/machine/or1k/Makefile.inc $(srcdir)/libc/machine/powerpc/Makefile.inc $(srcdir)/libc/machine/pru/Makefile.inc $(srcdir)/libc/machine/riscv/Makefile.inc $(srcdir)/libc/machine/rl78/Makefile.inc $(srcdir)/libc/machine/rx/Makefile.inc $(srcdir)/libc/machine/sh/Makefile.inc $(srcdir)/libc/machine/sparc/Makefile.inc $(srcdir)/libc/machine/spu/Makefile.inc $(srcdir)/libc/machine/tic4x/Makefile.inc $(srcdir)/libc/machine/tic6x/Makefile.inc $(srcdir)/libc/machine/tic80/Makefile.inc $(srcdir)/libc/machine/v850/Makefile.inc $(srcdir)/libc/machine/visium/Makefile.inc $(srcdir)/libc/machine/w65/Makefile.inc $(srcdir)/libc/machine/x86_64/Makefile.inc $(srcdir)/libc/machine/xc16x/Makefile.inc $(srcdir)/libc/machine/xstormy16/Makefile.inc $(srcdir)/libc/machine/xtensa/Makefile.inc $(srcdir)/libc/machine/z8k/Makefile.inc $(srcdir)/libm/Makefile.inc $(srcdir)/libm/mathfp/Makefile.inc $(srcdir)/libm/math/Makefile.inc $(srcdir)/libm/common/Makefile.inc $(srcdir)/libm/ld/Makefile.inc $(srcdir)/libm/complex/Makefile.inc $(srcdir)/libm/fenv/Makefile.inc $(srcdir)/libm/test/Makefile.inc $(srcdir)/libm/machine/aarch64/Makefile.inc $(srcdir)/libm/ld128/Makefile.inc $(srcdir)/libm/machine/amdgcn/Makefile.inc $(srcdir)/libm/machine/arm/Makefile.inc $(srcdir)/libm/machine/i386/Makefile.inc $(srcdir)/libm/ld80/Makefile.inc $(srcdir)/libm/machine/mips/Makefile.inc $(srcdir)/libm/machine/nds32/Makefile.inc $(srcdir)/libm/machine/powerpc/Makefile.inc $(srcdir)/libm/machine/pru/Makefile.inc $(srcdir)/libm/machine/sparc/Makefile.inc $(srcdir)/libm/machine/spu/Makefile.inc $(srcdir)/libm/machine/riscv/Makefile.inc $(srcdir)/libm/machine/x86_64/Makefile.inc $(srcdir)/libm/ld80/Makefile.inc $(am__configure_deps)
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
@@ -5239,7 +5260,7 @@ Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \
cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \
esac;
-$(srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/libc/Makefile.inc $(srcdir)/libc/argz/Makefile.inc $(srcdir)/libc/stdlib/Makefile.inc $(srcdir)/libc/ctype/Makefile.inc $(srcdir)/libc/search/Makefile.inc $(srcdir)/libc/stdio/Makefile.inc $(srcdir)/libc/stdio64/Makefile.inc $(srcdir)/libc/string/Makefile.inc $(srcdir)/libc/signal/Makefile.inc $(srcdir)/libc/time/Makefile.inc $(srcdir)/libc/locale/Makefile.inc $(srcdir)/libc/reent/Makefile.inc $(srcdir)/libc/errno/Makefile.inc $(srcdir)/libc/misc/Makefile.inc $(srcdir)/libc/unix/Makefile.inc $(srcdir)/libc/posix/Makefile.inc $(srcdir)/libc/syscalls/Makefile.inc $(srcdir)/libc/iconv/Makefile.inc $(srcdir)/libc/iconv/ces/Makefile.inc $(srcdir)/libc/iconv/ccs/Makefile.inc $(srcdir)/libc/iconv/ccs/binary/Makefile.inc $(srcdir)/libc/iconv/lib/Makefile.inc $(srcdir)/libc/xdr/Makefile.inc $(srcdir)/libc/ssp/Makefile.inc $(srcdir)/libc/sys/Makefile.inc $(srcdir)/libc/sys/a29khif/Makefile.inc $(srcdir)/libc/sys/amdgcn/Makefile.inc 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$(srcdir)/libc/machine/tic6x/Makefile.inc $(srcdir)/libc/machine/tic80/Makefile.inc $(srcdir)/libc/machine/v850/Makefile.inc $(srcdir)/libc/machine/visium/Makefile.inc $(srcdir)/libc/machine/w65/Makefile.inc $(srcdir)/libc/machine/x86_64/Makefile.inc $(srcdir)/libc/machine/xc16x/Makefile.inc $(srcdir)/libc/machine/xstormy16/Makefile.inc $(srcdir)/libc/machine/xtensa/Makefile.inc $(srcdir)/libc/machine/z8k/Makefile.inc $(srcdir)/libm/Makefile.inc $(srcdir)/libm/mathfp/Makefile.inc $(srcdir)/libm/math/Makefile.inc $(srcdir)/libm/common/Makefile.inc $(srcdir)/libm/ld/Makefile.inc $(srcdir)/libm/complex/Makefile.inc $(srcdir)/libm/fenv/Makefile.inc $(srcdir)/libm/test/Makefile.inc $(srcdir)/libm/machine/aarch64/Makefile.inc $(srcdir)/libm/ld128/Makefile.inc $(srcdir)/libm/machine/amdgcn/Makefile.inc $(srcdir)/libm/machine/arm/Makefile.inc $(srcdir)/libm/machine/i386/Makefile.inc $(srcdir)/libm/ld80/Makefile.inc $(srcdir)/libm/machine/mips/Makefile.inc $(srcdir)/libm/machine/nds32/Makefile.inc $(srcdir)/libm/machine/powerpc/Makefile.inc $(srcdir)/libm/machine/pru/Makefile.inc $(srcdir)/libm/machine/sparc/Makefile.inc $(srcdir)/libm/machine/spu/Makefile.inc $(srcdir)/libm/machine/riscv/Makefile.inc $(srcdir)/libm/machine/x86_64/Makefile.inc $(srcdir)/libm/ld80/Makefile.inc $(am__empty):
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$(SHELL) ./config.status --recheck
@@ -7921,6 +7942,21 @@ libc/sys/w65/libc_a-syscalls.$(OBJEXT): libc/sys/w65/$(am__dirstamp) \
libc/sys/w65/$(DEPDIR)/$(am__dirstamp)
libc/sys/w65/libc_a-trap.$(OBJEXT): libc/sys/w65/$(am__dirstamp) \
libc/sys/w65/$(DEPDIR)/$(am__dirstamp)
+libc/sys/xtensa/$(am__dirstamp):
+ @$(MKDIR_P) libc/sys/xtensa
+ @: > libc/sys/xtensa/$(am__dirstamp)
+libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp):
+ @$(MKDIR_P) libc/sys/xtensa/$(DEPDIR)
+ @: > libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/sys/xtensa/libc_a-creat.$(OBJEXT): \
+ libc/sys/xtensa/$(am__dirstamp) \
+ libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/sys/xtensa/libc_a-isatty.$(OBJEXT): \
+ libc/sys/xtensa/$(am__dirstamp) \
+ libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/sys/xtensa/libc_a-clibrary_init.$(OBJEXT): \
+ libc/sys/xtensa/$(am__dirstamp) \
+ libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp)
libc/sys/z8ksim/$(am__dirstamp):
@$(MKDIR_P) libc/sys/z8ksim
@: > libc/sys/z8ksim/$(am__dirstamp)
@@ -9643,6 +9679,33 @@ libc/machine/xstormy16/libc_a-reallocr.$(OBJEXT): \
libc/machine/xstormy16/libc_a-valloc.$(OBJEXT): \
libc/machine/xstormy16/$(am__dirstamp) \
libc/machine/xstormy16/$(DEPDIR)/$(am__dirstamp)
+libc/machine/xtensa/$(am__dirstamp):
+ @$(MKDIR_P) libc/machine/xtensa
+ @: > libc/machine/xtensa/$(am__dirstamp)
+libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp):
+ @$(MKDIR_P) libc/machine/xtensa/$(DEPDIR)
+ @: > libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/machine/xtensa/libc_a-memcpy.$(OBJEXT): \
+ libc/machine/xtensa/$(am__dirstamp) \
+ libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/machine/xtensa/libc_a-memset.$(OBJEXT): \
+ libc/machine/xtensa/$(am__dirstamp) \
+ libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/machine/xtensa/libc_a-setjmp.$(OBJEXT): \
+ libc/machine/xtensa/$(am__dirstamp) \
+ libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/machine/xtensa/libc_a-strcmp.$(OBJEXT): \
+ libc/machine/xtensa/$(am__dirstamp) \
+ libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/machine/xtensa/libc_a-strcpy.$(OBJEXT): \
+ libc/machine/xtensa/$(am__dirstamp) \
+ libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/machine/xtensa/libc_a-strlen.$(OBJEXT): \
+ libc/machine/xtensa/$(am__dirstamp) \
+ libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
+libc/machine/xtensa/libc_a-strncpy.$(OBJEXT): \
+ libc/machine/xtensa/$(am__dirstamp) \
+ libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
libc/machine/z8k/$(am__dirstamp):
@$(MKDIR_P) libc/machine/z8k
@: > libc/machine/z8k/$(am__dirstamp)
@@ -12370,6 +12433,7 @@ mostlyclean-compile:
-rm -f libc/machine/x86_64/*.$(OBJEXT)
-rm -f libc/machine/xc16x/*.$(OBJEXT)
-rm -f libc/machine/xstormy16/*.$(OBJEXT)
+ -rm -f libc/machine/xtensa/*.$(OBJEXT)
-rm -f libc/machine/z8k/*.$(OBJEXT)
-rm -f libc/misc/*.$(OBJEXT)
-rm -f libc/posix/*.$(OBJEXT)
@@ -12402,6 +12466,7 @@ mostlyclean-compile:
-rm -f libc/sys/sysvnecv70/*.$(OBJEXT)
-rm -f libc/sys/tirtos/*.$(OBJEXT)
-rm -f libc/sys/w65/*.$(OBJEXT)
+ -rm -f libc/sys/xtensa/*.$(OBJEXT)
-rm -f libc/sys/z8ksim/*.$(OBJEXT)
-rm -f libc/syscalls/*.$(OBJEXT)
-rm -f libc/time/*.$(OBJEXT)
@@ -13047,6 +13112,13 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xstormy16/$(DEPDIR)/libc_a-reallocr.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xstormy16/$(DEPDIR)/libc_a-setjmp.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xstormy16/$(DEPDIR)/libc_a-valloc.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xtensa/$(DEPDIR)/libc_a-memcpy.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xtensa/$(DEPDIR)/libc_a-memset.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xtensa/$(DEPDIR)/libc_a-setjmp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xtensa/$(DEPDIR)/libc_a-strcmp.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xtensa/$(DEPDIR)/libc_a-strcpy.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xtensa/$(DEPDIR)/libc_a-strlen.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/xtensa/$(DEPDIR)/libc_a-strncpy.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/z8k/$(DEPDIR)/libc_a-memcmp.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@libc/machine/z8k/$(DEPDIR)/libc_a-memmove.Po@am__quote@
@@ -13852,6 +13924,9 @@ distclean-compile:
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@AMDEP_TRUE@@am__include@ @am__quote@libc/sys/w65/$(DEPDIR)/libc_a-syscalls.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@libc/sys/w65/$(DEPDIR)/libc_a-trap.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/sys/xtensa/$(DEPDIR)/libc_a-clibrary_init.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/sys/xtensa/$(DEPDIR)/libc_a-creat.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@libc/sys/xtensa/$(DEPDIR)/libc_a-isatty.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@libc/sys/z8ksim/$(DEPDIR)/libc_a-glue.Po@am__quote@
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@AMDEP_TRUE@@am__include@ @am__quote@libc/syscalls/$(DEPDIR)/libc_a-sysexecve.Po@am__quote@
@@ -19557,6 +19632,104 @@ libc/machine/xstormy16/libc_a-setjmp.obj: libc/machine/xstormy16/setjmp.S
@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='libc/sys/xtensa/clibrary_init.c' object='libc/sys/xtensa/libc_a-clibrary_init.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libc_a_CPPFLAGS) $(CPPFLAGS) $(libc_a_CFLAGS) $(CFLAGS) -c -o libc/sys/xtensa/libc_a-clibrary_init.obj `if test -f 'libc/sys/xtensa/clibrary_init.c'; then $(CYGPATH_W) 'libc/sys/xtensa/clibrary_init.c'; else $(CYGPATH_W) '$(srcdir)/libc/sys/xtensa/clibrary_init.c'; fi`
+
libc/sys/z8ksim/libc_a-glue.o: libc/sys/z8ksim/glue.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libc_a_CPPFLAGS) $(CPPFLAGS) $(libc_a_CFLAGS) $(CFLAGS) -MT libc/sys/z8ksim/libc_a-glue.o -MD -MP -MF libc/sys/z8ksim/$(DEPDIR)/libc_a-glue.Tpo -c -o libc/sys/z8ksim/libc_a-glue.o `test -f 'libc/sys/z8ksim/glue.c' || echo '$(srcdir)/'`libc/sys/z8ksim/glue.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) libc/sys/z8ksim/$(DEPDIR)/libc_a-glue.Tpo libc/sys/z8ksim/$(DEPDIR)/libc_a-glue.Po
@@ -49580,6 +49795,8 @@ distclean-generic:
-rm -f libc/machine/xc16x/$(am__dirstamp)
-rm -f libc/machine/xstormy16/$(DEPDIR)/$(am__dirstamp)
-rm -f libc/machine/xstormy16/$(am__dirstamp)
+ -rm -f libc/machine/xtensa/$(DEPDIR)/$(am__dirstamp)
+ -rm -f libc/machine/xtensa/$(am__dirstamp)
-rm -f libc/machine/z8k/$(DEPDIR)/$(am__dirstamp)
-rm -f libc/machine/z8k/$(am__dirstamp)
-rm -f libc/misc/$(DEPDIR)/$(am__dirstamp)
@@ -49644,6 +49861,8 @@ distclean-generic:
-rm -f libc/sys/tirtos/$(am__dirstamp)
-rm -f libc/sys/w65/$(DEPDIR)/$(am__dirstamp)
-rm -f libc/sys/w65/$(am__dirstamp)
+ -rm -f libc/sys/xtensa/$(DEPDIR)/$(am__dirstamp)
+ -rm -f libc/sys/xtensa/$(am__dirstamp)
-rm -f libc/sys/z8ksim/$(DEPDIR)/$(am__dirstamp)
-rm -f libc/sys/z8ksim/$(am__dirstamp)
-rm -f libc/syscalls/$(DEPDIR)/$(am__dirstamp)
@@ -49708,7 +49927,7 @@ clean-am: clean-aminfo clean-checkPROGRAMS clean-generic clean-local \
distclean: distclean-am
-rm -f $(am__CONFIG_DISTCLEAN_FILES)
- -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR)
+ -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/xtensa/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/xtensa/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR)
-rm -f Makefile
distclean-am: clean-am distclean-DEJAGNU distclean-compile \
distclean-generic distclean-hdr distclean-local distclean-tags
@@ -49846,7 +50065,7 @@ installcheck-am:
maintainer-clean: maintainer-clean-am
-rm -f $(am__CONFIG_DISTCLEAN_FILES)
-rm -rf $(top_srcdir)/autom4te.cache
- -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR)
+ -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/xtensa/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/xtensa/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR)
-rm -f Makefile
maintainer-clean-am: distclean-am maintainer-clean-aminfo \
maintainer-clean-generic maintainer-clean-local
@@ -49975,7 +50194,7 @@ stmp-targ-include: config.status
$(AM_V_at)s=machine/$(machine_dir)/include d= $(TARG_INCLUDE_CP_DIR)
$(AM_V_at)s=sys/$(sys_dir)/include d= $(TARG_INCLUDE_CP_DIR)
$(AM_V_at)for i in $(call rwildcard,$(srcdir)/libc/sys/$(sys_dir)/include/,*.h); do \
- f=`echo $$i | sed s:$(srcdir)/libc/sys/$(sys_dir)/include/::`; \
+ f=`echo $$i | sed s:^$(srcdir)/libc/sys/$(sys_dir)/include/::`; \
$(MKDIR_P) targ-include/`dirname $$f`; \
cp $$i targ-include/$$f; \
done
@@ -50064,7 +50283,7 @@ install-data-local: install-toollibLIBRARIES install-multi $(INSTALL_DATA_LOCAL)
else true; fi ; \
done ; \
for i in $(call rwildcard,$(srcdir)/libc/sys/$(sys_dir)/include/,*.h); do \
- f=`echo $$i | sed s:$(srcdir)/libc/sys/$(sys_dir)/include/::`; \
+ f=`echo $$i | sed s:^$(srcdir)/libc/sys/$(sys_dir)/include/::`; \
$(MKDIR_P) $(DESTDIR)$(tooldir)/`dirname $$f`; \
$(INSTALL_DATA) $$i $(DESTDIR)$(tooldir)/`dirname $$f`; \
done ; \
diff --git a/newlib/configure b/newlib/configure
index 77ab8eca0..238d62786 100755
--- a/newlib/configure
+++ b/newlib/configure
@@ -603,6 +603,8 @@ HAVE_MULTISUBDIR_FALSE
HAVE_MULTISUBDIR_TRUE
HAVE_DOC_FALSE
HAVE_DOC_TRUE
+HAVE_LIBM_MACHINE_XTENSA_FALSE
+HAVE_LIBM_MACHINE_XTENSA_TRUE
HAVE_LIBM_MACHINE_X86_64_FALSE
HAVE_LIBM_MACHINE_X86_64_TRUE
HAVE_LIBM_MACHINE_RISCV_FALSE
@@ -637,6 +639,8 @@ HAVE_FPMATH_H_FALSE
HAVE_FPMATH_H_TRUE
HAVE_LIBC_MACHINE_Z8K_FALSE
HAVE_LIBC_MACHINE_Z8K_TRUE
+HAVE_LIBC_MACHINE_XTENSA_FALSE
+HAVE_LIBC_MACHINE_XTENSA_TRUE
HAVE_LIBC_MACHINE_XSTORMY16_FALSE
HAVE_LIBC_MACHINE_XSTORMY16_TRUE
HAVE_LIBC_MACHINE_XC16X_FALSE
@@ -751,6 +755,8 @@ HAVE_LIBC_MACHINE_AMDGCN_FALSE
HAVE_LIBC_MACHINE_AMDGCN_TRUE
HAVE_LIBC_MACHINE_AARCH64_FALSE
HAVE_LIBC_MACHINE_AARCH64_TRUE
+XTENSA_ESP32_PSRAM_CACHE_FIX_FALSE
+XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE
HAVE_SPU_EA_FALSE
HAVE_SPU_EA_TRUE
SH64_FALSE
@@ -767,6 +773,8 @@ HAVE_LONG_DOUBLE_FALSE
HAVE_LONG_DOUBLE_TRUE
HAVE_LIBC_SYS_Z8KSIM_DIR_FALSE
HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE
+HAVE_LIBC_SYS_XTENSA_DIR_FALSE
+HAVE_LIBC_SYS_XTENSA_DIR_TRUE
HAVE_LIBC_SYS_W65_DIR_FALSE
HAVE_LIBC_SYS_W65_DIR_TRUE
HAVE_LIBC_SYS_TIRTOS_DIR_FALSE
@@ -5501,6 +5509,13 @@ fi
else
HAVE_LIBC_SYS_W65_DIR_TRUE='#'
HAVE_LIBC_SYS_W65_DIR_FALSE=
+fi
+ if test "${sys_dir}" = xtensa; then
+ HAVE_LIBC_SYS_XTENSA_DIR_TRUE=
+ HAVE_LIBC_SYS_XTENSA_DIR_FALSE='#'
+else
+ HAVE_LIBC_SYS_XTENSA_DIR_TRUE='#'
+ HAVE_LIBC_SYS_XTENSA_DIR_FALSE=
fi
if test "${sys_dir}" = z8ksim; then
HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE=
@@ -5716,6 +5731,15 @@ else
fi
+ if echo $CC | grep mfix-esp32-psram-cache-issue >/dev/null 2>&1; then
+ XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE=
+ XTENSA_ESP32_PSRAM_CACHE_FIX_FALSE='#'
+else
+ XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE='#'
+ XTENSA_ESP32_PSRAM_CACHE_FIX_FALSE=
+fi
+
+
if test "${machine_dir}" = aarch64; then
HAVE_LIBC_MACHINE_AARCH64_TRUE=
@@ -6115,6 +6139,13 @@ fi
else
HAVE_LIBC_MACHINE_XSTORMY16_TRUE='#'
HAVE_LIBC_MACHINE_XSTORMY16_FALSE=
+fi
+ if test "${machine_dir}" = xtensa; then
+ HAVE_LIBC_MACHINE_XTENSA_TRUE=
+ HAVE_LIBC_MACHINE_XTENSA_FALSE='#'
+else
+ HAVE_LIBC_MACHINE_XTENSA_TRUE='#'
+ HAVE_LIBC_MACHINE_XTENSA_FALSE=
fi
if test "${machine_dir}" = z8k; then
HAVE_LIBC_MACHINE_Z8K_TRUE=
@@ -6318,6 +6349,14 @@ else
HAVE_LIBM_MACHINE_X86_64_FALSE=
fi
+ if test "${libm_machine_dir}" = "xtensa"; then
+ HAVE_LIBM_MACHINE_XTENSA_TRUE=
+ HAVE_LIBM_MACHINE_XTENSA_FALSE='#'
+else
+ HAVE_LIBM_MACHINE_XTENSA_TRUE='#'
+ HAVE_LIBM_MACHINE_XTENSA_FALSE=
+fi
+
@@ -7617,6 +7656,10 @@ if test -z "${HAVE_LIBC_SYS_W65_DIR_TRUE}" && test -z "${HAVE_LIBC_SYS_W65_DIR_F
as_fn_error $? "conditional \"HAVE_LIBC_SYS_W65_DIR\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${HAVE_LIBC_SYS_XTENSA_DIR_TRUE}" && test -z "${HAVE_LIBC_SYS_XTENSA_DIR_FALSE}"; then
+ as_fn_error $? "conditional \"HAVE_LIBC_SYS_XTENSA_DIR\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
if test -z "${HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE}" && test -z "${HAVE_LIBC_SYS_Z8KSIM_DIR_FALSE}"; then
as_fn_error $? "conditional \"HAVE_LIBC_SYS_Z8KSIM_DIR\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
@@ -7649,6 +7692,10 @@ if test -z "${HAVE_SPU_EA_TRUE}" && test -z "${HAVE_SPU_EA_FALSE}"; then
as_fn_error $? "conditional \"HAVE_SPU_EA\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${XTENSA_ESP32_PSRAM_CACHE_FIX_TRUE}" && test -z "${XTENSA_ESP32_PSRAM_CACHE_FIX_FALSE}"; then
+ as_fn_error $? "conditional \"XTENSA_ESP32_PSRAM_CACHE_FIX\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
if test -z "${HAVE_LIBC_MACHINE_AARCH64_TRUE}" && test -z "${HAVE_LIBC_MACHINE_AARCH64_FALSE}"; then
as_fn_error $? "conditional \"HAVE_LIBC_MACHINE_AARCH64\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
@@ -7877,6 +7924,10 @@ if test -z "${HAVE_LIBC_MACHINE_XSTORMY16_TRUE}" && test -z "${HAVE_LIBC_MACHINE
as_fn_error $? "conditional \"HAVE_LIBC_MACHINE_XSTORMY16\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${HAVE_LIBC_MACHINE_XTENSA_TRUE}" && test -z "${HAVE_LIBC_MACHINE_XTENSA_FALSE}"; then
+ as_fn_error $? "conditional \"HAVE_LIBC_MACHINE_XTENSA\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
if test -z "${HAVE_LIBC_MACHINE_Z8K_TRUE}" && test -z "${HAVE_LIBC_MACHINE_Z8K_FALSE}"; then
as_fn_error $? "conditional \"HAVE_LIBC_MACHINE_Z8K\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
@@ -7945,6 +7996,10 @@ if test -z "${HAVE_LIBM_MACHINE_X86_64_TRUE}" && test -z "${HAVE_LIBM_MACHINE_X8
as_fn_error $? "conditional \"HAVE_LIBM_MACHINE_X86_64\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${HAVE_LIBM_MACHINE_XTENSA_TRUE}" && test -z "${HAVE_LIBM_MACHINE_XTENSA_FALSE}"; then
+ as_fn_error $? "conditional \"HAVE_LIBM_MACHINE_XTENSA\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
if test -z "${HAVE_DOC_TRUE}" && test -z "${HAVE_DOC_FALSE}"; then
as_fn_error $? "conditional \"HAVE_DOC\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
diff --git a/newlib/configure.host b/newlib/configure.host
index 5f427526d..386183466 100644
--- a/newlib/configure.host
+++ b/newlib/configure.host
@@ -365,6 +365,13 @@ case "${host_cpu}" in
newlib_cflags="${newlib_cflags} -DMALLOC_PROVIDED"
newlib_cflags="${newlib_cflags} -DPREFER_SIZE_OVER_SPEED"
;;
+ xtensa)
+ libm_machine_dir=xtensa
+ machine_dir=xtensa
+ newlib_cflags="${newlib_cflags} -mlongcalls"
+ default_newlib_atexit_dynamic_alloc="no"
+ have_init_fini=no
+ ;;
z8k)
machine_dir=z8k
;;
@@ -569,6 +576,9 @@ case "${host}" in
w65-*-*)
sys_dir=w65
;;
+ xtensa*-*-*)
+ sys_dir=xtensa
+ ;;
z8k-*-coff)
sys_dir=z8ksim
;;
@@ -861,6 +871,9 @@ newlib_cflags="${newlib_cflags} -DCLOCK_PROVIDED -DMALLOC_PROVIDED -DEXIT_PROVID
xstormy16-*-*)
syscall_dir=syscalls
;;
+ xtensa*-*-* | xtensa*-*)
+ syscall_dir=syscalls
+ ;;
z8k-*-*)
syscall_dir=syscalls
;;
diff --git a/newlib/libc/acinclude.m4 b/newlib/libc/acinclude.m4
index 42662669f..24148b13f 100644
--- a/newlib/libc/acinclude.m4
+++ b/newlib/libc/acinclude.m4
@@ -23,6 +23,7 @@ m4_foreach_w([SYS_DIR], [
sh sysmec sysnec810 sysnecv850 sysvi386 sysvnecv70
tic80 tirtos
w65
+ xtensa
z8ksim
], [AM_CONDITIONAL([HAVE_LIBC_SYS_]m4_toupper(SYS_DIR)[_DIR], test "${sys_dir}" = SYS_DIR)])
@@ -38,6 +39,7 @@ m4_include([libc/machine/nds32/acinclude.m4])
m4_include([libc/machine/powerpc/acinclude.m4])
m4_include([libc/machine/sh/acinclude.m4])
m4_include([libc/machine/spu/acinclude.m4])
+m4_include([libc/machine/xtensa/acinclude.m4])
m4_foreach_w([MACHINE], [
aarch64 amdgcn arc arm
@@ -58,7 +60,7 @@ m4_foreach_w([MACHINE], [
tic4x tic6x tic80
v850 visium
w65
- x86_64 xc16x xstormy16
+ x86_64 xc16x xstormy16 xtensa
z8k
], [AM_CONDITIONAL([HAVE_LIBC_MACHINE_]m4_toupper(MACHINE), test "${machine_dir}" = MACHINE)])
diff --git a/newlib/libc/include/machine/ieeefp.h b/newlib/libc/include/machine/ieeefp.h
index abadf520b..ede75e1aa 100644
--- a/newlib/libc/include/machine/ieeefp.h
+++ b/newlib/libc/include/machine/ieeefp.h
@@ -506,6 +506,10 @@
#define __IEEE_LITTLE_ENDIAN
#endif
+#ifdef __XTENSA_EB__
+#define __IEEE_BIG_ENDIAN
+#endif
+
#ifdef __CYGWIN__
#define __OBSOLETE_MATH_DEFAULT 0
#endif
diff --git a/newlib/libc/include/machine/setjmp.h b/newlib/libc/include/machine/setjmp.h
index 29b76cec1..e3534e18d 100644
--- a/newlib/libc/include/machine/setjmp.h
+++ b/newlib/libc/include/machine/setjmp.h
@@ -304,6 +304,35 @@ _BEGIN_STD_C
#define _JBLEN 8
#endif
+#ifdef __XTENSA__
+#if __XTENSA_WINDOWED_ABI__
+
+/* The jmp_buf structure for Xtensa windowed ABI holds the following
+ (where "proc" is the procedure that calls setjmp): 4-12 registers
+ from the window of proc, the 4 words from the save area at proc's $sp
+ (in case a subsequent alloca in proc moves $sp), and the return
+ address within proc. Everything else is saved on the stack in the
+ normal save areas. The jmp_buf structure is:
+
+ struct jmp_buf {
+ int regs[12];
+ int save[4];
+ void *return_address;
+ }
+
+ See the setjmp code for details. */
+
+/* sizeof(struct jmp_buf) */
+#define _JBLEN 17
+
+#else /* __XTENSA_CALL0_ABI__ */
+
+/* a0, a1, a12, a13, a14, a15 */
+#define _JBLEN 6
+
+#endif /* __XTENSA_CALL0_ABI__ */
+#endif /* __XTENSA__ */
+
#ifdef __mep__
/* 16 GPRs, pc, hi, lo */
#define _JBLEN 19
diff --git a/newlib/libc/machine/Makefile.inc b/newlib/libc/machine/Makefile.inc
index 8aae2c52c..a53cf9c10 100644
--- a/newlib/libc/machine/Makefile.inc
+++ b/newlib/libc/machine/Makefile.inc
@@ -169,6 +169,9 @@ endif
if HAVE_LIBC_MACHINE_XSTORMY16
include %D%/xstormy16/Makefile.inc
endif
+if HAVE_LIBC_MACHINE_XTENSA
+include %D%/xtensa/Makefile.inc
+endif
if HAVE_LIBC_MACHINE_Z8K
include %D%/z8k/Makefile.inc
endif
diff --git a/newlib/libc/machine/xtensa/Makefile.inc b/newlib/libc/machine/xtensa/Makefile.inc
new file mode 100644
index 000000000..158c2befe
--- /dev/null
+++ b/newlib/libc/machine/xtensa/Makefile.inc
@@ -0,0 +1,8 @@
+libc_a_SOURCES += \
+ %D%/memcpy.S %D%/memset.S %D%/setjmp.S %D%/strcmp.S %D%/strcpy.S \
+ %D%/strlen.S %D%/strncpy.S
+
+if XTENSA_ESP32_PSRAM_CACHE_FIX
+libc_a_CPPFLAGS_%C% = \
+ -DXTENSA_ESP32_PSRAM_CACHE_FIX
+endif
diff --git a/newlib/libc/machine/xtensa/acinclude.m4 b/newlib/libc/machine/xtensa/acinclude.m4
new file mode 100644
index 000000000..863d7507d
--- /dev/null
+++ b/newlib/libc/machine/xtensa/acinclude.m4
@@ -0,0 +1 @@
+AM_CONDITIONAL([XTENSA_ESP32_PSRAM_CACHE_FIX], [echo $CC | grep mfix-esp32-psram-cache-issue >/dev/null 2>&1])
diff --git a/newlib/libc/machine/xtensa/memcpy.S b/newlib/libc/machine/xtensa/memcpy.S
new file mode 100644
index 000000000..77b026a45
--- /dev/null
+++ b/newlib/libc/machine/xtensa/memcpy.S
@@ -0,0 +1,343 @@
+/* ANSI C standard library function memcpy.
+
+ Copyright (c) 2002-2008 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "xtensa-asm.h"
+
+/* If the Xtensa Unaligned Load Exception option is not used, this
+ code can run a few cycles faster by relying on the low address bits
+ being ignored. However, if the code is then run with an Xtensa ISS
+ client that checks for unaligned accesses, it will produce a lot of
+ warning messages. Set this flag to disable the use of unaligned
+ accesses and keep the ISS happy. */
+
+/* #define UNALIGNED_ADDRESSES_CHECKED XCHAL_UNALIGNED_LOAD_EXCEPTION */
+#define UNALIGNED_ADDRESSES_CHECKED 1
+
+
+/* void *memcpy (void *dst, const void *src, size_t len)
+
+ The algorithm is as follows:
+
+ If the destination is unaligned, align it by conditionally
+ copying 1- and/or 2-byte pieces.
+
+ If the source is aligned, copy 16 bytes with a loop, and then finish up
+ with 8, 4, 2, and 1-byte copies conditional on the length.
+
+ Else (if source is unaligned), do the same, but use SRC to align the
+ source data.
+
+ This code tries to use fall-through branches for the common
+ case of aligned source and destination and multiple of 4 (or 8) length. */
+
+
+/* Byte by byte copy. */
+
+ .text
+ .begin schedule
+ .align XCHAL_INST_FETCH_WIDTH
+ .literal_position
+__memcpy_aux:
+
+ /* Skip bytes to get proper alignment for three-byte loop */
+.skip XCHAL_INST_FETCH_WIDTH - 3
+
+.Lbytecopy:
+#if XCHAL_HAVE_LOOPS
+ loopnez a4, 2f
+#else
+ beqz a4, 2f
+ add a7, a3, a4 // a7 = end address for source
+#endif
+1: l8ui a6, a3, 0
+ addi a3, a3, 1
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ nop
+ nop
+ nop
+#endif
+ s8i a6, a5, 0
+ addi a5, a5, 1
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+#if !XCHAL_HAVE_LOOPS
+ bltu a3, a7, 1b
+#endif
+2: leaf_return
+
+
+/* Destination is unaligned. */
+
+ .align 4
+.Ldst1mod2: // dst is only byte aligned
+
+ /* Do short copies byte-by-byte. */
+ bltui a4, 7, .Lbytecopy
+
+ /* Copy 1 byte. */
+ l8ui a6, a3, 0
+ addi a3, a3, 1
+ addi a4, a4, -1
+ s8i a6, a5, 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ addi a5, a5, 1
+
+ /* Return to main algorithm if dst is now aligned. */
+ bbci.l a5, 1, .Ldstaligned
+
+.Ldst2mod4: // dst has 16-bit alignment
+
+ /* Do short copies byte-by-byte. */
+ bltui a4, 6, .Lbytecopy
+
+ /* Copy 2 bytes. */
+ l8ui a6, a3, 0
+ l8ui a7, a3, 1
+ addi a3, a3, 2
+ addi a4, a4, -2
+ s8i a6, a5, 0
+ s8i a7, a5, 1
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ addi a5, a5, 2
+
+ /* dst is now aligned; return to main algorithm. */
+ j .Ldstaligned
+
+
+ .align 4
+ .global memcpy
+ .type memcpy, @function
+memcpy:
+ leaf_entry sp, 16
+ /* a2 = dst, a3 = src, a4 = len */
+
+ mov a5, a2 // copy dst so that a2 is return value
+ bbsi.l a2, 0, .Ldst1mod2
+ bbsi.l a2, 1, .Ldst2mod4
+.Ldstaligned:
+
+ /* Get number of loop iterations with 16B per iteration. */
+ srli a7, a4, 4
+
+ /* Check if source is aligned. */
+ slli a8, a3, 30
+ bnez a8, .Lsrcunaligned
+
+ /* Destination and source are word-aligned, use word copy. */
+#if XCHAL_HAVE_LOOPS
+ loopnez a7, 2f
+#else
+ beqz a7, 2f
+ slli a8, a7, 4
+ add a8, a8, a3 // a8 = end of last 16B source chunk
+#endif
+
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+
+1: l32i a6, a3, 0
+ l32i a7, a3, 4
+ s32i a6, a5, 0
+ s32i a7, a5, 4
+ memw
+ l32i a6, a3, 8
+ l32i a7, a3, 12
+ s32i a6, a5, 8
+ s32i a7, a5, 12
+ memw
+
+ addi a3, a3, 16
+ addi a5, a5, 16
+
+#else
+
+1: l32i a6, a3, 0
+ l32i a7, a3, 4
+ s32i a6, a5, 0
+ l32i a6, a3, 8
+ s32i a7, a5, 4
+ l32i a7, a3, 12
+ s32i a6, a5, 8
+ addi a3, a3, 16
+ s32i a7, a5, 12
+ addi a5, a5, 16
+
+#endif
+
+
+#if !XCHAL_HAVE_LOOPS
+ bltu a3, a8, 1b
+#endif
+
+ /* Copy any leftover pieces smaller than 16B. */
+2: bbci.l a4, 3, 3f
+
+ /* Copy 8 bytes. */
+ l32i a6, a3, 0
+ l32i a7, a3, 4
+ addi a3, a3, 8
+ s32i a6, a5, 0
+ s32i a7, a5, 4
+ addi a5, a5, 8
+
+3: bbsi.l a4, 2, 4f
+ bbsi.l a4, 1, 5f
+ bbsi.l a4, 0, 6f
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+ .align 4
+ /* Copy 4 bytes. */
+4: l32i a6, a3, 0
+ addi a3, a3, 4
+ s32i a6, a5, 0
+ addi a5, a5, 4
+ bbsi.l a4, 1, 5f
+ bbsi.l a4, 0, 6f
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+ /* Copy 2 bytes. */
+5: l16ui a6, a3, 0
+ addi a3, a3, 2
+ s16i a6, a5, 0
+ addi a5, a5, 2
+ bbsi.l a4, 0, 6f
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+ /* Copy 1 byte. */
+6: l8ui a6, a3, 0
+ s8i a6, a5, 0
+
+.Ldone:
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+
+/* Destination is aligned; source is unaligned. */
+
+ .align 4
+.Lsrcunaligned:
+ /* Avoid loading anything for zero-length copies. */
+ beqz a4, .Ldone
+
+ /* Copy 16 bytes per iteration for word-aligned dst and
+ unaligned src. */
+ ssa8 a3 // set shift amount from byte offset
+#if UNALIGNED_ADDRESSES_CHECKED
+ srli a11, a8, 30 // save unalignment offset for below
+ sub a3, a3, a11 // align a3
+#endif
+ l32i a6, a3, 0 // load first word
+#if XCHAL_HAVE_LOOPS
+ loopnez a7, 2f
+#else
+ beqz a7, 2f
+ slli a10, a7, 4
+ add a10, a10, a3 // a10 = end of last 16B source chunk
+#endif
+1: l32i a7, a3, 4
+ l32i a8, a3, 8
+ src_b a6, a6, a7
+ s32i a6, a5, 0
+ l32i a9, a3, 12
+ src_b a7, a7, a8
+ s32i a7, a5, 4
+ l32i a6, a3, 16
+ src_b a8, a8, a9
+ s32i a8, a5, 8
+ addi a3, a3, 16
+ src_b a9, a9, a6
+ s32i a9, a5, 12
+ addi a5, a5, 16
+#if !XCHAL_HAVE_LOOPS
+ bltu a3, a10, 1b
+#endif
+
+2: bbci.l a4, 3, 3f
+
+ /* Copy 8 bytes. */
+ l32i a7, a3, 4
+ l32i a8, a3, 8
+ src_b a6, a6, a7
+ s32i a6, a5, 0
+ addi a3, a3, 8
+ src_b a7, a7, a8
+ s32i a7, a5, 4
+ addi a5, a5, 8
+ mov a6, a8
+
+3: bbci.l a4, 2, 4f
+
+ /* Copy 4 bytes. */
+ l32i a7, a3, 4
+ addi a3, a3, 4
+ src_b a6, a6, a7
+ s32i a6, a5, 0
+ addi a5, a5, 4
+ mov a6, a7
+4:
+#if UNALIGNED_ADDRESSES_CHECKED
+ add a3, a3, a11 // readjust a3 with correct misalignment
+#endif
+ bbsi.l a4, 1, 5f
+ bbsi.l a4, 0, 6f
+ leaf_return
+
+ /* Copy 2 bytes. */
+5: l8ui a6, a3, 0
+ l8ui a7, a3, 1
+ addi a3, a3, 2
+ s8i a6, a5, 0
+ s8i a7, a5, 1
+ addi a5, a5, 2
+ bbsi.l a4, 0, 6f
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+ /* Copy 1 byte. */
+6: l8ui a6, a3, 0
+ s8i a6, a5, 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+ .end schedule
+
+ .size memcpy, . - memcpy
diff --git a/newlib/libc/machine/xtensa/memset.S b/newlib/libc/machine/xtensa/memset.S
new file mode 100644
index 000000000..48b5829d7
--- /dev/null
+++ b/newlib/libc/machine/xtensa/memset.S
@@ -0,0 +1,193 @@
+/* ANSI C standard library function memset.
+
+ Copyright (c) 2001-2008 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "xtensa-asm.h"
+
+/* void *memset (void *dst, int c, size_t length)
+
+ The algorithm is as follows:
+
+ Create a word with c in all byte positions.
+
+ If the destination is aligned, set 16B chunks with a loop, and then
+ finish up with 8B, 4B, 2B, and 1B stores conditional on the length.
+
+ If the destination is unaligned, align it by conditionally
+ setting 1B and/or 2B and then go to aligned case.
+
+ This code tries to use fall-through branches for the common
+ case of an aligned destination (except for the branches to
+ the alignment labels). */
+
+
+/* Byte-by-byte set. */
+
+ .text
+ .begin schedule
+ .align XCHAL_INST_FETCH_WIDTH
+ .literal_position
+__memset_aux:
+
+ /* Skip bytes to get proper alignment for three-byte loop */
+.skip XCHAL_INST_FETCH_WIDTH - 3
+
+.Lbyteset:
+#if XCHAL_HAVE_LOOPS
+ loopnez a4, 2f
+#else
+ beqz a4, 2f
+ add a6, a5, a4 // a6 = ending address
+#endif
+1: s8i a3, a5, 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ addi a5, a5, 1
+#if !XCHAL_HAVE_LOOPS
+ bltu a5, a6, 1b
+#endif
+2: leaf_return
+
+
+/* Destination is unaligned. */
+
+ .align 4
+
+.Ldst1mod2: // dst is only byte aligned
+
+ /* Do short sizes byte-by-byte. */
+ bltui a4, 8, .Lbyteset
+
+ /* Set 1 byte. */
+ s8i a3, a5, 0
+ addi a5, a5, 1
+ addi a4, a4, -1
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+
+ /* Now retest if dst is aligned. */
+ _bbci.l a5, 1, .Ldstaligned
+
+.Ldst2mod4: // dst has 16-bit alignment
+
+ /* Do short sizes byte-by-byte. */
+ bltui a4, 8, .Lbyteset
+
+ /* Set 2 bytes. */
+ s16i a3, a5, 0
+ addi a5, a5, 2
+ addi a4, a4, -2
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+
+ /* dst is now aligned; return to main algorithm */
+ j .Ldstaligned
+
+
+ .align 4
+ .global memset
+ .type memset, @function
+memset:
+ leaf_entry sp, 16
+ /* a2 = dst, a3 = c, a4 = length */
+
+ /* Duplicate character into all bytes of word. */
+ extui a3, a3, 0, 8
+ slli a7, a3, 8
+ or a3, a3, a7
+ slli a7, a3, 16
+ or a3, a3, a7
+
+ mov a5, a2 // copy dst so that a2 is return value
+
+ /* Check if dst is unaligned. */
+ _bbsi.l a2, 0, .Ldst1mod2
+ _bbsi.l a2, 1, .Ldst2mod4
+.Ldstaligned:
+
+ /* Get number of loop iterations with 16B per iteration. */
+ srli a7, a4, 4
+
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ //do not do this if we have less than one iteration to do
+ beqz a7, 2f
+ //this seems to work to prefetch the cache line
+ s32i a3, a5, 0
+ nop
+#endif
+
+ /* Destination is word-aligned. */
+#if XCHAL_HAVE_LOOPS
+ loopnez a7, 2f
+#else
+ beqz a7, 2f
+ slli a6, a7, 4
+ add a6, a6, a5 // a6 = end of last 16B chunk
+#endif
+ /* Set 16 bytes per iteration. */
+1: s32i a3, a5, 0
+ s32i a3, a5, 4
+ s32i a3, a5, 8
+ s32i a3, a5, 12
+ addi a5, a5, 16
+#if !XCHAL_HAVE_LOOPS
+ bltu a5, a6, 1b
+#endif
+
+ /* Set any leftover pieces smaller than 16B. */
+2: bbci.l a4, 3, 3f
+
+ /* Set 8 bytes. */
+ s32i a3, a5, 0
+ s32i a3, a5, 4
+ addi a5, a5, 8
+
+3: bbci.l a4, 2, 4f
+
+ /* Set 4 bytes. */
+ s32i a3, a5, 0
+ addi a5, a5, 4
+
+4: bbci.l a4, 1, 5f
+
+ /* Set 2 bytes. */
+ s16i a3, a5, 0
+ addi a5, a5, 2
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+
+5: bbci.l a4, 0, 6f
+
+ /* Set 1 byte. */
+ s8i a3, a5, 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+6: leaf_return
+
+ .end schedule
+
+ .size memset, . - memset
diff --git a/newlib/libc/machine/xtensa/setjmp.S b/newlib/libc/machine/xtensa/setjmp.S
new file mode 100644
index 000000000..c32d443f2
--- /dev/null
+++ b/newlib/libc/machine/xtensa/setjmp.S
@@ -0,0 +1,252 @@
+/* setjmp/longjmp functions for Xtensa.
+
+ Copyright (c) 2001-2006 by Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+/* Windowed ABI:
+
+ This implementation relies heavily on the Xtensa register window
+ mechanism. Setjmp flushes all the windows except its own to the
+ stack and then copies registers from the save areas on the stack
+ into the jmp_buf structure, along with the return address of the call
+ to setjmp. Longjmp invalidates all the windows except its own, and
+ then sets things up so that it will return to the right place,
+ using a window underflow to automatically restore the registers.
+
+ Note that it would probably be sufficient to only copy the
+ registers from setjmp's caller into jmp_buf. However, we also copy
+ the save area located at the stack pointer of setjmp's caller.
+ This save area will typically remain intact until the longjmp call.
+ The one exception is when there is an intervening alloca in
+ setjmp's caller. This is certainly an unusual situation and is
+ likely to cause problems in any case (the storage allocated on the
+ stack cannot be safely accessed following the longjmp). As bad as
+ it is, on most systems this situation would not necessarily lead to
+ a catastrophic failure. If we did not preserve the extra save area
+ on Xtensa, however, it would. When setjmp's caller returns after a
+ longjmp, there will be a window underflow; an invalid return
+ address or stack pointer in the save area will almost certainly
+ lead to a crash. Keeping a copy of the extra save area in the
+ jmp_buf avoids this with only a small additional cost. If setjmp
+ and longjmp are ever time-critical, this could be removed.
+
+
+ Call0 ABI:
+
+ Much like other ABIs, this version just saves the necessary registers
+ to the stack and restores them later. Much less needs to be done. */
+
+#include "xtensa-asm.h"
+
+#define SYS_nop 0
+
+
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+
+/* int setjmp (jmp_buf env) */
+
+ .text
+ .align 4
+ .literal_position
+ .global setjmp
+ .type setjmp, @function
+setjmp:
+ entry sp, 16
+
+ /* Flush registers. */
+ mov a4, a2 // save a2 (jmp_buf)
+ movi a2, SYS_nop
+ syscall
+ mov a2, a4 // restore a2
+
+ /* Copy the register save area at (sp - 16). */
+ addi a5, a1, -16
+ l32i a3, a5, 0
+ l32i a4, a5, 4
+ s32i a3, a2, 0
+ s32i a4, a2, 4
+ l32i a3, a5, 8
+ l32i a4, a5, 12
+ s32i a3, a2, 8
+ s32i a4, a2, 12
+
+ /* Copy 0-8 words from the register overflow area. */
+ extui a3, a0, 30, 2
+ blti a3, 2, .Lendsj
+ l32i a7, a1, 4
+ slli a4, a3, 4
+ sub a5, a7, a4
+ addi a6, a2, 16
+ addi a7, a7, -16 // a7 = end of register overflow area
+.Lsjloop:
+ l32i a3, a5, 0
+ l32i a4, a5, 4
+ s32i a3, a6, 0
+ s32i a4, a6, 4
+ l32i a3, a5, 8
+ l32i a4, a5, 12
+ s32i a3, a6, 8
+ s32i a4, a6, 12
+ addi a5, a5, 16
+ addi a6, a6, 16
+ blt a5, a7, .Lsjloop
+.Lendsj:
+
+ /* Copy the register save area at sp. */
+ l32i a3, a1, 0
+ l32i a4, a1, 4
+ s32i a3, a2, 48
+ s32i a4, a2, 52
+ l32i a3, a1, 8
+ l32i a4, a1, 12
+ s32i a3, a2, 56
+ s32i a4, a2, 60
+
+ /* Save the return address, including the window size bits. */
+ s32i a0, a2, 64
+
+ movi a2, 0
+ retw
+ .size setjmp, . - setjmp
+
+
+/* void longjmp (jmp_buf env, int val) */
+
+ .align 4
+ .literal_position
+ .global longjmp
+ .type longjmp, @function
+longjmp:
+ entry sp, 16
+ /* a2 == &env, a3 == val */
+
+ /* Invalidate all but the current window;
+ set WindowStart to (1 << WindowBase). */
+ rsr a5, WINDOWBASE
+ movi a4, 1
+ ssl a5
+ sll a4, a4
+ wsr a4, WINDOWSTART
+ rsync
+
+ /* Return to the return address of the setjmp, using the
+ window size bits from the setjmp call so that the caller
+ will be able to find the return value that we put in a2. */
+
+ l32i a0, a2, 64
+
+ /* Copy the first 4 saved registers from jmp_buf into the save area
+ at the current sp so that the values will be restored to registers
+ when longjmp returns. */
+
+ addi a7, a1, -16
+ l32i a4, a2, 0
+ l32i a5, a2, 4
+ s32i a4, a7, 0
+ s32i a5, a7, 4
+ l32i a4, a2, 8
+ l32i a5, a2, 12
+ s32i a4, a7, 8
+ s32i a5, a7, 12
+
+ /* Copy the remaining 0-8 saved registers. */
+ extui a7, a0, 30, 2
+ blti a7, 2, .Lendlj
+ l32i a8, a2, 52
+ slli a4, a7, 4
+ sub a6, a8, a4
+ addi a5, a2, 16
+ addi a8, a8, -16 // a8 = end of register overflow area
+.Lljloop:
+ l32i a7, a5, 0
+ l32i a4, a5, 4
+ s32i a7, a6, 0
+ s32i a4, a6, 4
+ l32i a7, a5, 8
+ l32i a4, a5, 12
+ s32i a7, a6, 8
+ s32i a4, a6, 12
+ addi a5, a5, 16
+ addi a6, a6, 16
+ blt a6, a8, .Lljloop
+.Lendlj:
+
+ /* The 4 words saved from the register save area at the target's
+ sp are copied back to the target procedure's save area. The
+ only point of this is to prevent a catastrophic failure in
+ case the contents were moved by an alloca after calling
+ setjmp. This is a bit paranoid but it doesn't cost much. */
+
+ l32i a7, a2, 4 // load the target stack pointer
+ addi a7, a7, -16 // find the destination save area
+ l32i a4, a2, 48
+ l32i a5, a2, 52
+ s32i a4, a7, 0
+ s32i a5, a7, 4
+ l32i a4, a2, 56
+ l32i a5, a2, 60
+ s32i a4, a7, 8
+ s32i a5, a7, 12
+
+ /* Return val ? val : 1. */
+ movi a2, 1
+ movnez a2, a3, a3
+
+ retw
+ .size longjmp, . - longjmp
+
+#else /* CALL0 ABI */
+
+ .text
+ .align 4
+ .literal_position
+ .global setjmp
+ .type setjmp, @function
+setjmp:
+ s32i a0, a2, 0
+ s32i a1, a2, 4
+ s32i a12, a2, 8
+ s32i a13, a2, 12
+ s32i a14, a2, 16
+ s32i a15, a2, 20
+ movi a2, 0
+ ret
+ .size setjmp, . - setjmp
+
+ .align 4
+ .literal_position
+ .global longjmp
+ .type longjmp, @function
+longjmp:
+ l32i a0, a2, 0
+ l32i a12, a2, 8
+ l32i a13, a2, 12
+ l32i a14, a2, 16
+ l32i a15, a2, 20
+ l32i a1, a2, 4
+ /* Return val ? val : 1. */
+ movi a2, 1
+ movnez a2, a3, a3
+
+ ret
+ .size longjmp, .-longjmp
+
+#endif /* CALL0 ABI */
diff --git a/newlib/libc/machine/xtensa/strcmp.S b/newlib/libc/machine/xtensa/strcmp.S
new file mode 100644
index 000000000..49cb80581
--- /dev/null
+++ b/newlib/libc/machine/xtensa/strcmp.S
@@ -0,0 +1,353 @@
+/* ANSI C standard library function strcmp.
+
+ Copyright (c) 2001-20012 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "xtensa-asm.h"
+
+#define MASK4 0x40404040
+
+
+#if XCHAL_HAVE_L32R
+ .literal .Lmask0, MASK0
+ .literal .Lmask1, MASK1
+ .literal .Lmask2, MASK2
+ .literal .Lmask3, MASK3
+ .literal .Lmask4, MASK4
+#endif /* XCHAL_HAVE_L32R */
+
+ .text
+ .align 4
+ .literal_position
+ .global strcmp
+ .type strcmp, @function
+strcmp:
+
+ leaf_entry sp, 16
+ /* a2 = s1, a3 = s2 */
+
+ l8ui a8, a2, 0 // byte 0 from s1
+ l8ui a9, a3, 0 // byte 0 from s2
+ movi a10, 3 // mask
+ bne a8, a9, .Lretdiff
+
+ or a11, a2, a3
+ bnone a11, a10, .Laligned
+
+ xor a11, a2, a3 // compare low two bits of s1 and s2
+ bany a11, a10, .Lunaligned // if they have different alignment
+
+ /* s1/s2 are not word-aligned. */
+ addi a2, a2, 1 // advance s1
+ beqz a8, .Leq // bytes equal, if zero, strings are equal
+ addi a3, a3, 1 // advance s2
+ bnone a2, a10, .Laligned // if s1/s2 now aligned
+ l8ui a8, a2, 0 // byte 1 from s1
+ l8ui a9, a3, 0 // byte 1 from s2
+ addi a2, a2, 1 // advance s1
+ bne a8, a9, .Lretdiff // if different, return difference
+ beqz a8, .Leq // bytes equal, if zero, strings are equal
+ addi a3, a3, 1 // advance s2
+ bnone a2, a10, .Laligned // if s1/s2 now aligned
+ l8ui a8, a2, 0 // byte 2 from s1
+ l8ui a9, a3, 0 // byte 2 from s2
+ addi a2, a2, 1 // advance s1
+ bne a8, a9, .Lretdiff // if different, return difference
+ beqz a8, .Leq // bytes equal, if zero, strings are equal
+ addi a3, a3, 1 // advance s2
+ j .Laligned
+
+/* s1 and s2 have different alignment.
+
+ If the zero-overhead loop option is available, use an (almost)
+ infinite zero-overhead loop with conditional exits so we only pay
+ for taken branches when exiting the loop.
+
+ Note: It is important for this unaligned case to come before the
+ code for aligned strings, because otherwise some of the branches
+ above cannot reach and have to be transformed to branches around
+ jumps. The unaligned code is smaller and the branches can reach
+ over it. */
+
+ .align 4
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ /* (2 mod 4) alignment for loop instruction */
+#else
+ /* (1 mod 4) alignment for loop instruction */
+ .byte 0
+ .byte 0
+#endif
+#endif
+.Lunaligned:
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ _movi.n a8, 0 // set up for the maximum loop count
+#else
+ _movi a8, 0 // set up for the maximum loop count
+#endif
+ loop a8, .Lretdiff // loop forever (almost anyway)
+#endif
+.Lnextbyte:
+ l8ui a8, a2, 0
+ l8ui a9, a3, 0
+ addi a2, a2, 1
+ bne a8, a9, .Lretdiff
+ addi a3, a3, 1
+#if XCHAL_HAVE_LOOPS
+ beqz a8, .Lretdiff
+#else
+ bnez a8, .Lnextbyte
+#endif
+.Lretdiff:
+ sub a2, a8, a9
+ leaf_return
+
+/* s1 is word-aligned; s2 is word-aligned.
+
+ If the zero-overhead loop option is available, use an (almost)
+ infinite zero-overhead loop with conditional exits so we only pay
+ for taken branches when exiting the loop. */
+
+/* New algorithm, relying on the fact that all normal ASCII is between
+ 32 and 127.
+
+ Rather than check all bytes for zero:
+ Take one word (4 bytes). Call it w1.
+ Shift w1 left by one into w1'.
+ Or w1 and w1'. For all normal ASCII bit 6 will be 1; for zero it won't.
+ Check that all 4 bit 6's (one for each byte) are one:
+ If they are, we are definitely not done.
+ If they are not, we are probably done, but need to check for zero. */
+
+ .align 4
+#if XCHAL_HAVE_LOOPS
+#if !XCHAL_HAVE_L32R
+ /* (2 mod 4) alignment for loop instruction */
+ .byte 0
+ .byte 0
+#endif
+.Laligned:
+#if XCHAL_HAVE_L32R
+ l32r a4, .Lmask0 // mask for byte 0
+ l32r a7, .Lmask4
+#else
+ const16 a4, MASK0@h
+ const16 a4, MASK0@l
+ const16 a7, MASK4@h
+ const16 a7, MASK4@l
+#endif
+ /* Loop forever */
+1:
+ loop a0, .Laligned_done
+
+ /* First unrolled loop body. */
+ l32i a8, a2, 0 // get word from s1
+ l32i a9, a3, 0 // get word from s2
+ slli a5, a8, 1
+ bne a8, a9, .Lwne2
+ or a9, a8, a5
+ bnall a9, a7, .Lprobeq
+
+ /* Second unrolled loop body. */
+ l32i a8, a2, 4 // get word from s1+4
+ l32i a9, a3, 4 // get word from s2+4
+ slli a5, a8, 1
+ bne a8, a9, .Lwne2
+ or a9, a8, a5
+ bnall a9, a7, .Lprobeq2
+
+ addi a2, a2, 8 // advance s1 pointer
+ addi a3, a3, 8 // advance s2 pointer
+.Laligned_done:
+ j 1b
+
+.Lprobeq2:
+ /* Adjust pointers to account for the loop unrolling. */
+ addi a2, a2, 4
+ addi a3, a3, 4
+
+#else /* !XCHAL_HAVE_LOOPS */
+
+.Laligned:
+ movi a4, MASK0 // mask for byte 0
+ movi a7, MASK4
+ j .Lfirstword
+.Lnextword:
+ addi a2, a2, 4 // advance s1 pointer
+ addi a3, a3, 4 // advance s2 pointer
+.Lfirstword:
+ l32i a8, a2, 0 // get word from s1
+ l32i a9, a3, 0 // get word from s2
+ slli a5, a8, 1
+ bne a8, a9, .Lwne2
+ or a9, a8, a5
+ ball a9, a7, .Lnextword
+#endif /* !XCHAL_HAVE_LOOPS */
+
+ /* align (0 mod 4) */
+.Lprobeq:
+ /* Words are probably equal, but check for sure.
+ If not, loop over the rest of string using normal algorithm. */
+
+ bnone a8, a4, .Leq // if byte 0 is zero
+#if XCHAL_HAVE_L32R
+ l32r a5, .Lmask1 // mask for byte 1
+ l32r a6, .Lmask2 // mask for byte 2
+ bnone a8, a5, .Leq // if byte 1 is zero
+ l32r a7, .Lmask3 // mask for byte 3
+ bnone a8, a6, .Leq // if byte 2 is zero
+ bnone a8, a7, .Leq // if byte 3 is zero
+ /* align (1 mod 4) */
+#else
+ const16 a5, MASK1@h // mask for byte 1
+ const16 a5, MASK1@l
+ bnone a8, a5, .Leq // if byte 1 is zero
+ const16 a6, MASK2@h // mask for byte 2
+ const16 a6, MASK2@l
+ bnone a8, a6, .Leq // if byte 2 is zero
+ const16 a7, MASK3@h // mask for byte 3
+ const16 a7, MASK3@l
+ bnone a8, a7, .Leq // if byte 3 is zero
+ /* align (2 mod 4) */
+#endif /* XCHAL_HAVE_L32R */
+#if XCHAL_HAVE_DENSITY
+ addi.n a2, a2, 4 // advance s1 pointer
+ addi.n a3, a3, 4 // advance s2 pointer
+ /* align (1 mod 4) or (2 mod 4) */
+#else
+ addi a2, a2, 4 // advance s1 pointer
+ addi a3, a3, 4 // advance s2 pointer
+ or a1, a1, a1 // nop
+#if !XCHAL_HAVE_L32R
+ or a1, a1, a1 // nop
+#endif
+ /* align (2 mod 4) */
+#endif /* XCHAL_HAVE_DENSITY */
+#if XCHAL_HAVE_LOOPS
+1:
+ loop a0, .Leq // loop forever (a4 is bigger than max iters)
+ l32i a8, a2, 0 // get word from s1
+ l32i a9, a3, 0 // get word from s2
+ addi a2, a2, 4 // advance s1 pointer
+ bne a8, a9, .Lwne
+ bnone a8, a4, .Leq // if byte 0 is zero
+ bnone a8, a5, .Leq // if byte 1 is zero
+ bnone a8, a6, .Leq // if byte 2 is zero
+ bnone a8, a7, .Leq // if byte 3 is zero
+ addi a3, a3, 4 // advance s2 pointer
+ j 1b
+#else /* !XCHAL_HAVE_LOOPS */
+
+ j .Lfirstword2
+.Lnextword2:
+ addi a3, a3, 4 // advance s2 pointer
+.Lfirstword2:
+ l32i a8, a2, 0 // get word from s1
+ l32i a9, a3, 0 // get word from s2
+ addi a2, a2, 4 // advance s1 pointer
+ bne a8, a9, .Lwne
+ bnone a8, a4, .Leq // if byte 0 is zero
+ bnone a8, a5, .Leq // if byte 1 is zero
+ bnone a8, a6, .Leq // if byte 2 is zero
+ bany a8, a7, .Lnextword2 // if byte 3 is zero
+#endif /* !XCHAL_HAVE_LOOPS */
+
+ /* Words are equal; some byte is zero. */
+.Leq: movi a2, 0 // return equal
+ leaf_return
+
+.Lwne2: /* Words are not equal. On big-endian processors, if none of the
+ bytes are zero, the return value can be determined by a simple
+ comparison. */
+#ifdef __XTENSA_EB__
+ or a10, a8, a5
+ bnall a10, a7, .Lsomezero
+ bgeu a8, a9, .Lposreturn
+ movi a2, -1
+ leaf_return
+.Lposreturn:
+ movi a2, 1
+ leaf_return
+.Lsomezero: // There is probably some zero byte.
+#endif /* __XTENSA_EB__ */
+.Lwne: /* Words are not equal. */
+ xor a2, a8, a9 // get word with nonzero in byte that differs
+ bany a2, a4, .Ldiff0 // if byte 0 differs
+ movi a5, MASK1 // mask for byte 1
+ bnone a8, a4, .Leq // if byte 0 is zero
+ bany a2, a5, .Ldiff1 // if byte 1 differs
+ movi a6, MASK2 // mask for byte 2
+ bnone a8, a5, .Leq // if byte 1 is zero
+ bany a2, a6, .Ldiff2 // if byte 2 differs
+ bnone a8, a6, .Leq // if byte 2 is zero
+#ifdef __XTENSA_EB__
+.Ldiff3:
+.Ldiff2:
+.Ldiff1:
+ /* Byte 0 is equal (at least) and there is a difference before a zero
+ byte. Just subtract words to get the return value.
+ The high order equal bytes cancel, leaving room for the sign. */
+ sub a2, a8, a9
+ leaf_return
+
+.Ldiff0:
+ /* Need to make room for the sign, so can't subtract whole words. */
+ extui a10, a8, 24, 8
+ extui a11, a9, 24, 8
+ sub a2, a10, a11
+ leaf_return
+
+#else /* !__XTENSA_EB__ */
+ /* Little-endian is a little more difficult because can't subtract
+ whole words. */
+.Ldiff3:
+ /* Bytes 0-2 are equal; byte 3 is different.
+ For little-endian need to have a sign bit for the difference. */
+ extui a10, a8, 24, 8
+ extui a11, a9, 24, 8
+ sub a2, a10, a11
+ leaf_return
+
+.Ldiff0:
+ /* Byte 0 is different. */
+ extui a10, a8, 0, 8
+ extui a11, a9, 0, 8
+ sub a2, a10, a11
+ leaf_return
+
+.Ldiff1:
+ /* Byte 0 is equal; byte 1 is different. */
+ extui a10, a8, 8, 8
+ extui a11, a9, 8, 8
+ sub a2, a10, a11
+ leaf_return
+
+.Ldiff2:
+ /* Bytes 0-1 are equal; byte 2 is different. */
+ extui a10, a8, 16, 8
+ extui a11, a9, 16, 8
+ sub a2, a10, a11
+ leaf_return
+
+#endif /* !__XTENSA_EB */
+
+ .size strcmp, . - strcmp
diff --git a/newlib/libc/machine/xtensa/strcpy.S b/newlib/libc/machine/xtensa/strcpy.S
new file mode 100644
index 000000000..9ab624b73
--- /dev/null
+++ b/newlib/libc/machine/xtensa/strcpy.S
@@ -0,0 +1,274 @@
+/* ANSI C standard library function strcpy.
+
+ Copyright (c) 2001-2008 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "xtensa-asm.h"
+
+ .text
+ .begin schedule
+ .align 4
+ .literal_position
+ .global strcpy
+ .type strcpy, @function
+strcpy:
+ leaf_entry sp, 16
+ /* a2 = dst, a3 = src */
+
+ mov a10, a2 // leave dst in return value register
+ movi a4, MASK0
+ movi a5, MASK1
+ movi a6, MASK2
+ movi a7, MASK3
+ bbsi.l a3, 0, .Lsrc1mod2
+ bbsi.l a3, 1, .Lsrc2mod4
+.Lsrcaligned:
+
+ /* Check if the destination is aligned. */
+ movi a8, 3
+ bnone a10, a8, .Laligned
+
+ j .Ldstunaligned
+
+.Lsrc1mod2: // src address is odd
+ l8ui a8, a3, 0 // get byte 0
+ addi a3, a3, 1 // advance src pointer
+ s8i a8, a10, 0 // store byte 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ beqz a8, 1f // if byte 0 is zero
+ addi a10, a10, 1 // advance dst pointer
+ bbci.l a3, 1, .Lsrcaligned // if src is now word-aligned
+
+.Lsrc2mod4: // src address is 2 mod 4
+ l8ui a8, a3, 0 // get byte 0
+ /* 1-cycle interlock */
+ s8i a8, a10, 0 // store byte 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ beqz a8, 1f // if byte 0 is zero
+ l8ui a8, a3, 1 // get byte 0
+ addi a3, a3, 2 // advance src pointer
+ s8i a8, a10, 1 // store byte 0
+ addi a10, a10, 2 // advance dst pointer
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ bnez a8, .Lsrcaligned
+1: leaf_return
+
+
+/* dst is word-aligned; src is word-aligned. */
+
+ .align 4
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ /* (2 mod 4) alignment for loop instruction */
+#else
+ /* (1 mod 4) alignment for loop instruction */
+ .byte 0
+ .byte 0
+#endif
+.Laligned:
+#if XCHAL_HAVE_DENSITY
+ _movi.n a8, 0 // set up for the maximum loop count
+#else
+ _movi a8, 0 // set up for the maximum loop count
+#endif
+ loop a8, .Lz3 // loop forever (almost anyway)
+ l32i a8, a3, 0 // get word from src
+ addi a3, a3, 4 // advance src pointer
+ bnone a8, a4, .Lz0 // if byte 0 is zero
+ bnone a8, a5, .Lz1 // if byte 1 is zero
+ bnone a8, a6, .Lz2 // if byte 2 is zero
+ s32i a8, a10, 0 // store word to dst
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ l32i a8, a10, 0
+ s32i a8, a10, 0
+#endif
+ bnone a8, a7, .Lz3 // if byte 3 is zero
+ addi a10, a10, 4 // advance dst pointer
+
+#else /* !XCHAL_HAVE_LOOPS */
+
+1: addi a10, a10, 4 // advance dst pointer
+.Laligned:
+ l32i a8, a3, 0 // get word from src
+ addi a3, a3, 4 // advance src pointer
+ bnone a8, a4, .Lz0 // if byte 0 is zero
+ bnone a8, a5, .Lz1 // if byte 1 is zero
+ bnone a8, a6, .Lz2 // if byte 2 is zero
+ s32i a8, a10, 0 // store word to dst
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ l32i a8, a10, 0
+ s32i a8, a10, 0
+#endif
+
+ bany a8, a7, 1b // if byte 3 is zero
+#endif /* !XCHAL_HAVE_LOOPS */
+
+.Lz3: /* Byte 3 is zero. */
+ leaf_return
+
+.Lz0: /* Byte 0 is zero. */
+#ifdef __XTENSA_EB__
+ movi a8, 0
+#endif
+ s8i a8, a10, 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+.Lz1: /* Byte 1 is zero. */
+#ifdef __XTENSA_EB__
+ extui a8, a8, 16, 16
+#endif
+ s16i a8, a10, 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+.Lz2: /* Byte 2 is zero. */
+#ifdef __XTENSA_EB__
+ extui a8, a8, 16, 16
+#endif
+ s16i a8, a10, 0
+ movi a8, 0
+ s8i a8, a10, 2
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+#if 1
+/* For now just use byte copy loop for the unaligned destination case. */
+
+ .align 4
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ /* (2 mod 4) alignment for loop instruction */
+#else
+ /* (1 mod 4) alignment for loop instruction */
+ .byte 0
+ .byte 0
+#endif
+#endif
+.Ldstunaligned:
+
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ _movi.n a8, 0 // set up for the maximum loop count
+#else
+ _movi a8, 0 // set up for the maximum loop count
+#endif
+ loop a8, 2f // loop forever (almost anyway)
+#endif
+1: l8ui a8, a3, 0
+ addi a3, a3, 1
+ s8i a8, a10, 0
+ addi a10, a10, 1
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+#if XCHAL_HAVE_LOOPS
+ beqz a8, 2f
+#else
+ bnez a8, 1b
+#endif
+2: leaf_return
+
+#else /* 0 */
+
+/* This code is not functional yet. */
+
+.Ldstunaligned:
+ l32i a9, a2, 0 // load word from dst
+#ifdef __XTENSA_EB__
+ ssa8b a9 // rotate by dst alignment so that
+ src a9, a9, a9 // shift in loop will put back in place
+ ssa8l a9 // shift left by byte*8
+#else
+ ssa8l a9 // rotate by dst alignment so that
+ src a9, a9, a9 // shift in loop will put back in place
+ ssa8b a9 // shift left by 32-byte*8
+#endif
+
+/* dst is word-aligned; src is unaligned. */
+
+.Ldstunalignedloop:
+ l32i a8, a3, 0 // get word from src
+ /* 1-cycle interlock */
+ bnone a8, a4, .Lu0 // if byte 0 is zero
+ bnone a8, a5, .Lu1 // if byte 1 is zero
+ bnone a8, a6, .Lu2 // if byte 2 is zero
+ src a9, a8, a9 // combine last word and this word
+ s32i a9, a10, 0 // store word to dst
+ bnone a8, a7, .Lu3 // if byte 3 is nonzero, iterate
+ l32i a9, a3, 4 // get word from src
+ addi a3, a3, 8 // advance src pointer
+ bnone a9, a4, .Lu4 // if byte 0 is zero
+ bnone a9, a5, .Lu5 // if byte 1 is zero
+ bnone a9, a6, .Lu6 // if byte 2 is zero
+ src a8, a9, a8 // combine last word and this word
+ s32i a8, a10, 4 // store word to dst
+ addi a10, a10, 8 // advance dst pointer
+ bany a8, a7, .Ldstunalignedloop // if byte 3 is nonzero, iterate
+
+ /* Byte 7 is zero. */
+.Lu7: leaf_return
+
+.Lu0: /* Byte 0 is zero. */
+#ifdef __XTENSA_EB__
+ movi a8, 0
+#endif
+ s8i a8, a10, 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+.Lu1: /* Byte 1 is zero. */
+#ifdef __XTENSA_EB__
+ extui a8, a8, 16, 16
+#endif
+ s16i a8, a10, 0
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+.Lu2: /* Byte 2 is zero. */
+ s16i a8, a10, 0
+ movi a8, 0
+ s8i a8, a10, 2
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+#endif /* 0 */
+ .end schedule
+
+ .size strcpy, . - strcpy
diff --git a/newlib/libc/machine/xtensa/strlen.S b/newlib/libc/machine/xtensa/strlen.S
new file mode 100644
index 000000000..6560a3185
--- /dev/null
+++ b/newlib/libc/machine/xtensa/strlen.S
@@ -0,0 +1,115 @@
+/* ANSI C standard library function strlen.
+
+ Copyright (c) 2001-2008 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "xtensa-asm.h"
+
+ .text
+ .begin schedule
+ .align 4
+ .literal_position
+ .global strlen
+ .type strlen, @function
+strlen:
+ leaf_entry sp, 16
+ /* a2 = s */
+
+ addi a3, a2, -4 // because we overincrement at the end
+ movi a4, MASK0
+ movi a5, MASK1
+ movi a6, MASK2
+ movi a7, MASK3
+ bbsi.l a2, 0, .L1mod2
+ bbsi.l a2, 1, .L2mod4
+ j .Laligned
+
+.L1mod2: // address is odd
+ l8ui a8, a3, 4 // get byte 0
+ addi a3, a3, 1 // advance string pointer
+ beqz a8, .Lz3 // if byte 0 is zero
+ bbci.l a3, 1, .Laligned // if string pointer is now word-aligned
+
+.L2mod4: // address is 2 mod 4
+ addi a3, a3, 2 // advance ptr for aligned access
+ l32i a8, a3, 0 // get word with first two bytes of string
+ bnone a8, a6, .Lz2 // if byte 2 (of word, not string) is zero
+ bany a8, a7, .Laligned // if byte 3 (of word, not string) is nonzero
+
+ /* Byte 3 is zero. */
+ addi a3, a3, 3 // point to zero byte
+ sub a2, a3, a2 // subtract to get length
+ leaf_return
+
+
+/* String is word-aligned. */
+
+ .align 4
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ /* (2 mod 4) alignment for loop instruction */
+#else
+ /* (1 mod 4) alignment for loop instruction */
+ .byte 0
+ .byte 0
+#endif
+#endif
+.Laligned:
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ _movi.n a8, 0 // set up for the maximum loop count
+#else
+ _movi a8, 0 // set up for the maximum loop count
+#endif
+ loop a8, .Lz3 // loop forever (almost anyway)
+#endif
+1: l32i a8, a3, 4 // get next word of string
+ addi a3, a3, 4 // advance string pointer
+ bnone a8, a4, .Lz0 // if byte 0 is zero
+ bnone a8, a5, .Lz1 // if byte 1 is zero
+ bnone a8, a6, .Lz2 // if byte 2 is zero
+#if XCHAL_HAVE_LOOPS
+ bnone a8, a7, .Lz3 // if byte 3 is zero
+#else
+ bany a8, a7, 1b // repeat if byte 3 is non-zero
+#endif
+
+.Lz3: /* Byte 3 is zero. */
+ addi a3, a3, 3 // point to zero byte
+ /* Fall through.... */
+
+.Lz0: /* Byte 0 is zero. */
+ sub a2, a3, a2 // subtract to get length
+ leaf_return
+
+.Lz1: /* Byte 1 is zero. */
+ addi a3, a3, 1 // point to zero byte
+ sub a2, a3, a2 // subtract to get length
+ leaf_return
+
+.Lz2: /* Byte 2 is zero. */
+ addi a3, a3, 2 // point to zero byte
+ sub a2, a3, a2 // subtract to get length
+ leaf_return
+
+ .end schedule
+
+ .size strlen, . - strlen
diff --git a/newlib/libc/machine/xtensa/strncpy.S b/newlib/libc/machine/xtensa/strncpy.S
new file mode 100644
index 000000000..faa7c7b25
--- /dev/null
+++ b/newlib/libc/machine/xtensa/strncpy.S
@@ -0,0 +1,274 @@
+/* ANSI C standard library function strncpy.
+
+ Copyright (c) 2001-2008 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#include "xtensa-asm.h"
+
+ .text
+.begin schedule
+ .align 4
+ .literal_position
+__strncpy_aux:
+
+.Lsrc1mod2: // src address is odd
+ l8ui a8, a3, 0 // get byte 0
+ addi a3, a3, 1 // advance src pointer
+ s8i a8, a10, 0 // store byte 0
+ addi a4, a4, -1 // decrement n
+ beqz a4, .Lret // if n is zero
+ addi a10, a10, 1 // advance dst pointer
+ beqz a8, .Lfill // if byte 0 is zero
+ bbci.l a3, 1, .Lsrcaligned // if src is now word-aligned
+
+.Lsrc2mod4: // src address is 2 mod 4
+ l8ui a8, a3, 0 // get byte 0
+ addi a4, a4, -1 // decrement n
+ s8i a8, a10, 0 // store byte 0
+ beqz a4, .Lret // if n is zero
+ addi a10, a10, 1 // advance dst pointer
+ beqz a8, .Lfill // if byte 0 is zero
+ l8ui a8, a3, 1 // get byte 0
+ addi a3, a3, 2 // advance src pointer
+ s8i a8, a10, 0 // store byte 0
+ addi a4, a4, -1 // decrement n
+ beqz a4, .Lret // if n is zero
+ addi a10, a10, 1 // advance dst pointer
+ bnez a8, .Lsrcaligned
+ j .Lfill
+
+.Lret:
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+
+ .align 4
+ .global strncpy
+ .type strncpy, @function
+strncpy:
+ leaf_entry sp, 16
+ /* a2 = dst, a3 = src */
+
+ mov a10, a2 // leave dst in return value register
+ beqz a4, .Lret // if n is zero
+
+ movi a11, MASK0
+ movi a5, MASK1
+ movi a6, MASK2
+ movi a7, MASK3
+ bbsi.l a3, 0, .Lsrc1mod2
+ bbsi.l a3, 1, .Lsrc2mod4
+.Lsrcaligned:
+
+ /* Check if the destination is aligned. */
+ movi a8, 3
+ bnone a10, a8, .Laligned
+
+ j .Ldstunaligned
+
+
+/* Fill the dst with zeros -- n is at least 1. */
+
+.Lfill:
+ movi a9, 0
+ bbsi.l a10, 0, .Lfill1mod2
+ bbsi.l a10, 1, .Lfill2mod4
+.Lfillaligned:
+ blti a4, 4, .Lfillcleanup
+
+ /* Loop filling complete words with zero. */
+#if XCHAL_HAVE_LOOPS
+
+ srai a8, a4, 2
+ loop a8, 1f
+ s32i a9, a10, 0
+ addi a10, a10, 4
+
+1: slli a8, a8, 2
+ sub a4, a4, a8
+
+#else /* !XCHAL_HAVE_LOOPS */
+
+1: s32i a9, a10, 0
+ addi a10, a10, 4
+ addi a4, a4, -4
+ bgei a4, 4, 1b
+
+#endif /* !XCHAL_HAVE_LOOPS */
+
+ beqz a4, 2f
+
+.Lfillcleanup:
+ /* Fill leftover (1 to 3) bytes with zero. */
+ s8i a9, a10, 0 // store byte 0
+ addi a4, a4, -1 // decrement n
+ addi a10, a10, 1
+ bnez a4, .Lfillcleanup
+
+2:
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+
+.Lfill1mod2: // dst address is odd
+ s8i a9, a10, 0 // store byte 0
+ addi a4, a4, -1 // decrement n
+ beqz a4, 2b // if n is zero
+ addi a10, a10, 1 // advance dst pointer
+ bbci.l a10, 1, .Lfillaligned // if dst is now word-aligned
+
+.Lfill2mod4: // dst address is 2 mod 4
+ s8i a9, a10, 0 // store byte 0
+ addi a4, a4, -1 // decrement n
+ beqz a4, 2b // if n is zero
+ s8i a9, a10, 1 // store byte 1
+ addi a4, a4, -1 // decrement n
+ beqz a4, 2b // if n is zero
+ addi a10, a10, 2 // advance dst pointer
+ j .Lfillaligned
+
+
+/* dst is word-aligned; src is word-aligned; n is at least 1. */
+
+ .align 4
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ /* (2 mod 4) alignment for loop instruction */
+#else
+ /* (1 mod 4) alignment for loop instruction */
+ .byte 0
+ .byte 0
+#endif
+#endif
+.Laligned:
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ _movi.n a8, 0 // set up for the maximum loop count
+#else
+ _movi a8, 0 // set up for the maximum loop count
+#endif
+ loop a8, 1f // loop forever (almost anyway)
+ blti a4, 5, .Ldstunaligned // n is near limit; do one at a time
+ l32i a8, a3, 0 // get word from src
+ addi a3, a3, 4 // advance src pointer
+ bnone a8, a11, .Lz0 // if byte 0 is zero
+ bnone a8, a5, .Lz1 // if byte 1 is zero
+ bnone a8, a6, .Lz2 // if byte 2 is zero
+ s32i a8, a10, 0 // store word to dst
+ addi a4, a4, -4 // decrement n
+ addi a10, a10, 4 // advance dst pointer
+ bnone a8, a7, .Lfill // if byte 3 is zero
+1:
+
+#else /* !XCHAL_HAVE_LOOPS */
+
+1: blti a4, 5, .Ldstunaligned // n is near limit; do one at a time
+ l32i a8, a3, 0 // get word from src
+ addi a3, a3, 4 // advance src pointer
+ bnone a8, a11, .Lz0 // if byte 0 is zero
+ bnone a8, a5, .Lz1 // if byte 1 is zero
+ bnone a8, a6, .Lz2 // if byte 2 is zero
+ s32i a8, a10, 0 // store word to dst
+ addi a4, a4, -4 // decrement n
+ addi a10, a10, 4 // advance dst pointer
+ bany a8, a7, 1b // no zeroes
+#endif /* !XCHAL_HAVE_LOOPS */
+
+ j .Lfill
+
+.Lz0: /* Byte 0 is zero. */
+#ifdef __XTENSA_EB__
+ movi a8, 0
+#endif
+ s8i a8, a10, 0
+ addi a4, a4, -1 // decrement n
+ addi a10, a10, 1 // advance dst pointer
+ j .Lfill
+
+.Lz1: /* Byte 1 is zero. */
+#ifdef __XTENSA_EB__
+ extui a8, a8, 16, 16
+#endif
+ s16i a8, a10, 0
+ addi a4, a4, -2 // decrement n
+ addi a10, a10, 2 // advance dst pointer
+ j .Lfill
+
+.Lz2: /* Byte 2 is zero. */
+#ifdef __XTENSA_EB__
+ extui a8, a8, 16, 16
+#endif
+ s16i a8, a10, 0
+ movi a8, 0
+ s8i a8, a10, 2
+ addi a4, a4, -3 // decrement n
+ addi a10, a10, 3 // advance dst pointer
+ j .Lfill
+
+ .align 4
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ /* (2 mod 4) alignment for loop instruction */
+#else
+ /* (1 mod 4) alignment for loop instruction */
+ .byte 0
+ .byte 0
+#endif
+#endif
+.Ldstunaligned:
+
+#if XCHAL_HAVE_LOOPS
+#if XCHAL_HAVE_DENSITY
+ _movi.n a8, 0 // set up for the maximum loop count
+#else
+ _movi a8, 0 // set up for the maximum loop count
+#endif
+ loop a8, 2f // loop forever (almost anyway)
+#endif
+1: l8ui a8, a3, 0
+ addi a3, a3, 1
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ nop
+ nop
+ nop
+#endif
+ s8i a8, a10, 0
+ addi a4, a4, -1
+ beqz a4, 3f
+ addi a10, a10, 1
+#if XCHAL_HAVE_LOOPS
+ beqz a8, 2f
+#else
+ bnez a8, 1b
+#endif
+2: j .Lfill
+
+3:
+#if XTENSA_ESP32_PSRAM_CACHE_FIX
+ memw
+#endif
+ leaf_return
+.end schedule
+
+ .size strncpy, . - strncpy
diff --git a/newlib/libc/machine/xtensa/xtensa-asm.h b/newlib/libc/machine/xtensa/xtensa-asm.h
new file mode 100644
index 000000000..926f3e499
--- /dev/null
+++ b/newlib/libc/machine/xtensa/xtensa-asm.h
@@ -0,0 +1,72 @@
+/* Copyright (c) 2006 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+/* Define macros for leaf function entry and return, supporting either the
+ * standard register windowed ABI or the non-windowed call0 ABI. These
+ * macros do not allocate any extra stack space, so they only work for
+ * leaf functions that do not need to spill anything to the stack. */
+
+#include <xtensa/config/core-isa.h>
+
+ .macro leaf_entry reg, size
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+ entry \reg, \size
+#else
+ /* do nothing */
+#endif
+ .endm
+
+ .macro leaf_return
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+ retw
+#else
+ ret
+#endif
+ .endm
+
+ .macro src_b r, w0, w1
+#ifdef __XTENSA_EB__
+ src \r, \w0, \w1
+#else
+ src \r, \w1, \w0
+#endif
+ .endm
+
+ .macro ssa8 r
+#ifdef __XTENSA_EB__
+ ssa8b \r
+#else
+ ssa8l \r
+#endif
+ .endm
+
+#if XCHAL_HAVE_BE
+#define MASK0 0xff000000
+#define MASK1 0x00ff0000
+#define MASK2 0x0000ff00
+#define MASK3 0x000000ff
+#else
+#define MASK0 0x000000ff
+#define MASK1 0x0000ff00
+#define MASK2 0x00ff0000
+#define MASK3 0xff000000
+#endif
+
diff --git a/newlib/libc/machine/xtensa/xtensa.tex b/newlib/libc/machine/xtensa/xtensa.tex
new file mode 100644
index 000000000..1a5bf65e7
--- /dev/null
+++ b/newlib/libc/machine/xtensa/xtensa.tex
@@ -0,0 +1,72 @@
+@node Xtensa
+@chapter Functions for Xtensa Processors
+
+This chapter describes machine-dependent functions that are included
+in the C library when it is built for Xtensa processors.
+
+@menu
+* setjmp:: Save stack environment
+* longjmp:: Non-local goto
+@end menu
+
+@page
+@node setjmp
+@section @code{setjmp}---save stack environment
+@findex setjmp
+@strong{Synopsis}
+@example
+#include <setjmp.h>
+int setjmp(jmp_buf env);
+
+@end example
+@strong{Description}@*
+@code{setjmp} and @code{longjmp} are useful for dealing with errors
+and interrupts encountered in a low-level subroutine of a program.
+@code{setjmp} saves the stack context/environment in @code{env} for
+later use by @code{longjmp}. The stack context will be invalidated if
+the function which called @code{setjmp} returns.
+
+@*
+@strong{Returns}@*
+@code{setjmp} returns 0 if returning directly, and non-zero when
+returning from @code{longjmp} using the saved context.
+
+@*
+@strong{Portability}@*
+@code{setjmp} is ANSI C and POSIX.1.
+
+setjmp requires no supporting OS subroutines.
+
+@*
+@page
+@node longjmp
+@section @code{longjmp}---non-local goto
+@findex longjmp
+@strong{Synopsis}
+@example
+#include <setjmp.h>
+void longjmp(jmp_buf env, int val);
+
+@end example
+@strong{Description}@*
+@code{longjmp} and @code{setjmp} are useful for dealing with errors
+and interrupts encountered in a low-level subroutine of a program.
+@code{longjmp} restores the environment saved by the last call of
+@code{setjmp} with the corresponding @code{env} argument. After
+@code{longjmp} is completed, program execution continues as if the
+corresponding call of @code{setjmp} had just returned the value
+@code{val}. @code{longjmp} cannot cause 0 to be returned. If
+@code{longjmp} is invoked with a second argument of 0, 1 will be
+returned instead.
+
+@*
+@strong{Returns}@*
+This function never returns.
+
+@*
+@strong{Portability}@*
+@code{longjmp} is ANSI C and POSIX.1.
+
+longjmp requires no supporting OS subroutines.
+
+@*
diff --git a/newlib/libc/sys/Makefile.inc b/newlib/libc/sys/Makefile.inc
index 9f8758934..24d8407d5 100644
--- a/newlib/libc/sys/Makefile.inc
+++ b/newlib/libc/sys/Makefile.inc
@@ -64,6 +64,9 @@ endif
if HAVE_LIBC_SYS_W65_DIR
include %D%/w65/Makefile.inc
endif
+if HAVE_LIBC_SYS_XTENSA_DIR
+include %D%/xtensa/Makefile.inc
+endif
if HAVE_LIBC_SYS_Z8KSIM_DIR
include %D%/z8ksim/Makefile.inc
endif
diff --git a/newlib/libc/sys/xtensa/Makefile.inc b/newlib/libc/sys/xtensa/Makefile.inc
new file mode 100644
index 000000000..ddee58ae1
--- /dev/null
+++ b/newlib/libc/sys/xtensa/Makefile.inc
@@ -0,0 +1 @@
+libc_a_SOURCES += %D%/creat.c %D%/isatty.c %D%/clibrary_init.c
diff --git a/newlib/libc/sys/xtensa/clibrary_init.c b/newlib/libc/sys/xtensa/clibrary_init.c
new file mode 100644
index 000000000..24d4cf94c
--- /dev/null
+++ b/newlib/libc/sys/xtensa/clibrary_init.c
@@ -0,0 +1,42 @@
+/* Copyright (c) 2003-2006 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TENSILICA
+ INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <stdlib.h>
+#include <unistd.h>
+
+const char * __progname = 0;
+
+void
+__clibrary_init (int argc, char **argv, char **envp,
+ void (*init)(void),
+ void (*fini)(void))
+{
+ if (argv != 0)
+ __progname = *argv;
+ environ = envp;
+ if (init)
+ init ();
+ if (fini)
+ atexit (fini);
+}
diff --git a/newlib/libc/sys/xtensa/creat.c b/newlib/libc/sys/xtensa/creat.c
new file mode 100644
index 000000000..21e6a1874
--- /dev/null
+++ b/newlib/libc/sys/xtensa/creat.c
@@ -0,0 +1,9 @@
+/* creat() "system call" (copied from libc/posix/creat.c) */
+
+#include <fcntl.h>
+
+int
+creat (const char *path, mode_t mode)
+{
+ return open (path, O_WRONLY | O_CREAT | O_TRUNC, mode);
+}
diff --git a/newlib/libc/sys/xtensa/crt0.c b/newlib/libc/sys/xtensa/crt0.c
new file mode 100644
index 000000000..11725dca5
--- /dev/null
+++ b/newlib/libc/sys/xtensa/crt0.c
@@ -0,0 +1,16 @@
+/* Dummy crt0 code. */
+
+/* Copyright (c) 2003 by Tensilica Inc. ALL RIGHTS RESERVED.
+ These coded instructions, statements, and computer programs are the
+ copyrighted works and confidential proprietary information of Tensilica Inc.
+ They may not be modified, copied, reproduced, distributed, or disclosed to
+ third parties in any manner, medium, or form, in whole or in part, without
+ the prior written consent of Tensilica Inc. */
+
+/* Xtensa systems normally use a crt1 file associated with a particular
+ linker support package (LSP). There is no need for this crt0 file,
+ except that the newlib makefiles require it to exist if there is a
+ sys/xtensa directory. The directory exists only to hold the header
+ files for the Xtensa ISS semihosting "platform". */
+
+void crt0_unused (void) {}
diff --git a/newlib/libc/sys/xtensa/include/fenv.h b/newlib/libc/sys/xtensa/include/fenv.h
new file mode 100644
index 000000000..2fa76f758
--- /dev/null
+++ b/newlib/libc/sys/xtensa/include/fenv.h
@@ -0,0 +1,88 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+
+#ifndef _FENV_H
+#define _FENV_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef unsigned long fenv_t;
+typedef unsigned long fexcept_t;
+
+#define FE_DIVBYZERO 0x08
+#define FE_INEXACT 0x01
+#define FE_INVALID 0x10
+#define FE_OVERFLOW 0x04
+#define FE_UNDERFLOW 0x02
+
+#define FE_ALL_EXCEPT \
+ (FE_DIVBYZERO | \
+ FE_INEXACT | \
+ FE_INVALID | \
+ FE_OVERFLOW | \
+ FE_UNDERFLOW)
+
+#define FE_DOWNWARD 0x3
+#define FE_TONEAREST 0x0
+#define FE_TOWARDZERO 0x1
+#define FE_UPWARD 0x2
+
+#define FE_DFL_ENV ((const fenv_t *) 0)
+
+int feclearexcept(int);
+int fegetexceptflag(fexcept_t *, int);
+int feraiseexcept(int);
+int fesetexceptflag(const fexcept_t *, int);
+int fetestexcept(int);
+int fegetround(void);
+int fesetround(int);
+int fegetenv(fenv_t *);
+int feholdexcept(fenv_t *);
+int fesetenv(const fenv_t *);
+int feupdateenv(const fenv_t *);
+
+/* glibc extensions */
+int feenableexcept(int excepts);
+int fedisableexcept(int excepts);
+int fegetexcept(void);
+
+#define _FE_EXCEPTION_FLAGS_OFFSET 7
+#define _FE_EXCEPTION_FLAG_MASK (FE_ALL_EXCEPT << _FE_EXCEPTION_FLAGS_OFFSET)
+#define _FE_EXCEPTION_ENABLE_OFFSET 2
+#define _FE_EXCEPTION_ENABLE_MASK (FE_ALL_EXCEPT << _FE_EXCEPTION_ENABLE_OFFSET)
+#define _FE_ROUND_MODE_OFFSET 0
+#define _FE_ROUND_MODE_MASK (0x3 << _FE_ROUND_MODE_OFFSET)
+#define _FE_FLOATING_ENV_MASK (_FE_EXCEPTION_FLAG_MASK | _FE_EXCEPTION_ENABLE_MASK | _FE_ROUND_MODE_MASK)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/newlib/libc/sys/xtensa/include/unistd.h b/newlib/libc/sys/xtensa/include/unistd.h
new file mode 100644
index 000000000..4f6fd29a4
--- /dev/null
+++ b/newlib/libc/sys/xtensa/include/unistd.h
@@ -0,0 +1,13 @@
+#ifndef _UNISTD_H_
+#define _UNISTD_H_
+
+# include <sys/unistd.h>
+
+#ifndef L_SET
+/* Old BSD names for the same constants; just for compatibility. */
+#define L_SET SEEK_SET
+#define L_INCR SEEK_CUR
+#define L_XTND SEEK_END
+#endif
+
+#endif /* _UNISTD_H_ */
diff --git a/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h b/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h
new file mode 100644
index 000000000..4d8e3f9b9
--- /dev/null
+++ b/newlib/libc/sys/xtensa/include/xtensa/config/core-isa.h
@@ -0,0 +1,115 @@
+/*
+ * xtensa/config/core-isa.h -- minimum required HAL definitions that are
+ * dependent on Xtensa processor CORE configuration
+ *
+ * See <xtensa/config/core.h>, which includes this file, for more details.
+ */
+
+/* Xtensa processor core configuration information.
+
+ Copyright (c) 1999-2023 Tensilica Inc.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice shall be included
+ in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+#if defined(_LIBC) || defined(_LIBGLOSS)
+
+/* Macros used to build newlib and libgloss */
+
+#undef XCHAL_HAVE_BE
+#ifdef __XCHAL_HAVE_BE
+#define XCHAL_HAVE_BE __XCHAL_HAVE_BE
+#else
+#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
+#endif
+
+#undef XCHAL_HAVE_WINDOWED
+#ifdef __XCHAL_HAVE_WINDOWED
+#define XCHAL_HAVE_WINDOWED __XCHAL_HAVE_WINDOWED
+#else
+#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
+#endif
+
+#undef XCHAL_NUM_AREGS
+#ifdef __XCHAL_NUM_AREGS
+#define XCHAL_NUM_AREGS __XCHAL_NUM_AREGS
+#else
+#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
+#endif
+
+#undef XCHAL_HAVE_DENSITY
+#ifdef __XCHAL_HAVE_DENSITY
+#define XCHAL_HAVE_DENSITY __XCHAL_HAVE_DENSITY
+#else
+#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
+#endif
+
+#undef XCHAL_HAVE_LOOPS
+#ifdef __XCHAL_HAVE_LOOPS
+#define XCHAL_HAVE_LOOPS __XCHAL_HAVE_LOOPS
+#else
+#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
+#endif
+
+#undef XCHAL_HAVE_L32R
+#ifdef __XCHAL_HAVE_L32R
+#define XCHAL_HAVE_L32R __XCHAL_HAVE_L32R
+#else
+#define XCHAL_HAVE_L32R 1 /* L32R instruction */
+#endif
+
+#undef XCHAL_HAVE_FP
+#ifdef __XCHAL_HAVE_FP
+#define XCHAL_HAVE_FP __XCHAL_HAVE_FP
+#else
+#define XCHAL_HAVE_FP 1 /* single prec floating point */
+#endif
+
+#undef XCHAL_HAVE_FP_SQRT
+#ifdef __XCHAL_HAVE_FP_SQRT
+#define XCHAL_HAVE_FP_SQRT __XCHAL_HAVE_FP_SQRT
+#else
+#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
+#endif
+
+#undef XCHAL_HAVE_DFP
+#ifdef __XCHAL_HAVE_DFP
+#define XCHAL_HAVE_DFP __XCHAL_HAVE_DFP
+#else
+#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
+#endif
+
+#undef XCHAL_INST_FETCH_WIDTH
+#ifdef __XCHAL_INST_FETCH_WIDTH
+#define XCHAL_INST_FETCH_WIDTH __XCHAL_INST_FETCH_WIDTH
+#else
+#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
+#endif
+
+#else /* defined(_LIBC) || defined(_LIBGLOSS) */
+
+/* Expect that core-isa.h exists in OS/baremetal port */
+#include_next <xtensa/config/core-isa.h>
+
+#endif /* defined(_LIBC) || defined(_LIBGLOSS) */
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
diff --git a/newlib/libc/sys/xtensa/isatty.c b/newlib/libc/sys/xtensa/isatty.c
new file mode 100644
index 000000000..fe64209b9
--- /dev/null
+++ b/newlib/libc/sys/xtensa/isatty.c
@@ -0,0 +1,18 @@
+/* isatty.c */
+
+/* Dumb implementation so programs will at least run. */
+
+#include <sys/stat.h>
+#include <reent.h>
+
+int
+_isatty_r (struct _reent *ptr, int fd)
+{
+ struct stat buf;
+
+ if (_fstat_r (ptr, fd, &buf) < 0)
+ return 0;
+ if (S_ISCHR (buf.st_mode))
+ return 1;
+ return 0;
+}
diff --git a/newlib/libc/sys/xtensa/sys/file.h b/newlib/libc/sys/xtensa/sys/file.h
new file mode 100644
index 000000000..48a2ca06d
--- /dev/null
+++ b/newlib/libc/sys/xtensa/sys/file.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2005-2006 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TENSILICA
+ INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <sys/fcntl.h>
+
+/* Alternate names for values for the WHENCE argument to `lseek'.
+ These are the same as SEEK_SET, SEEK_CUR, and SEEK_END, respectively. */
+#ifndef L_SET
+#define L_SET 0 /* Seek from beginning of file. */
+#define L_INCR 1 /* Seek from current position. */
+#define L_XTND 2 /* Seek from end of file. */
+#endif
diff --git a/newlib/libm/acinclude.m4 b/newlib/libm/acinclude.m4
index f7f9f534f..5fc137f27 100644
--- a/newlib/libm/acinclude.m4
+++ b/newlib/libm/acinclude.m4
@@ -4,7 +4,7 @@ m4_include([libm/machine/nds32/acinclude.m4])
dnl Define HAVE_LIBM_MACHINE_<machine> automake conditionals.
m4_foreach_w([MACHINE], [
- aarch64 amdgcn arm i386 mips nds32 powerpc pru sparc spu riscv x86_64
+ aarch64 amdgcn arm i386 mips nds32 powerpc pru sparc spu riscv x86_64 xtensa
], [dnl
AM_CONDITIONAL([HAVE_LIBM_MACHINE_]m4_toupper(MACHINE), test "${libm_machine_dir}" = "MACHINE")
])
diff --git a/newlib/libm/machine/xtensa/Makefile.inc b/newlib/libm/machine/xtensa/Makefile.inc
new file mode 100644
index 000000000..22e13761d
--- /dev/null
+++ b/newlib/libm/machine/xtensa/Makefile.inc
@@ -0,0 +1,6 @@
+%C%_src = \
+ %D%/feclearexcept.c %D%/fegetenv.c %D/fegetexcept.c %D%/fegetexceptflag.c \
+ %D%/fegetround.c %D%/feholdexcept.c %D%/feraiseexcept.c \
+ %D%/fesetexceptflag.c %D%/fetestexcept.c %D%/feupdateenv.c
+
+libm_a_SOURCES += $(%C%_src)
diff --git a/newlib/libm/machine/xtensa/feclearexcept.c b/newlib/libm/machine/xtensa/feclearexcept.c
new file mode 100644
index 000000000..f1bd84f96
--- /dev/null
+++ b/newlib/libm/machine/xtensa/feclearexcept.c
@@ -0,0 +1,48 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+
+int feclearexcept(int except)
+{
+ unsigned int fsr;
+
+ if (except & ~FE_ALL_EXCEPT)
+ return -1;
+ except <<= _FE_EXCEPTION_FLAGS_OFFSET;
+ asm ("rur.fsr %0" : "=a"(fsr));
+ fsr = fsr & ~except;
+ asm ("wur.fsr %0" : : "a"(fsr));
+ return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fegetenv.c b/newlib/libm/machine/xtensa/fegetenv.c
new file mode 100644
index 000000000..b3984ee84
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fegetenv.c
@@ -0,0 +1,55 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int fegetenv(fenv_t * env_ptr)
+{
+ unsigned int fsr;
+ unsigned int fcr;
+ asm ("rur.fsr %0" : "=a"(fsr));
+ asm ("rur.fcr %0" : "=a"(fcr));
+ *env_ptr = fsr | fcr;
+ return 0;
+}
+
+
+int fesetenv(const fenv_t * env_ptr)
+{
+ fenv_t env = *env_ptr;
+ if (env & ~(_FE_FLOATING_ENV_MASK))
+ return -1;
+ asm ("wur.fsr %0" : : "a"(*env_ptr));
+ asm ("wur.fcr %0" : : "a"(*env_ptr));
+ return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fegetexcept.c b/newlib/libm/machine/xtensa/fegetexcept.c
new file mode 100644
index 000000000..250917c3e
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fegetexcept.c
@@ -0,0 +1,67 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+/* These functions are glibc extensions. */
+
+#include <fenv.h>
+
+int fegetexcept(void)
+{
+ fexcept_t current;
+ asm ("rur.fsr %0" : "=a"(current));
+ return (current >> _FE_EXCEPTION_ENABLE_OFFSET) & FE_ALL_EXCEPT;
+}
+
+
+int feenableexcept(int excepts)
+{
+ fexcept_t current;
+ if (excepts & ~FE_ALL_EXCEPT)
+ return -1;
+ asm ("rur.fcr %0" : "=a"(current));
+ current |= excepts << _FE_EXCEPTION_ENABLE_OFFSET;
+ asm ("wur.fcr %0" : "=a"(current));
+ return 0;
+}
+
+
+int fedisableexcept(int excepts)
+{
+ fexcept_t current;
+ if (excepts & ~FE_ALL_EXCEPT)
+ return -1;
+ asm ("rur.fcr %0" : "=a"(current));
+ current &= ~(excepts << _FE_EXCEPTION_ENABLE_OFFSET);
+ asm ("wur.fcr %0" : "=a"(current));
+ return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fegetexceptflag.c b/newlib/libm/machine/xtensa/fegetexceptflag.c
new file mode 100644
index 000000000..6d9e7e6ac
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fegetexceptflag.c
@@ -0,0 +1,63 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int fegetexceptflag(fexcept_t *flagp, int excepts)
+{
+ unsigned int fsr;
+ if (excepts & ~FE_ALL_EXCEPT)
+ return -1;
+ asm ("rur.fsr %0" : "=a"(fsr));
+ fsr >>= _FE_EXCEPTION_FLAGS_OFFSET;
+ excepts &= fsr;
+ *flagp = excepts;
+
+ return 0;
+}
+
+
+int fesetexceptflag(const fexcept_t *flagp, int excepts)
+{
+ if (excepts & ~FE_ALL_EXCEPT)
+ return -1;
+
+ unsigned int fsr;
+
+ asm ("rur.fsr %0" : "=a"(fsr));
+
+ fsr &= ~(excepts << _FE_EXCEPTION_FLAGS_OFFSET);
+ fsr |= ((*flagp & excepts) << _FE_EXCEPTION_FLAGS_OFFSET);
+ asm ("wur.fsr %0" : : "a"(fsr));
+ return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fegetround.c b/newlib/libm/machine/xtensa/fegetround.c
new file mode 100644
index 000000000..f17be6dc1
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fegetround.c
@@ -0,0 +1,50 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int fegetround(void)
+{
+ fexcept_t current;
+ asm ("rur.fcr %0" : "=a"(current));
+ return (current & _FE_ROUND_MODE_MASK) >> _FE_ROUND_MODE_OFFSET;
+}
+
+
+int fesetround(int round)
+{
+ if (round & ~_FE_ROUND_MODE_MASK)
+ return -1;
+ asm ("wur.fcr %0" : : "a"(round));
+ return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/feholdexcept.c b/newlib/libm/machine/xtensa/feholdexcept.c
new file mode 100644
index 000000000..32e5e0b3b
--- /dev/null
+++ b/newlib/libm/machine/xtensa/feholdexcept.c
@@ -0,0 +1,54 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int feholdexcept(fenv_t * envp)
+{
+ fexcept_t fsr;
+ fenv_t fcr;
+ /* Get the environment. */
+ asm ("rur.fcr %0" : "=a"(fcr));
+ asm ("rur.fsr %0" : "=a"(fsr));
+ *envp = fsr | fcr;
+
+ /* Clear the exception enable flags. */
+ fcr &= _FE_ROUND_MODE_MASK;
+ asm ("wur.fcr %0" : :"a"(fcr));
+
+ /* Clear the exception happened flags. */
+ fsr = 0;
+ asm ("wur.fsr %0" : :"a"(fsr));
+
+ return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/feraiseexcept.c b/newlib/libm/machine/xtensa/feraiseexcept.c
new file mode 100644
index 000000000..8d418f0fe
--- /dev/null
+++ b/newlib/libm/machine/xtensa/feraiseexcept.c
@@ -0,0 +1,49 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+/* Xtensa doesn't trap, so setting the flags is the best we can
+ do. */
+
+#include <fenv.h>
+
+int feraiseexcept(int excepts)
+{
+ fexcept_t current;
+
+ if (excepts & ~FE_ALL_EXCEPT)
+ return -1;
+ asm ("rur.fsr %0" : "=a"(current));
+ current |= excepts << _FE_EXCEPTION_FLAGS_OFFSET;
+ asm ("wur.fsr %0" : : "a"(current));
+ return 0;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/fetestexcept.c b/newlib/libm/machine/xtensa/fetestexcept.c
new file mode 100644
index 000000000..295085949
--- /dev/null
+++ b/newlib/libm/machine/xtensa/fetestexcept.c
@@ -0,0 +1,41 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int fetestexcept(int excepts)
+{
+ fexcept_t current;
+ asm ("rur.fsr %0" : "=a"(current));
+ return (current >> _FE_EXCEPTION_FLAGS_OFFSET) & excepts;
+}
+
+#endif
diff --git a/newlib/libm/machine/xtensa/feupdateenv.c b/newlib/libm/machine/xtensa/feupdateenv.c
new file mode 100644
index 000000000..cbb1ffa43
--- /dev/null
+++ b/newlib/libm/machine/xtensa/feupdateenv.c
@@ -0,0 +1,46 @@
+/* Copyright (c) 2011 Tensilica Inc. ALL RIGHTS RESERVED.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above
+ copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided
+ with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ TENSILICA INCORPORATED BE LIABLE FOR ANY DIRECT, INDIRECT,
+ INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#include <xtensa/config/core-isa.h>
+
+#if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+
+#include <fenv.h>
+
+int feupdateenv(const fenv_t * envp)
+{
+ fenv_t current;
+ int err = fegetenv (¤t);
+ if (err != 0)
+ return err;
+ err = fesetenv (envp);
+ if (err != 0)
+ return err;
+ return feraiseexcept (current);
+}
+
+#endif
diff --git a/newlib/libm/math/ef_sqrt.c b/newlib/libm/math/ef_sqrt.c
index 448e26e57..dfbd98e8c 100644
--- a/newlib/libm/math/ef_sqrt.c
+++ b/newlib/libm/math/ef_sqrt.c
@@ -12,6 +12,11 @@
* is preserved.
* ====================================================
*/
+#ifdef __XTENSA__
+#include <xtensa/config/core-isa.h>
+#endif
+
+#if !XCHAL_HAVE_FP_SQRT
#include "fdlibm.h"
@@ -87,3 +92,5 @@ static float volatile one = 1.0, tiny=1.0e-30;
SET_FLOAT_WORD(z,ix);
return z;
}
+
+#endif /* !XCHAL_HAVE_FP_SQRT */
--
2.34.1
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #3: 0003-libgloss-add-Xtensa-port.patch --]
[-- Type: text/x-patch; name="0003-libgloss-add-Xtensa-port.patch", Size: 117490 bytes --]
From a3b19729eb1b51007d945aedaa1b4bfe18c19063 Mon Sep 17 00:00:00 2001
From: Alexey Lapshin <alexey.lapshin@espressif.com>
Date: Wed, 9 Aug 2023 00:07:04 +0400
Subject: [PATCH 3/3] libgloss: add Xtensa port
Supported esp32 and esp32s2 boards:
https://github.com/espressif/esp-toolchain-docs/blob/main/gcc/build-and-run-native-app.md
---
libgloss/Makefile.am | 3 +
libgloss/Makefile.in | 292 +++++++++++++++++-
libgloss/configure | 64 ++++
libgloss/configure.ac | 6 +-
libgloss/libnosys/acinclude.m4 | 1 +
libgloss/xtensa/Makefile.inc | 55 ++++
libgloss/xtensa/acinclude.m4 | 5 +
libgloss/xtensa/app.elf.ld | 190 ++++++++++++
libgloss/xtensa/board.elf.specs | 5 +
libgloss/xtensa/boards/esp32/board.c | 19 ++
.../xtensa/boards/esp32/include/soc/cpu.h | 11 +
.../xtensa/boards/esp32/include/soc/uart.h | 19 ++
libgloss/xtensa/boards/esp32/memory.elf.ld | 26 ++
libgloss/xtensa/boards/esp32s3/board.c | 19 ++
.../xtensa/boards/esp32s3/include/soc/cpu.h | 11 +
.../xtensa/boards/esp32s3/include/soc/uart.h | 19 ++
libgloss/xtensa/boards/esp32s3/memory.elf.ld | 21 ++
libgloss/xtensa/crt0.S | 14 +
libgloss/xtensa/crt1-boards.S | 226 ++++++++++++++
libgloss/xtensa/crt1-sim.S | 204 ++++++++++++
libgloss/xtensa/default.specs | 2 +
libgloss/xtensa/include/register_access.h | 7 +
libgloss/xtensa/include/syscalls.h | 59 ++++
libgloss/xtensa/include/xtensa/corebits.h | 186 +++++++++++
libgloss/xtensa/nano.specs | 18 ++
libgloss/xtensa/sim-call.S | 8 +
libgloss/xtensa/sim-vectors.S | 163 ++++++++++
libgloss/xtensa/sim.elf.specs | 5 +
libgloss/xtensa/sleep.S | 64 ++++
libgloss/xtensa/sys.openocd.specs | 8 +
libgloss/xtensa/sys.qemu.specs | 8 +
libgloss/xtensa/syscalls.c | 210 +++++++++++++
libgloss/xtensa/window-vectors.S | 252 +++++++++++++++
33 files changed, 2190 insertions(+), 10 deletions(-)
create mode 100644 libgloss/xtensa/Makefile.inc
create mode 100644 libgloss/xtensa/acinclude.m4
create mode 100644 libgloss/xtensa/app.elf.ld
create mode 100644 libgloss/xtensa/board.elf.specs
create mode 100644 libgloss/xtensa/boards/esp32/board.c
create mode 100644 libgloss/xtensa/boards/esp32/include/soc/cpu.h
create mode 100644 libgloss/xtensa/boards/esp32/include/soc/uart.h
create mode 100644 libgloss/xtensa/boards/esp32/memory.elf.ld
create mode 100644 libgloss/xtensa/boards/esp32s3/board.c
create mode 100644 libgloss/xtensa/boards/esp32s3/include/soc/cpu.h
create mode 100644 libgloss/xtensa/boards/esp32s3/include/soc/uart.h
create mode 100644 libgloss/xtensa/boards/esp32s3/memory.elf.ld
create mode 100644 libgloss/xtensa/crt0.S
create mode 100644 libgloss/xtensa/crt1-boards.S
create mode 100644 libgloss/xtensa/crt1-sim.S
create mode 100644 libgloss/xtensa/default.specs
create mode 100644 libgloss/xtensa/include/register_access.h
create mode 100644 libgloss/xtensa/include/syscalls.h
create mode 100644 libgloss/xtensa/include/xtensa/corebits.h
create mode 100644 libgloss/xtensa/nano.specs
create mode 100644 libgloss/xtensa/sim-call.S
create mode 100644 libgloss/xtensa/sim-vectors.S
create mode 100644 libgloss/xtensa/sim.elf.specs
create mode 100644 libgloss/xtensa/sleep.S
create mode 100644 libgloss/xtensa/sys.openocd.specs
create mode 100644 libgloss/xtensa/sys.qemu.specs
create mode 100644 libgloss/xtensa/syscalls.c
create mode 100644 libgloss/xtensa/window-vectors.S
diff --git a/libgloss/Makefile.am b/libgloss/Makefile.am
index d4b7d4077..f440ad23a 100644
--- a/libgloss/Makefile.am
+++ b/libgloss/Makefile.am
@@ -103,3 +103,6 @@ endif
if CONFIG_WINCE
include wince/Makefile.inc
endif
+if CONFIG_XTENSA
+include xtensa/Makefile.inc
+endif
diff --git a/libgloss/Makefile.in b/libgloss/Makefile.in
index 7f46375c0..e20f1eb90 100644
--- a/libgloss/Makefile.in
+++ b/libgloss/Makefile.in
@@ -190,6 +190,32 @@ check_PROGRAMS = $(am__EXEEXT_2) $(am__EXEEXT_3)
@CONFIG_RISCV_TRUE@ riscv/libsemihost.a
@CONFIG_WINCE_TRUE@am__append_36 = $(gdbdir)
@CONFIG_WINCE_TRUE@am__append_37 = wince/stub.exe
+@CONFIG_XTENSA_TRUE@am__append_38 = -D_LIBGLOSS -I$(srcdir)/xtensa/include
+@CONFIG_XTENSA_TRUE@am__append_39 = \
+@CONFIG_XTENSA_TRUE@ xtensa/default.specs \
+@CONFIG_XTENSA_TRUE@ xtensa/nano.specs \
+@CONFIG_XTENSA_TRUE@ xtensa/crt0.o
+
+@CONFIG_XTENSA_TRUE@am__append_40 = xtensa/libgloss.a
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_41 = \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/sim.elf.specs \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/board.elf.specs \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/sys.qemu.specs \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/sys.openocd.specs \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/app.elf.ld \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/crt1-sim.o \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/crt1-boards.o
+
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_42 = xtensa/libsys_qemu.a \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/libsys_openocd.a
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_43 = xtensa/boards/esp32/memory.elf.ld
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_44 = xtensa/boards/esp32/board.c
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_45 = -I$(srcdir)/xtensa/boards/esp32/include
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_46 = -I$(srcdir)/xtensa/boards/esp32/include
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_47 = xtensa/boards/esp32s3/memory.elf.ld
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_48 = xtensa/boards/esp32s3/board.c
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_49 = -I$(srcdir)/xtensa/boards/esp32s3/include
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__append_50 = -I$(srcdir)/xtensa/boards/esp32s3/include
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/depstand.m4 \
@@ -203,7 +229,8 @@ am__aclocal_m4_deps = $(top_srcdir)/../config/depstand.m4 \
$(top_srcdir)/mcore/acinclude.m4 \
$(top_srcdir)/mips/acinclude.m4 \
$(top_srcdir)/mn10300/acinclude.m4 \
- $(top_srcdir)/moxie/acinclude.m4 $(top_srcdir)/configure.ac
+ $(top_srcdir)/moxie/acinclude.m4 \
+ $(top_srcdir)/xtensa/acinclude.m4 $(top_srcdir)/configure.ac
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
$(ACLOCAL_M4)
DIST_COMMON = $(srcdir)/Makefile.am $(top_srcdir)/configure \
@@ -515,6 +542,27 @@ riscv_libsemihost_a_LIBADD =
@CONFIG_RISCV_TRUE@ riscv/riscv_libsemihost_a-semihost-sys_unlink.$(OBJEXT) \
@CONFIG_RISCV_TRUE@ riscv/riscv_libsemihost_a-semihost-sys_write.$(OBJEXT)
riscv_libsemihost_a_OBJECTS = $(am_riscv_libsemihost_a_OBJECTS)
+xtensa_libgloss_a_AR = $(AR) $(ARFLAGS)
+xtensa_libgloss_a_LIBADD =
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__objects_7 = xtensa/boards/esp32/xtensa_libgloss_a-board.$(OBJEXT)
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am__objects_8 = xtensa/boards/esp32s3/xtensa_libgloss_a-board.$(OBJEXT)
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am_xtensa_libgloss_a_OBJECTS = xtensa/xtensa_libgloss_a-sleep.$(OBJEXT) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/xtensa_libgloss_a-syscalls.$(OBJEXT) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/xtensa_libgloss_a-window-vectors.$(OBJEXT) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__objects_7) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__objects_8)
+xtensa_libgloss_a_OBJECTS = $(am_xtensa_libgloss_a_OBJECTS)
+xtensa_libsys_openocd_a_AR = $(AR) $(ARFLAGS)
+xtensa_libsys_openocd_a_LIBADD =
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am_xtensa_libsys_openocd_a_OBJECTS = xtensa/xtensa_libsys_openocd_a-syscalls.$(OBJEXT)
+xtensa_libsys_openocd_a_OBJECTS = \
+ $(am_xtensa_libsys_openocd_a_OBJECTS)
+xtensa_libsys_qemu_a_AR = $(AR) $(ARFLAGS)
+xtensa_libsys_qemu_a_LIBADD =
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@am_xtensa_libsys_qemu_a_OBJECTS = xtensa/xtensa_libsys_qemu_a-sim-vectors.$(OBJEXT) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/xtensa_libsys_qemu_a-sim-call.$(OBJEXT) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/xtensa_libsys_qemu_a-syscalls.$(OBJEXT)
+xtensa_libsys_qemu_a_OBJECTS = $(am_xtensa_libsys_qemu_a_OBJECTS)
@CONFIG_WINCE_TRUE@am__EXEEXT_1 = wince/stub.exe$(EXEEXT)
@CONFIG_BFIN_TRUE@am__EXEEXT_2 = bfin/sim-test$(EXEEXT)
@CONFIG_IQ2000_TRUE@am__EXEEXT_3 = iq2000/test$(EXEEXT)
@@ -575,7 +623,9 @@ SOURCES = $(aarch64_librdimon_a_SOURCES) $(arc_libnsim_a_SOURCES) \
$(iq2000_libeval_a_SOURCES) $(libnosys_libnosys_a_SOURCES) \
$(libobjs_a_SOURCES) $(lm32_libgloss_a_SOURCES) \
$(nios2_libnios2_a_SOURCES) $(riscv_libgloss_a_SOURCES) \
- $(riscv_libsemihost_a_SOURCES) bfin/sim-test.c iq2000/test.c \
+ $(riscv_libsemihost_a_SOURCES) $(xtensa_libgloss_a_SOURCES) \
+ $(xtensa_libsys_openocd_a_SOURCES) \
+ $(xtensa_libsys_qemu_a_SOURCES) bfin/sim-test.c iq2000/test.c \
$(wince_stub_exe_SOURCES)
AM_V_DVIPS = $(am__v_DVIPS_@AM_V@)
am__v_DVIPS_ = $(am__v_DVIPS_@AM_DEFAULT_V@)
@@ -681,7 +731,7 @@ CCASFLAGS = @CCASFLAGS@
CCDEPMODE = @CCDEPMODE@
CFLAGS = @CFLAGS@
CPP = @CPP@
-CPPFLAGS = @CPPFLAGS@
+CPPFLAGS = @CPPFLAGS@ $(am__append_38)
CYGPATH_W = @CYGPATH_W@
DEFS = @DEFS@
DEPDIR = @DEPDIR@
@@ -728,6 +778,7 @@ SET_MAKE = @SET_MAKE@
SHELL = @SHELL@
STRIP = @STRIP@
VERSION = @VERSION@
+XTENSA_BOARD_ESP = @XTENSA_BOARD_ESP@
abs_builddir = @abs_builddir@
abs_srcdir = @abs_srcdir@
abs_top_builddir = @abs_top_builddir@
@@ -799,11 +850,13 @@ multilibtool_DATA = $(am__append_3) $(am__append_6) $(am__append_7) \
$(am__append_8) $(am__append_13) $(am__append_15) \
$(am__append_18) $(am__append_22) $(am__append_23) \
$(am__append_27) $(am__append_29) $(am__append_32) \
- $(am__append_34)
+ $(am__append_34) $(am__append_39) $(am__append_41) \
+ $(am__append_43) $(am__append_47)
multilibtool_LIBRARIES = $(am__append_2) $(am__append_5) \
$(am__append_9) $(am__append_11) $(am__append_20) \
$(am__append_21) $(am__append_24) $(am__append_28) \
- $(am__append_30) $(am__append_33) $(am__append_35)
+ $(am__append_30) $(am__append_33) $(am__append_35) \
+ $(am__append_40) $(am__append_42)
includetooldir = $(tooldir)/include
includetool_DATA = $(am__append_16)
includesystooldir = $(tooldir)/include/sys
@@ -1095,6 +1148,27 @@ TEXINFO_TEX = ../texinfo/texinfo.tex
@CONFIG_WINCE_TRUE@wince_stub_exe_SOURCES = wince-stub.c
@CONFIG_WINCE_TRUE@wince_stub_exe_CPPFLAGS = $(AM_CPPFLAGS) -I$(gdbdir)
@CONFIG_WINCE_TRUE@wince_stub_exe_LDADD = -lwinsock $(WINCE_STUB_LIBS)
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libgloss_a_SOURCES = xtensa/sleep.S \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/syscalls.c \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/window-vectors.S \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_44) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_48)
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libsys_qemu_a_CPPFLAGS = -DQEMU_SEMIHOSTING \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_45) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_49)
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libsys_qemu_a_SOURCES = \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/sim-vectors.S \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/sim-call.S \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/syscalls.c
+
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libsys_openocd_a_CPPFLAGS = -DOPENOCD_SEMIHOSTING \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_46) \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ $(am__append_50)
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libsys_openocd_a_SOURCES = \
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@ xtensa/syscalls.c
+
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32S3_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libgloss_a_CPPFLAGS = -I$(srcdir)/xtensa/boards/esp32s3/include
+@CONFIG_XTENSA_TRUE@@HAVE_XTENSA_BOARD_ESP32_TRUE@@HAVE_XTENSA_BOARD_ESP_TRUE@xtensa_libgloss_a_CPPFLAGS = -I$(srcdir)/xtensa/boards/esp32/include
all: config.h
$(MAKE) $(AM_MAKEFLAGS) all-recursive
@@ -1102,7 +1176,7 @@ all: config.h
.SUFFIXES: .S .c .dvi .o .obj .ps
am--refresh: Makefile
@:
-$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/aarch64/Makefile.inc $(srcdir)/aarch64/cpu-init/Makefile.inc $(srcdir)/arc/Makefile.inc $(srcdir)/arm/Makefile.inc $(srcdir)/arm/cpu-init/Makefile.inc $(srcdir)/bfin/Makefile.inc $(srcdir)/csky/Makefile.inc $(srcdir)/d30v/Makefile.inc $(srcdir)/iq2000/Makefile.inc $(srcdir)/libnosys/Makefile.inc $(srcdir)/lm32/Makefile.inc $(srcdir)/nios2/Makefile.inc $(srcdir)/riscv/Makefile.inc $(srcdir)/wince/Makefile.inc $(am__configure_deps)
+$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(top_srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/aarch64/Makefile.inc $(srcdir)/aarch64/cpu-init/Makefile.inc $(srcdir)/arc/Makefile.inc $(srcdir)/arm/Makefile.inc $(srcdir)/arm/cpu-init/Makefile.inc $(srcdir)/bfin/Makefile.inc $(srcdir)/csky/Makefile.inc $(srcdir)/d30v/Makefile.inc $(srcdir)/iq2000/Makefile.inc $(srcdir)/libnosys/Makefile.inc $(srcdir)/lm32/Makefile.inc $(srcdir)/nios2/Makefile.inc $(srcdir)/riscv/Makefile.inc $(srcdir)/wince/Makefile.inc $(srcdir)/xtensa/Makefile.inc $(am__configure_deps)
@for dep in $?; do \
case '$(am__configure_deps)' in \
*$$dep*) \
@@ -1124,7 +1198,7 @@ Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \
cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \
esac;
-$(top_srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/aarch64/Makefile.inc $(srcdir)/aarch64/cpu-init/Makefile.inc $(srcdir)/arc/Makefile.inc $(srcdir)/arm/Makefile.inc $(srcdir)/arm/cpu-init/Makefile.inc $(srcdir)/bfin/Makefile.inc $(srcdir)/csky/Makefile.inc $(srcdir)/d30v/Makefile.inc $(srcdir)/iq2000/Makefile.inc $(srcdir)/libnosys/Makefile.inc $(srcdir)/lm32/Makefile.inc $(srcdir)/nios2/Makefile.inc $(srcdir)/riscv/Makefile.inc $(srcdir)/wince/Makefile.inc $(am__empty):
+$(top_srcdir)/../multilib.am $(srcdir)/doc/Makefile.inc $(srcdir)/aarch64/Makefile.inc $(srcdir)/aarch64/cpu-init/Makefile.inc $(srcdir)/arc/Makefile.inc $(srcdir)/arm/Makefile.inc $(srcdir)/arm/cpu-init/Makefile.inc $(srcdir)/bfin/Makefile.inc $(srcdir)/csky/Makefile.inc $(srcdir)/d30v/Makefile.inc $(srcdir)/iq2000/Makefile.inc $(srcdir)/libnosys/Makefile.inc $(srcdir)/lm32/Makefile.inc $(srcdir)/nios2/Makefile.inc $(srcdir)/riscv/Makefile.inc $(srcdir)/wince/Makefile.inc $(srcdir)/xtensa/Makefile.inc $(am__empty):
$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
$(SHELL) ./config.status --recheck
@@ -1782,6 +1856,59 @@ riscv/libsemihost.a: $(riscv_libsemihost_a_OBJECTS) $(riscv_libsemihost_a_DEPEND
$(AM_V_at)-rm -f riscv/libsemihost.a
$(AM_V_AR)$(riscv_libsemihost_a_AR) riscv/libsemihost.a $(riscv_libsemihost_a_OBJECTS) $(riscv_libsemihost_a_LIBADD)
$(AM_V_at)$(RANLIB) riscv/libsemihost.a
+xtensa/$(am__dirstamp):
+ @$(MKDIR_P) xtensa
+ @: > xtensa/$(am__dirstamp)
+xtensa/$(DEPDIR)/$(am__dirstamp):
+ @$(MKDIR_P) xtensa/$(DEPDIR)
+ @: > xtensa/$(DEPDIR)/$(am__dirstamp)
+xtensa/xtensa_libgloss_a-sleep.$(OBJEXT): xtensa/$(am__dirstamp) \
+ xtensa/$(DEPDIR)/$(am__dirstamp)
+xtensa/xtensa_libgloss_a-syscalls.$(OBJEXT): xtensa/$(am__dirstamp) \
+ xtensa/$(DEPDIR)/$(am__dirstamp)
+xtensa/xtensa_libgloss_a-window-vectors.$(OBJEXT): \
+ xtensa/$(am__dirstamp) xtensa/$(DEPDIR)/$(am__dirstamp)
+xtensa/boards/esp32/$(am__dirstamp):
+ @$(MKDIR_P) xtensa/boards/esp32
+ @: > xtensa/boards/esp32/$(am__dirstamp)
+xtensa/boards/esp32/$(DEPDIR)/$(am__dirstamp):
+ @$(MKDIR_P) xtensa/boards/esp32/$(DEPDIR)
+ @: > xtensa/boards/esp32/$(DEPDIR)/$(am__dirstamp)
+xtensa/boards/esp32/xtensa_libgloss_a-board.$(OBJEXT): \
+ xtensa/boards/esp32/$(am__dirstamp) \
+ xtensa/boards/esp32/$(DEPDIR)/$(am__dirstamp)
+xtensa/boards/esp32s3/$(am__dirstamp):
+ @$(MKDIR_P) xtensa/boards/esp32s3
+ @: > xtensa/boards/esp32s3/$(am__dirstamp)
+xtensa/boards/esp32s3/$(DEPDIR)/$(am__dirstamp):
+ @$(MKDIR_P) xtensa/boards/esp32s3/$(DEPDIR)
+ @: > xtensa/boards/esp32s3/$(DEPDIR)/$(am__dirstamp)
+xtensa/boards/esp32s3/xtensa_libgloss_a-board.$(OBJEXT): \
+ xtensa/boards/esp32s3/$(am__dirstamp) \
+ xtensa/boards/esp32s3/$(DEPDIR)/$(am__dirstamp)
+
+xtensa/libgloss.a: $(xtensa_libgloss_a_OBJECTS) $(xtensa_libgloss_a_DEPENDENCIES) $(EXTRA_xtensa_libgloss_a_DEPENDENCIES) xtensa/$(am__dirstamp)
+ $(AM_V_at)-rm -f xtensa/libgloss.a
+ $(AM_V_AR)$(xtensa_libgloss_a_AR) xtensa/libgloss.a $(xtensa_libgloss_a_OBJECTS) $(xtensa_libgloss_a_LIBADD)
+ $(AM_V_at)$(RANLIB) xtensa/libgloss.a
+xtensa/xtensa_libsys_openocd_a-syscalls.$(OBJEXT): \
+ xtensa/$(am__dirstamp) xtensa/$(DEPDIR)/$(am__dirstamp)
+
+xtensa/libsys_openocd.a: $(xtensa_libsys_openocd_a_OBJECTS) $(xtensa_libsys_openocd_a_DEPENDENCIES) $(EXTRA_xtensa_libsys_openocd_a_DEPENDENCIES) xtensa/$(am__dirstamp)
+ $(AM_V_at)-rm -f xtensa/libsys_openocd.a
+ $(AM_V_AR)$(xtensa_libsys_openocd_a_AR) xtensa/libsys_openocd.a $(xtensa_libsys_openocd_a_OBJECTS) $(xtensa_libsys_openocd_a_LIBADD)
+ $(AM_V_at)$(RANLIB) xtensa/libsys_openocd.a
+xtensa/xtensa_libsys_qemu_a-sim-vectors.$(OBJEXT): \
+ xtensa/$(am__dirstamp) xtensa/$(DEPDIR)/$(am__dirstamp)
+xtensa/xtensa_libsys_qemu_a-sim-call.$(OBJEXT): \
+ xtensa/$(am__dirstamp) xtensa/$(DEPDIR)/$(am__dirstamp)
+xtensa/xtensa_libsys_qemu_a-syscalls.$(OBJEXT): \
+ xtensa/$(am__dirstamp) xtensa/$(DEPDIR)/$(am__dirstamp)
+
+xtensa/libsys_qemu.a: $(xtensa_libsys_qemu_a_OBJECTS) $(xtensa_libsys_qemu_a_DEPENDENCIES) $(EXTRA_xtensa_libsys_qemu_a_DEPENDENCIES) xtensa/$(am__dirstamp)
+ $(AM_V_at)-rm -f xtensa/libsys_qemu.a
+ $(AM_V_AR)$(xtensa_libsys_qemu_a_AR) xtensa/libsys_qemu.a $(xtensa_libsys_qemu_a_OBJECTS) $(xtensa_libsys_qemu_a_LIBADD)
+ $(AM_V_at)$(RANLIB) xtensa/libsys_qemu.a
install-binPROGRAMS: $(bin_PROGRAMS)
@$(NORMAL_INSTALL)
@list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \
@@ -1860,6 +1987,9 @@ mostlyclean-compile:
-rm -f lm32/*.$(OBJEXT)
-rm -f nios2/*.$(OBJEXT)
-rm -f riscv/*.$(OBJEXT)
+ -rm -f xtensa/*.$(OBJEXT)
+ -rm -f xtensa/boards/esp32/*.$(OBJEXT)
+ -rm -f xtensa/boards/esp32s3/*.$(OBJEXT)
distclean-compile:
-rm -f *.tab.c
@@ -2060,6 +2190,15 @@ distclean-compile:
@AMDEP_TRUE@@am__include@ @am__quote@riscv/$(DEPDIR)/riscv_libsemihost_a-sys_kill.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@riscv/$(DEPDIR)/riscv_libsemihost_a-sys_utime.Po@am__quote@
@AMDEP_TRUE@@am__include@ @am__quote@riscv/$(DEPDIR)/riscv_libsemihost_a-sys_wait.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/$(DEPDIR)/xtensa_libgloss_a-sleep.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/$(DEPDIR)/xtensa_libgloss_a-syscalls.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/$(DEPDIR)/xtensa_libgloss_a-window-vectors.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/$(DEPDIR)/xtensa_libsys_openocd_a-syscalls.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-sim-call.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-sim-vectors.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-syscalls.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/boards/esp32/$(DEPDIR)/xtensa_libgloss_a-board.Po@am__quote@
+@AMDEP_TRUE@@am__include@ @am__quote@xtensa/boards/esp32s3/$(DEPDIR)/xtensa_libgloss_a-board.Po@am__quote@
.S.o:
@am__fastdepCCAS_TRUE@ $(AM_V_CPPAS)depbase=`echo $@ | sed 's|[^/]*$$|$(DEPDIR)/&|;s|\.o$$||'`;\
@@ -2147,6 +2286,62 @@ nios2/nios2_libnios2_a-io-nios2.obj: nios2/io-nios2.S
@AMDEP_TRUE@@am__fastdepCCAS_FALSE@ DEPDIR=$(DEPDIR) $(CCASDEPMODE) $(depcomp) @AMDEPBACKSLASH@
@am__fastdepCCAS_FALSE@ $(AM_V_CPPAS@am__nodep@)$(CCAS) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(nios2_libnios2_a_CPPFLAGS) $(CPPFLAGS) $(AM_CCASFLAGS) $(CCASFLAGS) -c -o nios2/nios2_libnios2_a-io-nios2.obj `if test -f 'nios2/io-nios2.S'; then $(CYGPATH_W) 'nios2/io-nios2.S'; else $(CYGPATH_W) '$(srcdir)/nios2/io-nios2.S'; fi`
+xtensa/xtensa_libgloss_a-sleep.o: xtensa/sleep.S
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+
+xtensa/xtensa_libsys_openocd_a-syscalls.o: xtensa/syscalls.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(xtensa_libsys_openocd_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xtensa/xtensa_libsys_openocd_a-syscalls.o -MD -MP -MF xtensa/$(DEPDIR)/xtensa_libsys_openocd_a-syscalls.Tpo -c -o xtensa/xtensa_libsys_openocd_a-syscalls.o `test -f 'xtensa/syscalls.c' || echo '$(srcdir)/'`xtensa/syscalls.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) xtensa/$(DEPDIR)/xtensa_libsys_openocd_a-syscalls.Tpo xtensa/$(DEPDIR)/xtensa_libsys_openocd_a-syscalls.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='xtensa/syscalls.c' object='xtensa/xtensa_libsys_openocd_a-syscalls.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(xtensa_libsys_openocd_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xtensa/xtensa_libsys_openocd_a-syscalls.o `test -f 'xtensa/syscalls.c' || echo '$(srcdir)/'`xtensa/syscalls.c
+
+xtensa/xtensa_libsys_openocd_a-syscalls.obj: xtensa/syscalls.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(xtensa_libsys_openocd_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xtensa/xtensa_libsys_openocd_a-syscalls.obj -MD -MP -MF xtensa/$(DEPDIR)/xtensa_libsys_openocd_a-syscalls.Tpo -c -o xtensa/xtensa_libsys_openocd_a-syscalls.obj `if test -f 'xtensa/syscalls.c'; then $(CYGPATH_W) 'xtensa/syscalls.c'; else $(CYGPATH_W) '$(srcdir)/xtensa/syscalls.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) xtensa/$(DEPDIR)/xtensa_libsys_openocd_a-syscalls.Tpo xtensa/$(DEPDIR)/xtensa_libsys_openocd_a-syscalls.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='xtensa/syscalls.c' object='xtensa/xtensa_libsys_openocd_a-syscalls.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(xtensa_libsys_openocd_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xtensa/xtensa_libsys_openocd_a-syscalls.obj `if test -f 'xtensa/syscalls.c'; then $(CYGPATH_W) 'xtensa/syscalls.c'; else $(CYGPATH_W) '$(srcdir)/xtensa/syscalls.c'; fi`
+
+xtensa/xtensa_libsys_qemu_a-syscalls.o: xtensa/syscalls.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(xtensa_libsys_qemu_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xtensa/xtensa_libsys_qemu_a-syscalls.o -MD -MP -MF xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-syscalls.Tpo -c -o xtensa/xtensa_libsys_qemu_a-syscalls.o `test -f 'xtensa/syscalls.c' || echo '$(srcdir)/'`xtensa/syscalls.c
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-syscalls.Tpo xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-syscalls.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='xtensa/syscalls.c' object='xtensa/xtensa_libsys_qemu_a-syscalls.o' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(xtensa_libsys_qemu_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xtensa/xtensa_libsys_qemu_a-syscalls.o `test -f 'xtensa/syscalls.c' || echo '$(srcdir)/'`xtensa/syscalls.c
+
+xtensa/xtensa_libsys_qemu_a-syscalls.obj: xtensa/syscalls.c
+@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(xtensa_libsys_qemu_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xtensa/xtensa_libsys_qemu_a-syscalls.obj -MD -MP -MF xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-syscalls.Tpo -c -o xtensa/xtensa_libsys_qemu_a-syscalls.obj `if test -f 'xtensa/syscalls.c'; then $(CYGPATH_W) 'xtensa/syscalls.c'; else $(CYGPATH_W) '$(srcdir)/xtensa/syscalls.c'; fi`
+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-syscalls.Tpo xtensa/$(DEPDIR)/xtensa_libsys_qemu_a-syscalls.Po
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='xtensa/syscalls.c' object='xtensa/xtensa_libsys_qemu_a-syscalls.obj' libtool=no @AMDEPBACKSLASH@
+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(xtensa_libsys_qemu_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xtensa/xtensa_libsys_qemu_a-syscalls.obj `if test -f 'xtensa/syscalls.c'; then $(CYGPATH_W) 'xtensa/syscalls.c'; else $(CYGPATH_W) '$(srcdir)/xtensa/syscalls.c'; fi`
+
wince_stub_exe-wince-stub.o: wince-stub.c
@am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(wince_stub_exe_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT wince_stub_exe-wince-stub.o -MD -MP -MF $(DEPDIR)/wince_stub_exe-wince-stub.Tpo -c -o wince_stub_exe-wince-stub.o `test -f 'wince-stub.c' || echo '$(srcdir)/'`wince-stub.c
@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/wince_stub_exe-wince-stub.Tpo $(DEPDIR)/wince_stub_exe-wince-stub.Po
@@ -4233,6 +4498,12 @@ distclean-generic:
-rm -f riscv/$(DEPDIR)/$(am__dirstamp)
-rm -f riscv/$(am__dirstamp)
-rm -f wince/$(am__dirstamp)
+ -rm -f xtensa/$(DEPDIR)/$(am__dirstamp)
+ -rm -f xtensa/$(am__dirstamp)
+ -rm -f xtensa/boards/esp32/$(DEPDIR)/$(am__dirstamp)
+ -rm -f xtensa/boards/esp32/$(am__dirstamp)
+ -rm -f xtensa/boards/esp32s3/$(DEPDIR)/$(am__dirstamp)
+ -rm -f xtensa/boards/esp32s3/$(am__dirstamp)
maintainer-clean-generic:
@echo "This command is intended for maintainers to use"
@@ -4245,7 +4516,7 @@ clean-am: clean-aminfo clean-binPROGRAMS clean-checkPROGRAMS \
distclean: distclean-recursive
-rm -f $(am__CONFIG_DISTCLEAN_FILES)
- -rm -rf ./$(DEPDIR) aarch64/$(DEPDIR) arc/$(DEPDIR) arm/$(DEPDIR) bfin/$(DEPDIR) csky/$(DEPDIR) d30v/$(DEPDIR) iq2000/$(DEPDIR) libnosys/$(DEPDIR) lm32/$(DEPDIR) nios2/$(DEPDIR) riscv/$(DEPDIR)
+ -rm -rf ./$(DEPDIR) aarch64/$(DEPDIR) arc/$(DEPDIR) arm/$(DEPDIR) bfin/$(DEPDIR) csky/$(DEPDIR) d30v/$(DEPDIR) iq2000/$(DEPDIR) libnosys/$(DEPDIR) lm32/$(DEPDIR) nios2/$(DEPDIR) riscv/$(DEPDIR) xtensa/$(DEPDIR) xtensa/boards/esp32/$(DEPDIR) xtensa/boards/esp32s3/$(DEPDIR)
-rm -f Makefile
distclean-am: clean-am distclean-compile distclean-generic \
distclean-hdr distclean-local distclean-tags
@@ -4388,7 +4659,7 @@ installcheck-am:
maintainer-clean: maintainer-clean-recursive
-rm -f $(am__CONFIG_DISTCLEAN_FILES)
-rm -rf $(top_srcdir)/autom4te.cache
- -rm -rf ./$(DEPDIR) aarch64/$(DEPDIR) arc/$(DEPDIR) arm/$(DEPDIR) bfin/$(DEPDIR) csky/$(DEPDIR) d30v/$(DEPDIR) iq2000/$(DEPDIR) libnosys/$(DEPDIR) lm32/$(DEPDIR) nios2/$(DEPDIR) riscv/$(DEPDIR)
+ -rm -rf ./$(DEPDIR) aarch64/$(DEPDIR) arc/$(DEPDIR) arm/$(DEPDIR) bfin/$(DEPDIR) csky/$(DEPDIR) d30v/$(DEPDIR) iq2000/$(DEPDIR) libnosys/$(DEPDIR) lm32/$(DEPDIR) nios2/$(DEPDIR) riscv/$(DEPDIR) xtensa/$(DEPDIR) xtensa/boards/esp32/$(DEPDIR) xtensa/boards/esp32s3/$(DEPDIR)
-rm -f Makefile
maintainer-clean-am: distclean-am maintainer-clean-aminfo \
maintainer-clean-generic maintainer-clean-local
@@ -4537,6 +4808,9 @@ maintainer-clean-local: maintainer-clean-multi
@CONFIG_BFIN_TRUE@bfin/basiccrt60xc1.$(OBJEXT): bfin/basiccrt.S
@CONFIG_BFIN_TRUE@ $(AM_V_CPPAS)$(CPPASCOMPILE) $(bfin_CPPFLAGS) -o $@ -c $< $(if $(findstring mcpu=,$(CFLAGS)),-mcpu=bf608-any,-mcpu=bf608-none) -D__ADSPBF60x_CORE1__
+@CONFIG_XTENSA_TRUE@xtensa/crt0.$(OBJEXT): xtensa/crt0.S
+@CONFIG_XTENSA_TRUE@ $(AM_V_CPPAS)$(CPPASCOMPILE) $(CPPFLAGS) -o $@ -c $<
+
# Tell versions [3.59,3.63) of GNU make to not export all variables.
# Otherwise a system limit (for SysV at least) may be exceeded.
.NOEXPORT:
diff --git a/libgloss/configure b/libgloss/configure
index c07610411..3c0db8121 100755
--- a/libgloss/configure
+++ b/libgloss/configure
@@ -589,6 +589,13 @@ LIBOBJS
multi_basedir
target_makefile_frag_path
host_makefile_frag_path
+HAVE_XTENSA_BOARD_ESP_FALSE
+HAVE_XTENSA_BOARD_ESP_TRUE
+HAVE_XTENSA_BOARD_ESP32S3_FALSE
+HAVE_XTENSA_BOARD_ESP32S3_TRUE
+HAVE_XTENSA_BOARD_ESP32_FALSE
+HAVE_XTENSA_BOARD_ESP32_TRUE
+XTENSA_BOARD_ESP
MOXIE_BUILD_CRT0_FALSE
MOXIE_BUILD_CRT0_TRUE
MN10300_BSP_LIST
@@ -632,6 +639,8 @@ CFLAGS
CC
NEED_TOP_INCLUDE_DIR_FALSE
NEED_TOP_INCLUDE_DIR_TRUE
+CONFIG_XTENSA_FALSE
+CONFIG_XTENSA_TRUE
CONFIG_WINCE_FALSE
CONFIG_WINCE_TRUE
CONFIG_RISCV_FALSE
@@ -2928,6 +2937,9 @@ case "${target}" in
subdirs="$subdirs xstormy16"
;;
+ xtensa-*-*)
+ config_xtensa=true
+ ;;
m32c-*-*)
ac_config_files="$ac_config_files m32c/Makefile"
@@ -3082,6 +3094,14 @@ else
CONFIG_WINCE_FALSE=
fi
+ if test x$config_xtensa = xtrue; then
+ CONFIG_XTENSA_TRUE=
+ CONFIG_XTENSA_FALSE='#'
+else
+ CONFIG_XTENSA_TRUE='#'
+ CONFIG_XTENSA_FALSE=
+fi
+
if test x$config_arm = xtrue; then
@@ -4959,6 +4979,7 @@ case "${target}" in
v850*-*-*) ;;
w65-*-*) ;;
xstormy16-*-*) ;;
+ xtensa-*-*) ;;
z8k-*-*) ;;
*)
$as_echo "#define MISSING_SYSCALL_NAMES 1" >>confdefs.h
@@ -5099,6 +5120,33 @@ esac
+XTENSA_BOARD_ESP=`echo $CC | sed 's/.*-mdynconfig=xtensa_\(.*\)\.so.*/\1/;s/.*-mcpu=\(^ *\).*/\1/;s/.* .*/unknown/'`
+
+ if test x$XTENSA_BOARD_ESP = xesp32; then
+ HAVE_XTENSA_BOARD_ESP32_TRUE=
+ HAVE_XTENSA_BOARD_ESP32_FALSE='#'
+else
+ HAVE_XTENSA_BOARD_ESP32_TRUE='#'
+ HAVE_XTENSA_BOARD_ESP32_FALSE=
+fi
+
+ if test x$XTENSA_BOARD_ESP = xesp32s3; then
+ HAVE_XTENSA_BOARD_ESP32S3_TRUE=
+ HAVE_XTENSA_BOARD_ESP32S3_FALSE='#'
+else
+ HAVE_XTENSA_BOARD_ESP32S3_TRUE='#'
+ HAVE_XTENSA_BOARD_ESP32S3_FALSE=
+fi
+
+ if echo $XTENSA_BOARD_ESP | grep -w -e esp32 -e esp32s3 >/dev/null 2>&1; then
+ HAVE_XTENSA_BOARD_ESP_TRUE=
+ HAVE_XTENSA_BOARD_ESP_FALSE='#'
+else
+ HAVE_XTENSA_BOARD_ESP_TRUE='#'
+ HAVE_XTENSA_BOARD_ESP_FALSE=
+fi
+
+
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for compiler search settings" >&5
$as_echo_n "checking for compiler search settings... " >&6; }
@@ -5359,6 +5407,10 @@ if test -z "${CONFIG_WINCE_TRUE}" && test -z "${CONFIG_WINCE_FALSE}"; then
as_fn_error $? "conditional \"CONFIG_WINCE\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${CONFIG_XTENSA_TRUE}" && test -z "${CONFIG_XTENSA_FALSE}"; then
+ as_fn_error $? "conditional \"CONFIG_XTENSA\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
if test -z "${NEED_TOP_INCLUDE_DIR_TRUE}" && test -z "${NEED_TOP_INCLUDE_DIR_FALSE}"; then
as_fn_error $? "conditional \"NEED_TOP_INCLUDE_DIR\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
@@ -5375,6 +5427,18 @@ if test -z "${am__fastdepCCAS_TRUE}" && test -z "${am__fastdepCCAS_FALSE}"; then
as_fn_error $? "conditional \"am__fastdepCCAS\" was never defined.
Usually this means the macro was only invoked conditionally." "$LINENO" 5
fi
+if test -z "${HAVE_XTENSA_BOARD_ESP32_TRUE}" && test -z "${HAVE_XTENSA_BOARD_ESP32_FALSE}"; then
+ as_fn_error $? "conditional \"HAVE_XTENSA_BOARD_ESP32\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAVE_XTENSA_BOARD_ESP32S3_TRUE}" && test -z "${HAVE_XTENSA_BOARD_ESP32S3_FALSE}"; then
+ as_fn_error $? "conditional \"HAVE_XTENSA_BOARD_ESP32S3\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
+if test -z "${HAVE_XTENSA_BOARD_ESP_TRUE}" && test -z "${HAVE_XTENSA_BOARD_ESP_FALSE}"; then
+ as_fn_error $? "conditional \"HAVE_XTENSA_BOARD_ESP\" was never defined.
+Usually this means the macro was only invoked conditionally." "$LINENO" 5
+fi
: "${CONFIG_STATUS=./config.status}"
ac_write_fail=0
diff --git a/libgloss/configure.ac b/libgloss/configure.ac
index a332193ce..47854eab3 100644
--- a/libgloss/configure.ac
+++ b/libgloss/configure.ac
@@ -195,6 +195,9 @@ case "${target}" in
AC_CONFIG_FILES([xstormy16/Makefile])
subdirs="$subdirs xstormy16"
;;
+ xtensa-*-*)
+ config_xtensa=true
+ ;;
m32c-*-*)
AC_CONFIG_FILES([m32c/Makefile])
subdirs="$subdirs m32c"
@@ -248,7 +251,7 @@ AC_SUBST(subdirs)
dnl These subdirs have converted to non-recursive make. Hopefully someday all
dnl the ports above will too!
m4_foreach_w([SUBDIR], [
- aarch64 arc arm bfin csky d30v iq2000 libnosys lm32 nios2 riscv wince
+ aarch64 arc arm bfin csky d30v iq2000 libnosys lm32 nios2 riscv wince xtensa
], [dnl
AM_CONDITIONAL([CONFIG_]m4_toupper(SUBDIR), [test x$config_]SUBDIR = xtrue)
])
@@ -352,6 +355,7 @@ m4_include([mcore/acinclude.m4])
m4_include([mips/acinclude.m4])
m4_include([mn10300/acinclude.m4])
m4_include([moxie/acinclude.m4])
+m4_include([xtensa/acinclude.m4])
AC_CACHE_CHECK([for compiler search settings], libc_cv_compiler_isystem, [dnl
for subdir in include include-fixed; do
diff --git a/libgloss/libnosys/acinclude.m4 b/libgloss/libnosys/acinclude.m4
index 7b0d7b4d6..ba293f08a 100644
--- a/libgloss/libnosys/acinclude.m4
+++ b/libgloss/libnosys/acinclude.m4
@@ -22,6 +22,7 @@ case "${target}" in
v850*-*-*) ;;
w65-*-*) ;;
xstormy16-*-*) ;;
+ xtensa-*-*) ;;
z8k-*-*) ;;
*) AC_DEFINE(MISSING_SYSCALL_NAMES, 1, [Missing syscall names]) ;;
esac
diff --git a/libgloss/xtensa/Makefile.inc b/libgloss/xtensa/Makefile.inc
new file mode 100644
index 000000000..8761f3eb0
--- /dev/null
+++ b/libgloss/xtensa/Makefile.inc
@@ -0,0 +1,55 @@
+CPPFLAGS += -D_LIBGLOSS -I$(srcdir)/%D%/include
+
+multilibtool_DATA += \
+ %D%/default.specs \
+ %D%/nano.specs \
+ %D%/crt0.o
+
+multilibtool_LIBRARIES += %D%/libgloss.a
+
+if HAVE_XTENSA_BOARD_ESP
+multilibtool_DATA += \
+ %D%/sim.elf.specs \
+ %D%/board.elf.specs \
+ %D%/sys.qemu.specs \
+ %D%/sys.openocd.specs \
+ %D%/app.elf.ld \
+ %D%/crt1-sim.o \
+ %D%/crt1-boards.o
+
+%C%_libgloss_a_SOURCES = \
+ %D%/sleep.S \
+ %D%/syscalls.c \
+ %D%/window-vectors.S
+
+multilibtool_LIBRARIES += %D%/libsys_qemu.a
+%C%_libsys_qemu_a_CPPFLAGS = -DQEMU_SEMIHOSTING
+%C%_libsys_qemu_a_SOURCES = \
+ %D%/sim-vectors.S \
+ %D%/sim-call.S \
+ %D%/syscalls.c
+
+multilibtool_LIBRARIES += %D%/libsys_openocd.a
+%C%_libsys_openocd_a_CPPFLAGS = -DOPENOCD_SEMIHOSTING
+%C%_libsys_openocd_a_SOURCES = \
+ %D%/syscalls.c
+
+if HAVE_XTENSA_BOARD_ESP32
+multilibtool_DATA += %D%/boards/esp32/memory.elf.ld
+%C%_libgloss_a_SOURCES += %D%/boards/esp32/board.c
+%C%_libgloss_a_CPPFLAGS = -I$(srcdir)/%D%/boards/esp32/include
+%C%_libsys_qemu_a_CPPFLAGS += -I$(srcdir)/%D%/boards/esp32/include
+%C%_libsys_openocd_a_CPPFLAGS += -I$(srcdir)/%D%/boards/esp32/include
+endif
+
+if HAVE_XTENSA_BOARD_ESP32S3
+multilibtool_DATA += %D%/boards/esp32s3/memory.elf.ld
+%C%_libgloss_a_SOURCES += %D%/boards/esp32s3/board.c
+%C%_libgloss_a_CPPFLAGS = -I$(srcdir)/%D%/boards/esp32s3/include
+%C%_libsys_qemu_a_CPPFLAGS += -I$(srcdir)/%D%/boards/esp32s3/include
+%C%_libsys_openocd_a_CPPFLAGS += -I$(srcdir)/%D%/boards/esp32s3/include
+endif
+endif
+
+%D%/crt0.$(OBJEXT): %D%/crt0.S
+ $(AM_V_CPPAS)$(CPPASCOMPILE) $(CPPFLAGS) -o $@ -c $<
diff --git a/libgloss/xtensa/acinclude.m4 b/libgloss/xtensa/acinclude.m4
new file mode 100644
index 000000000..fc98f8a3d
--- /dev/null
+++ b/libgloss/xtensa/acinclude.m4
@@ -0,0 +1,5 @@
+XTENSA_BOARD_ESP=`echo $CC | sed 's/.*-mdynconfig=xtensa_\(.*\)\.so.*/\1/;s/.*-mcpu=\(^ *\).*/\1/;s/.* .*/unknown/'`
+AC_SUBST([XTENSA_BOARD_ESP])
+AM_CONDITIONAL([HAVE_XTENSA_BOARD_ESP32], [test x$XTENSA_BOARD_ESP = xesp32])
+AM_CONDITIONAL([HAVE_XTENSA_BOARD_ESP32S3], [test x$XTENSA_BOARD_ESP = xesp32s3])
+AM_CONDITIONAL([HAVE_XTENSA_BOARD_ESP], [echo $XTENSA_BOARD_ESP | grep -w -e esp32 -e esp32s3 >/dev/null 2>&1])
diff --git a/libgloss/xtensa/app.elf.ld b/libgloss/xtensa/app.elf.ld
new file mode 100644
index 000000000..12c7eb8ab
--- /dev/null
+++ b/libgloss/xtensa/app.elf.ld
@@ -0,0 +1,190 @@
+__stack = ORIGIN(dram_seg) + LENGTH(dram_seg);
+__MIN_STACK_SIZE = 0x1000;
+
+ENTRY(_start)
+SECTIONS
+{
+ . = SEGMENT_START("iram_seg", 0);
+ .vectors :
+ {
+ _vector_table = ABSOLUTE(.);
+ . = 0x0;
+ KEEP(*(.WindowVectors.text));
+ . = 0x180;
+ KEEP(*(.Level2InterruptVector.text));
+ . = 0x1c0;
+ KEEP(*(.Level3InterruptVector.text));
+ . = 0x200;
+ KEEP(*(.Level4InterruptVector.text));
+ . = 0x240;
+ KEEP(*(.Level5InterruptVector.text));
+ . = 0x280;
+ KEEP(*(.DebugExceptionVector.text));
+ . = 0x2c0;
+ KEEP(*(.NMIExceptionVector.text));
+ . = 0x300;
+ KEEP(*(.KernelExceptionVector.text));
+ . = 0x340;
+ KEEP(*(.UserExceptionVector.text));
+ . = 0x3C0;
+ KEEP(*(.DoubleExceptionVector.text));
+ . = 0x400;
+ KEEP(*(.ResetVector.text));
+ *(.*Vector.literal)
+ . = ALIGN (16);
+ } > iram_seg
+
+ text :
+ {
+ KEEP (*(.init.literal))
+ KEEP (*(SORT_NONE(.init)))
+ *(.literal .text .stub .literal.* .text.* .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ KEEP (*(.fini.literal))
+ KEEP (*(SORT_NONE(.fini)))
+ } > iram_seg
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ /* Adjust the address for the data segment. We want to adjust up to
+ the same address within the page on the next page up. */
+ . = ALIGN (CONSTANT (MAXPAGESIZE)) - ((CONSTANT (MAXPAGESIZE) - .) & (CONSTANT (MAXPAGESIZE) - 1)); . = DATA_SEGMENT_ALIGN (CONSTANT (MAXPAGESIZE), CONSTANT (COMMONPAGESIZE));
+
+ .rodata :
+ {
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.rodata1)
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+ *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
+ }
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ }
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ }
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ }
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ }
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ }
+
+ _data_start = .;
+ .data :
+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ SORT(CONSTRUCTORS)
+ *(.data1)
+ }
+ _edata = .; PROVIDE (edata = .);
+ . = .;
+ __bss_start = .;
+ .bss :
+ {
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections.
+ FIXME: Why do we need it? When there is no .bss section, we do not
+ pad the .data section. */
+ . = ALIGN(. != 0 ? 32 / 8 : 1);
+ }
+ . = ALIGN(32 / 8);
+ . = ALIGN(32 / 8);
+ _end = .; PROVIDE (end = .);
+ . = DATA_SEGMENT_END (.);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(. <= __stack - __MIN_STACK_SIZE, "region DRAM overflowed by .data and .bss sections")
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .debug_addr 0 : { *(.debug_addr) }
+ .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
+
diff --git a/libgloss/xtensa/board.elf.specs b/libgloss/xtensa/board.elf.specs
new file mode 100644
index 000000000..87cff19e7
--- /dev/null
+++ b/libgloss/xtensa/board.elf.specs
@@ -0,0 +1,5 @@
+*startfile:
+crt1-boards%O%s
+
+*lib:
+-lc --whole-archive -lgloss --no-whole-archive -lpthread_stubs -lc %Tmemory.elf.ld %Tapp.elf.ld
diff --git a/libgloss/xtensa/boards/esp32/board.c b/libgloss/xtensa/boards/esp32/board.c
new file mode 100644
index 000000000..905bf171e
--- /dev/null
+++ b/libgloss/xtensa/boards/esp32/board.c
@@ -0,0 +1,19 @@
+#include <stdint.h>
+#include <soc/uart.h>
+
+void board_init(void)
+{
+ WRITE_REGISTER(UART0_CLKDIV_REG, UART0_CLKDIV_VAL);
+}
+
+void board_uart_write_char(char c)
+{
+ /* wait until txfifo_cnt == 0 */
+ while (UART0_TXFIFO_CNT) {
+ ;
+ }
+ if (c == '\n') {
+ WRITE_REGISTER(UART0_TX_ADDR, '\r');
+ }
+ WRITE_REGISTER(UART0_TX_ADDR, c);
+}
diff --git a/libgloss/xtensa/boards/esp32/include/soc/cpu.h b/libgloss/xtensa/boards/esp32/include/soc/cpu.h
new file mode 100644
index 000000000..d570d3502
--- /dev/null
+++ b/libgloss/xtensa/boards/esp32/include/soc/cpu.h
@@ -0,0 +1,11 @@
+#ifndef SOC_CPU_H
+#define SOC_CPU_H
+
+/*
+ * ESP32 starts with CPU frequency 40MHz
+ * Let's do not reconfigure it to simplify libgloss
+ */
+#define CPU_FREQUENCY_MHZ 40
+#define CPU_FREQUENCY_HZ (CPU_FREQUENCY_MHZ * 1000000)
+
+#endif // SOC_CPU_H
diff --git a/libgloss/xtensa/boards/esp32/include/soc/uart.h b/libgloss/xtensa/boards/esp32/include/soc/uart.h
new file mode 100644
index 000000000..c5f1dc28a
--- /dev/null
+++ b/libgloss/xtensa/boards/esp32/include/soc/uart.h
@@ -0,0 +1,19 @@
+#ifndef SOC_UART_H
+#define SOC_UART_H
+
+#include <soc/cpu.h>
+#include <register_access.h>
+
+#define UART0_BAUDRATE 115200
+
+#define UART0_TX_ADDR 0x60000000
+#define UART0_BASE 0x3ff40000
+#define UART0_CLKDIV_REG (UART0_BASE + 0x14)
+#define UART0_STATUS (UART0_BASE + 0x1c)
+#define UART0_CLKDIV_VAL (CPU_FREQUENCY_HZ / UART0_BAUDRATE )
+#define UART0_TXFIFO_CNT (((READ_REGISTER(UART0_STATUS)) >> 16) & 0xff)
+
+
+void board_uart_write_char(char c);
+
+#endif // SOC_UART_H
diff --git a/libgloss/xtensa/boards/esp32/memory.elf.ld b/libgloss/xtensa/boards/esp32/memory.elf.ld
new file mode 100644
index 000000000..fa0e423b5
--- /dev/null
+++ b/libgloss/xtensa/boards/esp32/memory.elf.ld
@@ -0,0 +1,26 @@
+/*
+ * IROM/DRAM definition in QEMU:
+ * [ESP32_MEMREGION_IROM] = { 0x40000000, 0x70000 },
+ * [ESP32_MEMREGION_DRAM] = { 0x3ffae000, 0x52000 },
+ *
+ * In theory we could use whole DRAM section, but I had some faults when using
+ * memory in range 0x3ffae000 - 0x3ffb0000
+ *
+ * But used memory range for data such as esp-idf for ESP32 to satisfy user's
+ * expectation on chip emulation
+ *
+ * Pass '--defsym=entire_dram_seg=1' to linker script to use whole DRAM
+ *
+ */
+
+MEMORY
+{
+ iram_seg (X) : org = 0x40078000, len = 0x28000
+/* 64k at the end of DRAM, after ROM bootloader stack
+ * or entire DRAM (for QEMU only)
+ */
+ dram_seg (RW) : org = DEFINED(entire_dram_seg) ? 0x3FFB0000 : 0x3FFF0000,
+ len = DEFINED(entire_dram_seg) ? 0x50000 : 0x10000
+}
+
+
diff --git a/libgloss/xtensa/boards/esp32s3/board.c b/libgloss/xtensa/boards/esp32s3/board.c
new file mode 100644
index 000000000..905bf171e
--- /dev/null
+++ b/libgloss/xtensa/boards/esp32s3/board.c
@@ -0,0 +1,19 @@
+#include <stdint.h>
+#include <soc/uart.h>
+
+void board_init(void)
+{
+ WRITE_REGISTER(UART0_CLKDIV_REG, UART0_CLKDIV_VAL);
+}
+
+void board_uart_write_char(char c)
+{
+ /* wait until txfifo_cnt == 0 */
+ while (UART0_TXFIFO_CNT) {
+ ;
+ }
+ if (c == '\n') {
+ WRITE_REGISTER(UART0_TX_ADDR, '\r');
+ }
+ WRITE_REGISTER(UART0_TX_ADDR, c);
+}
diff --git a/libgloss/xtensa/boards/esp32s3/include/soc/cpu.h b/libgloss/xtensa/boards/esp32s3/include/soc/cpu.h
new file mode 100644
index 000000000..2a6793a8d
--- /dev/null
+++ b/libgloss/xtensa/boards/esp32s3/include/soc/cpu.h
@@ -0,0 +1,11 @@
+#ifndef SOC_CPU_H
+#define SOC_CPU_H
+
+/*
+ * ESP32S3 starts with CPU frequency 40MHz
+ * Let's do not reconfigure it to simplify libgloss
+ */
+#define CPU_FREQUENCY_MHZ 40
+#define CPU_FREQUENCY_HZ (CPU_FREQUENCY_MHZ * 1000000)
+
+#endif // SOC_CPU_H
diff --git a/libgloss/xtensa/boards/esp32s3/include/soc/uart.h b/libgloss/xtensa/boards/esp32s3/include/soc/uart.h
new file mode 100644
index 000000000..c32323a77
--- /dev/null
+++ b/libgloss/xtensa/boards/esp32s3/include/soc/uart.h
@@ -0,0 +1,19 @@
+#ifndef SOC_UART_H
+#define SOC_UART_H
+
+#include <soc/cpu.h>
+#include <register_access.h>
+
+#define UART0_BAUDRATE 115200
+
+#define UART0_TX_ADDR 0x60000000
+#define UART0_BASE 0x60000000
+#define UART0_CLKDIV_REG (UART0_BASE + 0x14)
+#define UART0_STATUS (UART0_BASE + 0x1c)
+#define UART0_CLKDIV_VAL (CPU_FREQUENCY_HZ / UART0_BAUDRATE )
+#define UART0_TXFIFO_CNT (((READ_REGISTER(UART0_STATUS)) >> 16) & 0x3ff)
+
+
+void board_uart_write_char(char c);
+
+#endif // SOC_UART_H
diff --git a/libgloss/xtensa/boards/esp32s3/memory.elf.ld b/libgloss/xtensa/boards/esp32s3/memory.elf.ld
new file mode 100644
index 000000000..6426b7fc6
--- /dev/null
+++ b/libgloss/xtensa/boards/esp32s3/memory.elf.ld
@@ -0,0 +1,21 @@
+/*
+ * IROM/DRAM definition in QEMU:
+ * [ESP32S3_MEMREGION_IROM] = { 0x40000000, 0x60000 },
+ * [ESP32S3_MEMREGION_DRAM] = { 0x3FC80000, 0x70000 },
+ *
+ * In theory we could use whole DRAM section, but I had some faults when using
+ * memory in range 0x3ffae000 - 0x3ffb0000
+ *
+ * But used memory range for data such as esp-idf for ESP32S3 to satisfy user's
+ * expectation on chip emulation
+ *
+ * Pass '--defsym=entire_dram_seg=1' to linker script to use whole DRAM
+ *
+ */
+
+MEMORY
+{
+ iram_seg (X) : org = 0x40378000, len = 0x70000
+ dram_seg (RW) : org = DEFINED(entire_dram_seg) ? 0x3FC80000 : 0x3FCF0000,
+ len = DEFINED(entire_dram_seg) ? 0x70000 : 0x10000
+}
diff --git a/libgloss/xtensa/crt0.S b/libgloss/xtensa/crt0.S
new file mode 100644
index 000000000..de4bb0719
--- /dev/null
+++ b/libgloss/xtensa/crt0.S
@@ -0,0 +1,14 @@
+// crt0.S
+// Dummy startup file which calls main() function.
+// It can be used for compilation tests only.
+
+ .text
+
+ /*
+ * Simple jump to main().
+ */
+
+ .global _start
+ _start:
+ movi a4, main
+ jx a4 // jump to main
diff --git a/libgloss/xtensa/crt1-boards.S b/libgloss/xtensa/crt1-boards.S
new file mode 100644
index 000000000..65ab7b45a
--- /dev/null
+++ b/libgloss/xtensa/crt1-boards.S
@@ -0,0 +1,226 @@
+// crt1-boards.S
+//
+// For most hardware / boards, this code sets up the C calling context
+// (setting up stack, PS, and clearing BSS) and jumps to __clibrary_start
+// which sets up the C library, calls constructors and registers destructors,
+// and calls main().
+//
+// Control arrives here at _start from the reset vector or from crt0-app.S.
+
+// Copyright (c) 1998-2013 Tensilica Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+#include <xtensa/corebits.h>
+
+
+// Exports
+.global _start
+
+// Imports
+// __clibrary_init from C library (eg. newlib or uclibc)
+// exit from C library
+// main from user application
+// board_init board-specific (uart/mingloss/tinygloss.c)
+// xthal_dcache_all_writeback from HAL library
+// __stack from linker script (see LSP Ref Manual)
+// __bss_start from linker script (see LSP Ref Manual)
+// _end from linker script (see LSP Ref Manual)
+
+.type main, @function
+
+# define CALL call4
+# define CALLX callx4
+# define ARG1 a6 /* 1st outgoing call argument */
+# define ARG2 a7 /* 2nd outgoing call argument */
+# define ARG3 a8 /* 3rd outgoing call argument */
+# define ARG4 a9 /* 4th outgoing call argument */
+# define ARG5 a10 /* 5th outgoing call argument */
+
+
+/**************************************************************************/
+
+ .text
+ .align 4
+_start:
+ // _start is typically NOT at the beginning of the text segment --
+ // it is always called from either the reset vector or other code
+ // that does equivalent initialization (such as crt0-app.S).
+ //
+ // Assumptions on entry to _start:
+ // - low (level-one) and medium priority interrupts are disabled
+ // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to
+ // be zeroed, to potentially enable them, before calling main)
+ // - C calling context not initialized:
+ // - PS not initialized
+ // - SP not initialized
+ // - the following are initialized:
+ // - LITBASE, cache attributes, WindowBase, WindowStart,
+ // CPENABLE, FP's FCR and FSR, EXCSAVE[n]
+
+ // Keep a0 zero. It is used to initialize a few things.
+ // It is also the return address, where zero indicates
+ // that the frame used by _start is the bottommost frame.
+ //
+
+ movi a0, 0 // keep this register zero.
+
+ wsr a0, INTENABLE // INTENABLE value is not defined after reset.
+ //make sure that interrupts are shut off (*before* we lower PS.INTLEVEL and PS.EXCM!)
+
+ // Windowed register init, so we can call windowed code (eg. C code).
+ movi a1, 1
+ wsr a1, WINDOWSTART
+ // The processor always clears WINDOWBASE at reset, so no need to clear it here.
+ // It resets WINDOWSTART to 1 starting with LX2.0/X7.0 (RB-2006.0).
+ // However, assuming hard reset is not yet always practical, so do this anyway:
+ wsr a0, WINDOWBASE
+ rsync
+
+ // Set VECBASE to use our vectors instead vectors in ROM
+ movi a1, _vector_table
+ wsr a1, VECBASE
+
+ // Initialize the stack pointer.
+ // See the "ABI and Software Conventions" chapter in the
+ // Xtensa ISA Reference manual for details.
+
+ // NOTE: Because the _start routine does not use any memory in its
+ // stack frame, and because all of its CALL instructions use a
+ // window size of 4 (or zero), the stack frame for _start can be empty.
+
+ movi sp, __stack
+
+ /*
+ * Now that sp (a1) is set, we can set PS as per the application
+ * (user vector mode, enable interrupts, enable window exceptions if applicable).
+ */
+ movi a3, PS_UM|PS_WOE
+ wsr a3, PS
+ rsync
+
+
+ /*
+ * Do any initialization that affects the memory map, such as
+ * setting up TLB entries, that needs to be done before we can
+ * successfully clear BSS (e.g. if some BSS segments are in
+ * remapped areas).
+ *
+ * NOTE: This hook works where the reset vector does not unpack
+ * segments (see "ROM packing" in the LSP manual), or where
+ * unpacking of segments is not affected by memory remapping.
+ * If ROM unpacking is affected, TLB setup must be done in
+ * assembler from the reset vector.
+ *
+ * The __memmap_init() routine can be a C function, however it
+ * does not have BSS initialized! In particular, __memmap_init()
+ * cannot set BSS variables, i.e. uninitialized global variables
+ * (they'll be wiped out by the following BSS clear), nor can it
+ * assume they are yet initialized to zero.
+ *
+ * The __memmap_init() function is optional. It is marked as a
+ * weak symbol, so that it gets valued zero if not defined.
+ */
+ .weak __memmap_init
+ movi a4, __memmap_init
+ beqz a4, 1f
+ CALLX a4
+1:
+
+ /*
+ * Clear the BSS (uninitialized data) segments.
+ * This code supports multiple zeroed sections (*.bss).
+ *
+ */
+ movi a6, __bss_start
+ movi a8, _end
+ sub a8, a8, a6
+ movi a7, 0
+ CALL memset
+
+ /* need to init reent_s before entering exit */
+ CALL __initreent
+
+ /* init semihosting if has function */
+ .weak __semihosting_init
+ movi a4, __semihosting_init
+ beqz a4, 2f
+ CALLX a4
+2:
+
+ // We can now call C code, the C calling environment has been initialized.
+ //
+ // From this point on, we use ABI-specific macros to refer to registers a0 .. a15
+ // (ARG#).
+
+
+ .type board_init, @function
+ .type __clibrary_init, @function
+ .type exit, @function
+
+
+ // Initialize the board (eg. UART, etc).
+ CALL board_init
+
+ /*
+ * Call __clibrary_init to initialize the C library:
+ *
+ * void __clibrary_init(int argc, char ** argv, char ** environ,
+ * void(*init_func)(void), void(*fini_func)(void));
+ */
+
+ // Pass an empty argv array, with an empty string as the program name.
+
+ .weak _init
+ .weak _fini
+ movi ARG1, _start_argc // argc address
+ movi ARG2, _start_argv // argv = ["", 0]
+ movi ARG3, _start_envp // envp = [0]
+ movi ARG4, _init // function that calls constructors
+ movi ARG5, _fini // function that calls destructors
+ l32i ARG1, ARG1, 0 // argc = 1
+ CALL __clibrary_init
+
+ // Call: int main(int argc, char ** argv, char ** environ);
+ movi ARG1, _start_argc // argc address
+ movi ARG2, _start_argv // argv = ["", 0]
+ movi ARG3, _start_envp // envp = [0]
+ l32i ARG1, ARG1, 0 // argc = 1
+ CALL main
+ // The return value is the same register as the first outgoing argument.
+ CALL exit // exit with main's return value
+ // Does not return here.
+
+ .data
+ // Mark argc/argv/envp parameters as weak so that an external
+ // object file can override them.
+ .weak _start_argc, _start_argv, _start_envp
+ .align 4
+_start_argv:
+ .word _start_null // empty program name
+_start_null:
+_start_envp:
+ .word 0 // end of argv array, empty string, empty environ
+_start_argc:
+ .word 1 // one argument (program name)
+ .text
+
+ .size _start, . - _start
+
diff --git a/libgloss/xtensa/crt1-sim.S b/libgloss/xtensa/crt1-sim.S
new file mode 100644
index 000000000..b9433f020
--- /dev/null
+++ b/libgloss/xtensa/crt1-sim.S
@@ -0,0 +1,204 @@
+// crt1-sim.S
+// For the Xtensa simulator target, this code sets up the C calling context
+// and calls main() (via __clibrary_start).
+// Control arrives here at _start from the reset vector or from crt0-app.S.
+
+// Copyright (c) 1998-2012 Tensilica Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+#include <xtensa/config/core-isa.h>
+#include <xtensa/corebits.h>
+#include <syscalls.h>
+
+// Exports
+.global _start
+
+// Imports
+// __clibrary_init from C library (eg. newlib or uclibc)
+// exit from C library
+// main from user application
+// __stack from linker script (see LSP Ref Manual)
+
+.type __clibrary_init, @function
+.type main, @function
+.type exit, @function
+
+# define CALL call4
+# define CALLX callx4
+# define ARG1 a6 /* 1st outgoing call argument */
+# define ARG2 a7 /* 2nd outgoing call argument */
+# define ARG3 a8 /* 3rd outgoing call argument */
+# define ARG4 a9 /* 4th outgoing call argument */
+# define ARG5 a10 /* 5th outgoing call argument */
+
+ .data
+ .weak _start_envp // allow overriding
+ .align 4
+_start_envp: .word 0 // empty environ
+
+ .text
+ .align 4
+
+_start:
+ // _start is typically NOT at the beginning of the text segment --
+ // it is always called from either the reset vector or other code
+ // that does equivalent initialization (such as crt0-app.S).
+ //
+ // Assumptions on entry to _start:
+ // - low (level-one) and medium priority interrupts are disabled
+ // via PS.INTLEVEL and/or INTENABLE (PS.INTLEVEL is expected to
+ // be zeroed, to potentially enable them, before calling main)
+ // - C calling context not initialized:
+ // - PS not initialized
+ // - SP not initialized
+ // - the following are initialized:
+ // - LITBASE, cache attributes, WindowBase, WindowStart,
+ // CPENABLE, FP's FCR and FSR, EXCSAVE[n]
+
+ // Keep a0 zero. It is used to initialize a few things.
+ // It is also the return address, where zero indicates
+ // that the frame used by _start is the bottommost frame.
+ //
+ movi a0, 0 // keep this register zero.
+
+ wsr a0, INTENABLE // INTENABLE value is not defined after reset.
+ //make sure that interrupts are shut off (*before* we lower PS.INTLEVEL and PS.EXCM!)
+
+ // Windowed register init, so we can call windowed code (eg. C code).
+ movi a1, 1
+ wsr a1, WINDOWSTART
+ // The processor always clears WINDOWBASE at reset, so no need to clear it here.
+ // It resets WINDOWSTART to 1 starting with LX2.0/X7.0 (RB-2006.0).
+ // However, assuming hard reset is not yet always practical, so do this anyway:
+ wsr a0, WINDOWBASE
+ rsync
+
+ // Set VECBASE to use our vectors instead vectors in ROM
+ movi a1, _vector_table
+ wsr a1, VECBASE
+
+
+ // Run only one core
+ // Multi-threading could be supported in future
+ rsr.prid a1 // core and multiprocessor ID
+ extui a1, a1, 13, 1 // extract core ID
+ beqz a1, .Lcore0 // goto Lcore0 for core0 only
+.Lsuspend: // other cores are suspended
+ waiti 0
+ j .Lsuspend
+
+.Lcore0:
+ // Initialize the stack pointer.
+ // See the "ABI and Software Conventions" chapter in the
+ // Xtensa ISA Reference manual for details.
+
+ // NOTE: Because the _start routine does not use any memory in its
+ // stack frame, and because all of its CALL instructions use a
+ // window size of 4, the stack frame for _start can be empty.
+ movi sp, __stack
+
+ // reserve stack space for
+ // - argv array
+ // - argument strings
+ movi a2, SYS_argv_size
+ simcall // returns size of argv[] + its strings in a2
+
+ // The stack only needs 16-byte alignment.
+ // However, here we round up the argv size further to 128 byte multiples
+ // so that in most cases, variations in argv[0]'s path do not result in
+ // different stack allocation. Otherwise, such variations can impact
+ // execution timing (eg. due to cache effects etc) for the same code and data.
+ // If we have a PIF, it's more likely the extra required space is okay.
+ addi a2, a2, 127
+ srli a2, a2, 7
+ slli a2, a2, 7
+
+ // No need to use MOVSP because we have no caller (we're the
+ // base caller); in fact it's better not to use MOVSP in this
+ // context, to avoid unnecessary ALLOCA exceptions and copying
+ // from undefined memory:
+ // sub a3, sp, a2
+ // movsp sp, a3
+ sub sp, sp, a2
+
+ /*
+ * Now that sp (a1) is set, we can set PS as per the application
+ * (user vector mode, enable interrupts, enable window exceptions if applicable).
+ */
+ movi a3, PS_UM|PS_WOE // PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0
+ wsr a3, PS
+ rsync
+
+ #if XCHAL_HAVE_FP || XCHAL_HAVE_DFP
+ movi a3, 1
+ wsr a3, CPENABLE
+ #endif
+
+1:
+
+ /*
+ * Clear the BSS (uninitialized data) segments.
+ * This code supports multiple zeroed sections (*.bss).
+ * For speed, we clear memory using an ISS simcall
+ * (see crt1-boards.S for more generic BSS clearing code).
+ */
+ movi a6, __bss_start
+ movi a7, _end
+ bgeu a6, a7, .Lnobss
+.Lbssloop:
+ movi a2, SYS_memset
+ l32i a3, a6, 0 // arg1 = fill start address
+ movi a4, 0 // arg2 = fill pattern
+ l32i a5, a6, 4 // get end address
+ addi a6, a6, 8 // next bss table entry
+ sub a5, a5, a3 // arg3 = fill size in bytes
+ simcall // memset(a3,a4,a5)
+ bltu a6, a7, .Lbssloop // loop until end of bss table
+.Lnobss:
+
+ /* need to init reent_s before entering exit */
+ CALL __initreent
+
+ mov a3, sp // tell simcall where to write argv[]
+ movi a2, SYS_argv
+ simcall // write argv[] array at a3
+
+ movi a2, SYS_argc
+ simcall // put argc in a2
+
+ .weak _init
+ .weak _fini
+ mov ARG2, sp // argv
+ movi ARG3, _start_envp // envp
+ movi ARG4, _init // _init
+ movi ARG5, _fini // _fini
+ CALL __clibrary_init
+
+ mov ARG1, a2 // argc
+ mov ARG2, sp // argv
+ CALL main
+
+ // The return value is the same register as the first outgoing argument.
+ CALL exit // exit with main's return value
+ // Does not return here.
+
+ .size _start, . - _start
+
diff --git a/libgloss/xtensa/default.specs b/libgloss/xtensa/default.specs
new file mode 100644
index 000000000..6002fe450
--- /dev/null
+++ b/libgloss/xtensa/default.specs
@@ -0,0 +1,2 @@
+*lib:
+-lc -lnosys -lc
diff --git a/libgloss/xtensa/include/register_access.h b/libgloss/xtensa/include/register_access.h
new file mode 100644
index 000000000..cc060618e
--- /dev/null
+++ b/libgloss/xtensa/include/register_access.h
@@ -0,0 +1,7 @@
+#ifndef REGISTER_ACCESS_H
+#define REGISTER_ACCESS_H
+
+#define WRITE_REGISTER(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
+#define READ_REGISTER(addr) (*((volatile uint32_t *)(addr)))
+
+#endif // REGISTER_ACCESS_H
diff --git a/libgloss/xtensa/include/syscalls.h b/libgloss/xtensa/include/syscalls.h
new file mode 100644
index 000000000..dd297d96e
--- /dev/null
+++ b/libgloss/xtensa/include/syscalls.h
@@ -0,0 +1,59 @@
+#ifndef XTENSA_SIMCALL_H
+#define XTENSA_SIMCALL_H
+
+#ifdef OPENOCD_SEMIHOSTING
+/* This data based on libgloss project (file aarch64/svc.h) */
+
+#define ESP_SEMIHOSTING_SYS_DRV_INFO 0x100
+#define ADP_STOPPED_APPLICATION_EXIT 0x20026
+
+#define SYS_close 0x02
+#define SYS_clock 0x10
+#define SYS_elapsed 0x30
+#define SYS_errno 0x13
+#define SYS_exit 0x18
+#define SYS_exit_extended 0x20
+#define SYS_flen 0x0C
+#define SYS_get_cmdline 0x15
+#define SYS_heapinfo 0x16
+#define SYS_iserror 0x08
+#define SYS_istty 0x09
+#define SYS_open 0x01
+#define SYS_read 0x06
+#define SYS_readc 0x07
+#define SYS_remove 0x0E
+#define SYS_rename 0x0F
+#define SYS_lseek 0x0A
+#define SYS_system 0x12
+#define SYS_tickfreq 0x31
+#define SYS_time 0x11
+#define SYS_tmpnam 0x0D
+#define SYS_write 0x05
+#define SYS_writec 0x03
+#define SYS_write0 0x04
+
+#else
+
+/* This data based on QEMU project (file target/xtensa/xtensa-semi.c) */
+
+#define SYS_exit 1
+#define SYS_read 3
+#define SYS_write 4
+#define SYS_open 5
+#define SYS_close 6
+#define SYS_lseek 19
+#define SYS_select_one 29
+#define SYS_sendto 27
+#define SYS_recvfrom 28
+#define SYS_select_one 29
+#define SYS_bind 30
+#define SYS_ioctl 31
+
+#define SYS_argc 1000
+#define SYS_argv_size 1001
+#define SYS_argv 1002
+#define SYS_memset 1004
+
+#endif /* OPENOCD_SEMIHOSTING */
+
+#endif /* !XTENSA_SIMCALL_H */
diff --git a/libgloss/xtensa/include/xtensa/corebits.h b/libgloss/xtensa/include/xtensa/corebits.h
new file mode 100644
index 000000000..445e33495
--- /dev/null
+++ b/libgloss/xtensa/include/xtensa/corebits.h
@@ -0,0 +1,186 @@
+/*
+ * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
+ *
+ * (In previous releases, these were defined in specreg.h, a generated file.
+ * This file is not generated, ie. it is processor configuration independent.)
+ */
+
+/* $Id: //depot/rel/Eaglenest/Xtensa/OS/include/xtensa/corebits.h#2 $ */
+
+/*
+ * Copyright (c) 2005-2011 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_COREBITS_H
+#define XTENSA_COREBITS_H
+
+/* EXCCAUSE register fields: */
+#define EXCCAUSE_EXCCAUSE_SHIFT 0
+#define EXCCAUSE_EXCCAUSE_MASK 0x3F
+/* EXCCAUSE register values: */
+/*
+ * General Exception Causes
+ * (values of EXCCAUSE special register set by general exceptions,
+ * which vector to the user, kernel, or double-exception vectors).
+ */
+#define EXCCAUSE_ILLEGAL 0 /* Illegal Instruction */
+#define EXCCAUSE_SYSCALL 1 /* System Call (SYSCALL instruction) */
+#define EXCCAUSE_INSTR_ERROR 2 /* Instruction Fetch Error */
+# define EXCCAUSE_IFETCHERROR 2 /* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_LOAD_STORE_ERROR 3 /* Load Store Error */
+# define EXCCAUSE_LOADSTOREERROR 3 /* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_LEVEL1_INTERRUPT 4 /* Level 1 Interrupt */
+# define EXCCAUSE_LEVEL1INTERRUPT 4 /* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
+#define EXCCAUSE_DIVIDE_BY_ZERO 6 /* Integer Divide by Zero */
+#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
+#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
+#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
+/* Reserved 10..11 */
+#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
+#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
+#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
+#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
+#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
+#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
+#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
+/* Reserved 19 */ /* Size Restriction on IFetch (not implemented) */
+#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
+/* Reserved 21..23 */
+#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
+#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
+#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
+/* Reserved 27 */ /* Size Restriction on Load/Store (not implemented) */
+#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
+#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
+/* Reserved 30..31 */
+#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
+#define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
+#define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
+#define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
+#define EXCCAUSE_CP3_DISABLED 35 /* Access to Coprocessor 3 when disabled */
+#define EXCCAUSE_CP4_DISABLED 36 /* Access to Coprocessor 4 when disabled */
+#define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
+#define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
+#define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
+/* Reserved 40..63 */
+
+/* PS register fields: */
+#define PS_WOE_SHIFT 18
+#define PS_WOE_MASK 0x00040000
+#define PS_WOE PS_WOE_MASK
+#define PS_WOE_ABI PS_WOE_MASK
+#define PS_CALLINC_SHIFT 16
+#define PS_CALLINC_MASK 0x00030000
+#define PS_CALLINC(n) (((n)&3)<<PS_CALLINC_SHIFT) /* n = 0..3 */
+#define PS_OWB_SHIFT 8
+#define PS_OWB_MASK 0x00000F00
+#define PS_OWB(n) (((n)&15)<<PS_OWB_SHIFT) /* n = 0..15 (or 0..7) */
+#define PS_RING_SHIFT 6
+#define PS_RING_MASK 0x000000C0
+#define PS_RING(n) (((n)&3)<<PS_RING_SHIFT) /* n = 0..3 */
+#define PS_UM_SHIFT 5
+#define PS_UM_MASK 0x00000020
+#define PS_UM PS_UM_MASK
+#define PS_EXCM_SHIFT 4
+#define PS_EXCM_MASK 0x00000010
+#define PS_EXCM PS_EXCM_MASK
+#define PS_INTLEVEL_SHIFT 0
+#define PS_INTLEVEL_MASK 0x0000000F
+#define PS_INTLEVEL(n) ((n)&PS_INTLEVEL_MASK) /* n = 0..15 */
+/* Backward compatibility (deprecated): */
+#define PS_PROGSTACK_SHIFT PS_UM_SHIFT
+#define PS_PROGSTACK_MASK PS_UM_MASK
+#define PS_PROG_SHIFT PS_UM_SHIFT
+#define PS_PROG_MASK PS_UM_MASK
+#define PS_PROG PS_UM
+
+/* DBREAKCn register fields: */
+#define DBREAKC_MASK_SHIFT 0
+#define DBREAKC_MASK_MASK 0x0000003F
+#define DBREAKC_LOADBREAK_SHIFT 30
+#define DBREAKC_LOADBREAK_MASK 0x40000000
+#define DBREAKC_STOREBREAK_SHIFT 31
+#define DBREAKC_STOREBREAK_MASK 0x80000000
+
+/* DEBUGCAUSE register fields: */
+#define DEBUGCAUSE_DEBUGINT_SHIFT 5
+#define DEBUGCAUSE_DEBUGINT_MASK 0x20 /* debug interrupt */
+#define DEBUGCAUSE_BREAKN_SHIFT 4
+#define DEBUGCAUSE_BREAKN_MASK 0x10 /* BREAK.N instruction */
+#define DEBUGCAUSE_BREAK_SHIFT 3
+#define DEBUGCAUSE_BREAK_MASK 0x08 /* BREAK instruction */
+#define DEBUGCAUSE_DBREAK_SHIFT 2
+#define DEBUGCAUSE_DBREAK_MASK 0x04 /* DBREAK match */
+#define DEBUGCAUSE_IBREAK_SHIFT 1
+#define DEBUGCAUSE_IBREAK_MASK 0x02 /* IBREAK match */
+#define DEBUGCAUSE_ICOUNT_SHIFT 0
+#define DEBUGCAUSE_ICOUNT_MASK 0x01 /* ICOUNT would increment to zero */
+
+/* MESR register fields: */
+#define MESR_MEME 0x00000001 /* memory error */
+#define MESR_MEME_SHIFT 0
+#define MESR_DME 0x00000002 /* double memory error */
+#define MESR_DME_SHIFT 1
+#define MESR_RCE 0x00000010 /* recorded memory error */
+#define MESR_RCE_SHIFT 4
+#define MESR_LCE
+#define MESR_LCE_SHIFT ?
+#define MESR_LCE_L
+#define MESR_ERRENAB 0x00000100
+#define MESR_ERRENAB_SHIFT 8
+#define MESR_ERRTEST 0x00000200
+#define MESR_ERRTEST_SHIFT 9
+#define MESR_DATEXC 0x00000400
+#define MESR_DATEXC_SHIFT 10
+#define MESR_INSEXC 0x00000800
+#define MESR_INSEXC_SHIFT 11
+#define MESR_WAYNUM_SHIFT 16
+#define MESR_ACCTYPE_SHIFT 20
+#define MESR_MEMTYPE_SHIFT 24
+#define MESR_ERRTYPE_SHIFT 30
+
+/* MEMCTL register fields: */
+#define MEMCTL_SNOOP_EN_SHIFT 1
+#define MEMCTL_SNOOP_EN 0x02 /* enable snoop responses (default 0) */
+#define MEMCTL_L0IBUF_EN_SHIFT 0
+#define MEMCTL_L0IBUF_EN 0x01 /* enable loop instr. buffer (default 1) */
+#define MEMCTL_INV_EN_SHIFT 23
+#define MEMCTL_INV_EN 0x00800000 /* invalidate cache ways being increased */
+#define MEMCTL_DCWU_SHIFT 8
+#define MEMCTL_DCWU_BITS 5
+#define MEMCTL_DCWA_SHIFT 13
+#define MEMCTL_DCWA_BITS 5
+#define MEMCTL_ICWU_SHIFT 18
+#define MEMCTL_ICWU_BITS 5
+#define MEMCTL_DCWU_MASK 0x00001F00 /* Bits 8-12 dcache ways in use */
+#define MEMCTL_DCWA_MASK 0x0003E000 /* Bits 13-17 dcache ways allocatable */
+#define MEMCTL_ICWU_MASK 0x007C0000 /* Bits 18-22 icache ways in use */
+#define MEMCTL_DCWU_CLR_MASK ~(MEMCTL_DCWU_MASK)
+#define MEMCTL_DCWA_CLR_MASK ~(MEMCTL_DCWA_MASK)
+#define MEMCTL_ICWU_CLR_MASK ~(MEMCTL_ICWU_MASK)
+#define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
+#define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
+
+
+#endif /*XTENSA_COREBITS_H*/
+
diff --git a/libgloss/xtensa/nano.specs b/libgloss/xtensa/nano.specs
new file mode 100644
index 000000000..adf7abbaf
--- /dev/null
+++ b/libgloss/xtensa/nano.specs
@@ -0,0 +1,18 @@
+%rename link nano_link
+%rename link_gcc_c_sequence nano_link_gcc_c_sequence
+
+*nano_libc:
+-lc_nano
+
+*nano_libgloss:
+%{specs=nosys.specs:-lnosys}
+
+*link_gcc_c_sequence:
+%(nano_link_gcc_c_sequence) --start-group %G %(nano_libc) %(nano_libgloss) --end-group
+
+*link:
+%(nano_link) %:replace-outfile(-lc -lc_nano) %:replace-outfile(-lg -lg_nano) %:replace-outfile(-lm -lm_nano)
+
+*lib:
+%{!shared:%{g*:-lg_nano} %{!p:%{!pg:-lc_nano}}%{p:-lc_p}%{pg:-lc_p}}
+
diff --git a/libgloss/xtensa/sim-call.S b/libgloss/xtensa/sim-call.S
new file mode 100644
index 000000000..4b493c296
--- /dev/null
+++ b/libgloss/xtensa/sim-call.S
@@ -0,0 +1,8 @@
+
+ .type __sim_call, @function
+ .align 4
+ .global __sim_call
+__sim_call:
+ entry a1, 32
+ simcall
+ retw
diff --git a/libgloss/xtensa/sim-vectors.S b/libgloss/xtensa/sim-vectors.S
new file mode 100644
index 000000000..936753a6d
--- /dev/null
+++ b/libgloss/xtensa/sim-vectors.S
@@ -0,0 +1,163 @@
+#include <xtensa/config/core-isa.h>
+#include <syscalls.h>
+
+//#define PS_OWB_SHIFT 8
+//#define PS_OWB_BITS 4
+//#define EXCCAUSE_ALLOCA 5 /* Stack Extension Assist (MOVSP instruction) for alloca */
+
+#if XCHAL_HAVE_L32R
+ .section .rodata
+_sim_panic_msg:
+ .ascii "PANIC: Unhandled exception!\n"
+ _sim_panic_msg_len = . - _sim_panic_msg
+
+ .section .text
+ .literal .Lpanic_msg, _sim_panic_msg
+ .literal .Lpanic_msg_len, _sim_panic_msg_len
+ .align 4
+_xt_unhandled_exc:
+ movi a2, SYS_write
+ movi a3, 2
+ l32r a4, .Lpanic_msg
+ l32r a5, .Lpanic_msg_len
+ simcall
+#else
+_xt_unhandled_exc:
+#endif
+ movi a2, SYS_exit
+ movi a3, 1
+ simcall
+
+/*
+--------------------------------------------------------------------------------
+Handle alloca exception generated by interruptee executing 'movsp'.
+This uses space between the window vectors, so is essentially "free".
+All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
+and PS.EXCM has been set by the exception hardware (can't be interrupted).
+The fact the alloca exception was taken means the registers associated with
+the base-save area have been spilled and will be restored by the underflow
+handler, so those 4 registers are available for scratch.
+The code is optimized to avoid unaligned branches and minimize cache misses.
+--------------------------------------------------------------------------------
+*/
+
+ #if XCHAL_HAVE_WINDOWED
+ .section .text
+ .global _xt_alloca_exc
+ .align 4
+_xt_alloca_exc:
+
+ rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */
+ rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */
+ rsr a2, PS
+ extui a3, a2, 8/*PS_OWB_BITS*/, 4/*PS_OWB_BITS*/
+ xor a3, a3, a4 /* bits changed from old to current windowbase */
+ rsr a4, EXCSAVE1 /* restore original a0 (now in a4) */
+ slli a3, a3, 8
+ xor a2, a2, a3 /* flip changed bits in old window base */
+ wsr a2, PS /* update PS.OWB to new window base */
+ rsync
+
+ bbci.l a4, 31, _WindowUnderflow4
+ rotw -1 /* original a0 goes to a8 */
+ bbci.l a8, 30, _WindowUnderflow8
+ rotw -1
+ j _WindowUnderflow12
+ #endif
+
+
+/*
+--------------------------------------------------------------------------------
+ User exception handler.
+--------------------------------------------------------------------------------
+*/
+
+ #if XCHAL_HAVE_WINDOWED
+ .section .text
+ .align 4
+_xt_to_alloca_exc:
+ j _xt_alloca_exc /* in window vectors section */
+ #endif
+
+ .type _xt_user_exc,@function
+ .align 4
+_xt_user_exc:
+
+ rsr a0, EXCCAUSE
+ /* Handle alloca and syscall exceptions */
+ #if XCHAL_HAVE_WINDOWED
+ beqi a0, 5/*EXCCAUSE_ALLOCA*/, _xt_to_alloca_exc
+ #endif
+ j _xt_unhandled_exc
+
+
+/*
+--------------------------------------------------------------------------------
+NMI Exception
+--------------------------------------------------------------------------------
+*/
+
+ .begin literal_prefix .NMIExceptionVector
+ .section .NMIExceptionVector.text, "ax"
+ .global NMIExceptionVector
+ .type NMIExceptionVector,@function
+ .align 4
+
+NMIExceptionVector:
+ j _xt_unhandled_exc
+
+ .end literal_prefix
+
+/*
+--------------------------------------------------------------------------------
+Kernel Exception
+--------------------------------------------------------------------------------
+*/
+
+ .begin literal_prefix .KernelExceptionVector
+ .section .KernelExceptionVector.text, "ax"
+ .global KernelExceptionVector
+ .type KernelExceptionVector,@function
+ .align 4
+
+KernelExceptionVector:
+ j _xt_unhandled_exc
+
+ .end literal_prefix
+
+/*
+--------------------------------------------------------------------------------
+User Exception
+--------------------------------------------------------------------------------
+*/
+
+ .begin literal_prefix .UserExceptionVector
+ .section .UserExceptionVector.text, "ax"
+ .global _UserExceptionVector
+ .type _UserExceptionVector,@function
+ .align 4
+
+_UserExceptionVector:
+
+ wsr a0, EXCSAVE1 /* preserve a0 */
+ j _xt_user_exc /* user exception handler */
+ /* never returns here - call0 is used as a jump (see note at top) */
+
+ .end literal_prefix
+
+/*
+--------------------------------------------------------------------------------
+Double Exception
+--------------------------------------------------------------------------------
+*/
+
+ .begin literal_prefix .DoubleExceptionVector
+ .section .DoubleExceptionVector.text, "ax"
+ .global DoubleExceptionVector
+ .type DoubleExceptionVector,@function
+ .align 4
+
+DoubleExceptionVector:
+ j _xt_unhandled_exc
+
+ .end literal_prefix
diff --git a/libgloss/xtensa/sim.elf.specs b/libgloss/xtensa/sim.elf.specs
new file mode 100644
index 000000000..3024f6887
--- /dev/null
+++ b/libgloss/xtensa/sim.elf.specs
@@ -0,0 +1,5 @@
+*startfile:
+crt1-sim%O%s
+
+*lib:
+-lc --whole-archive -lgloss --no-whole-archive -lpthread_stubs -lc %Tmemory.elf.ld %Tapp.elf.ld
diff --git a/libgloss/xtensa/sleep.S b/libgloss/xtensa/sleep.S
new file mode 100644
index 000000000..413ce9288
--- /dev/null
+++ b/libgloss/xtensa/sleep.S
@@ -0,0 +1,64 @@
+#include <soc/cpu.h>
+
+#define USECONDS_IN_SECOND 1000000
+
+ .type sleep, @function
+ .align 4
+ .global sleep
+sleep:
+ entry a1, 0x30
+ mov.n a7, a1
+ s32i.n a2, a7, 0
+
+ mov a3, a2
+.Lsleep_delay_second:
+ addi a3, a3, -1
+ movi a10, USECONDS_IN_SECOND
+ call8 usleep
+ bnez a3, .Lsleep_delay_second
+
+.Lsleep_exit:
+ s32i.n a2, a7, 0
+ retw
+
+
+ .type usleep, @function
+ .align 4
+ .global usleep
+usleep:
+ entry a1, 0x30
+ mov.n a7, a1
+ s32i.n a2, a7, 0
+
+ /* convert time to CLOCK ticks per 1us */
+ movi a6, CPU_FREQUENCY_MHZ // CPU_FREQUENCY_MHZ == ticks per us
+ mull a2, a2, a6
+
+ /*
+ * Registers purpose:
+ * a3 - start CCOUNT value
+ * a4 - current CCOUNT value
+ * a5 - target CCOUNT value
+ */
+
+ rsr a3, CCOUNT
+ add a5, a3, a2
+ bgeu a5, a3, .Lusleep_waitloop
+
+.Lusleep_waitoverflow:
+ /* you are here because a5 (target CCOUNT) was overflown
+ * it means that we need to wait CCOUNT register overflow
+ * before do main loop
+ */
+ rsr a4, CCOUNT
+ bgeu a4, a3, .Lusleep_waitoverflow
+
+.Lusleep_waitloop:
+ /* wait until we reach target CCOUNT value */
+ rsr a4, CCOUNT
+ bgeu a4, a5, .Lusleep_exit
+ j .Lusleep_waitloop
+.Lusleep_exit:
+ s32i.n a2, a7, 0
+ retw
+
diff --git a/libgloss/xtensa/sys.openocd.specs b/libgloss/xtensa/sys.openocd.specs
new file mode 100644
index 000000000..457318424
--- /dev/null
+++ b/libgloss/xtensa/sys.openocd.specs
@@ -0,0 +1,8 @@
+%rename link_gcc_c_sequence openocd_link_gcc_c_sequence
+
+*libopenocd:
+--whole-archive -lsys_openocd --no-whole-archive
+
+*link_gcc_c_sequence:
+%(openocd_link_gcc_c_sequence) --start-group %G %(libopenocd) --end-group
+
diff --git a/libgloss/xtensa/sys.qemu.specs b/libgloss/xtensa/sys.qemu.specs
new file mode 100644
index 000000000..5185c0480
--- /dev/null
+++ b/libgloss/xtensa/sys.qemu.specs
@@ -0,0 +1,8 @@
+%rename link_gcc_c_sequence qemu_link_gcc_c_sequence
+
+*libqemu:
+--whole-archive -lsys_qemu --no-whole-archive
+
+*link_gcc_c_sequence:
+%(qemu_link_gcc_c_sequence) --start-group %G %(libqemu) --end-group
+
diff --git a/libgloss/xtensa/syscalls.c b/libgloss/xtensa/syscalls.c
new file mode 100644
index 000000000..0ccc7d44e
--- /dev/null
+++ b/libgloss/xtensa/syscalls.c
@@ -0,0 +1,210 @@
+#include <unistd.h>
+#include <syscalls.h>
+#include <sys/stat.h>
+#include <soc/uart.h>
+
+#if defined (OPENOCD_SEMIHOSTING) || (QEMU_SEMIHOSTING)
+# define WITH_SEMIHOSTING
+# define __WEAK_FUNCTION_ATTR__
+#else
+# define __WEAK_FUNCTION_ATTR__ __attribute__((__weak__))
+#endif
+
+
+/* __semihosting_call is a function in case semihosting usage, macro (-1) otherwise */
+#ifdef WITH_SEMIHOSTING
+
+static inline int
+__attribute__ ((always_inline))
+__semihosting_call(int id, int arg1, int arg2, int arg3, int arg4)
+{
+# ifdef OPENOCD_SEMIHOSTING
+ register long a2 asm("a2") = id;
+ long args[] = {arg1, arg2, arg3, arg4};
+ register long a3 asm("a3") = (long)&args;
+
+ /* OpenOCD has different semihosting api for sys_exit on 32-bit and 64-bit */
+ if (id == SYS_exit && sizeof(void *) != 8) {
+ a3 = ADP_STOPPED_APPLICATION_EXIT;
+ }
+ __asm__ __volatile__ (
+ "break 1, 14\n"
+ : "+r"(a2): "r"(a3)
+ : "memory");
+
+ // return code is placed in a2 register, so return it to the caller
+ return a2;
+# else // OPENOCD_SEMIHOSTING
+ extern int __sim_call(int id, int arg1, int arg2, int arg3, int arg4);
+ return __sim_call(id, arg1, arg2, arg3, arg4);
+# endif // OPENOCD_SEMIHOSTING
+}
+
+# ifdef OPENOCD_SEMIHOSTING
+
+int
+__semihosting_init (void)
+{
+ struct {
+ int version;
+ } ver_info = { 2 };
+ __semihosting_call(ESP_SEMIHOSTING_SYS_DRV_INFO, (long) &ver_info, sizeof(ver_info), 0, 0);
+}
+
+# endif // OPENOCD_SEMIHOSTING
+
+#else // !WITH_SEMIHOSTING
+# define __semihosting_call(...) (-1)
+#endif // WITH_SEMIHOSTING
+
+
+void
+__WEAK_FUNCTION_ATTR__
+__attribute__ ((noreturn))
+_exit (int status)
+{
+ __semihosting_call(SYS_exit, status, 0, 0, 0);
+
+ for (;;) {
+ ;
+ }
+}
+
+
+int
+__WEAK_FUNCTION_ATTR__
+_open (const char *file, int flags, int mode)
+{
+ return __semihosting_call(SYS_open, (int) file, flags, mode, 0);
+}
+
+
+int
+__WEAK_FUNCTION_ATTR__
+_lseek (int fd, _off_t off, int whence)
+{
+ return __semihosting_call(SYS_lseek, fd, off, whence, 0);
+}
+
+
+int
+__WEAK_FUNCTION_ATTR__
+_close (int fd)
+{
+ return __semihosting_call(SYS_close, fd, 0, 0, 0);
+}
+
+
+_ssize_t
+__WEAK_FUNCTION_ATTR__
+_write (int fd, const char *buf, size_t cnt)
+{
+ int ret = 0;
+#ifdef WITH_SEMIHOSTING
+ ret = __semihosting_call(SYS_write, fd, (int) buf, cnt, 0);
+# ifdef OPENOCD_SEMIHOSTING
+ /* ret - number of bytes that are NOT written. Calculate written */
+ ret = cnt - ret;
+# endif // OPENOCD_SEMIHOSTING
+#else // !WITH_SEMIHOSTING
+ if (fd != STDOUT_FILENO && fd != STDERR_FILENO) {
+ return -1;
+ }
+
+ for (uint32_t i = 0; i < cnt; i++) {
+ board_uart_write_char(buf[i]);
+ }
+ ret = cnt;
+#endif // WITH_SEMIHOSTING
+ return ret;
+}
+
+
+/* Do not compile functions with common implementation
+ * if building semihosting library
+ */
+#ifndef WITH_SEMIHOSTING
+
+static struct _reent s_reent;
+
+struct _reent*
+__WEAK_FUNCTION_ATTR__
+__initreent(void)
+{
+ _REENT_INIT_PTR(_GLOBAL_REENT);
+}
+
+
+struct _reent*
+__WEAK_FUNCTION_ATTR__
+__getreent(void)
+{
+ return _GLOBAL_REENT;
+}
+
+
+int
+__WEAK_FUNCTION_ATTR__
+_fstat (int fd, struct stat *pstat)
+{
+
+ if (fd < STDERR_FILENO)
+ {
+ pstat->st_mode = S_IFCHR;
+ return 0;
+ }
+ return -1;
+}
+
+
+_ssize_t
+__WEAK_FUNCTION_ATTR__
+_read (int fd, char *buf, size_t cnt)
+{
+ return -1;
+}
+
+
+int
+__WEAK_FUNCTION_ATTR__
+_getpid (void)
+{
+ return -1;
+}
+
+
+int
+__WEAK_FUNCTION_ATTR__
+_kill (int sig)
+{
+ return -1;
+}
+
+
+void *
+__WEAK_FUNCTION_ATTR__
+_sbrk (int incr)
+{
+ extern char end; /* Set by linker. */
+ static char * heap_end;
+ char * prev_heap_end;
+
+ if (heap_end == 0) {
+ heap_end = & end;
+ }
+
+ prev_heap_end = heap_end;
+ heap_end += incr;
+
+ return (void *) prev_heap_end;
+}
+
+
+int
+__WEAK_FUNCTION_ATTR__
+pthread_setcancelstate (int state, int *oldstate)
+{
+ return 0;
+}
+
+#endif // WITH_SEMIHOSTING
diff --git a/libgloss/xtensa/window-vectors.S b/libgloss/xtensa/window-vectors.S
new file mode 100644
index 000000000..acab8b355
--- /dev/null
+++ b/libgloss/xtensa/window-vectors.S
@@ -0,0 +1,252 @@
+// window-vectors-new.S - Register Window Overflow/Underflow Handlers for XEA2
+// $Id: //depot/rel/Eaglenest/Xtensa/OS/xtos/window-vectors-new.S#3 $
+
+// Copyright (c) 1999-2013 Tensilica Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+// Exports
+.global _WindowOverflow4
+.global _WindowUnderflow4
+.global _WindowOverflow8
+.global _WindowUnderflow8
+.global _WindowOverflow12
+.global _WindowUnderflow12
+
+ // Note: the current window exception vectors do not generate any
+ // literals. Hence the literal_prefix directive is not necessary.
+ // Specifying it "just in case" creates an empty section (named
+ // ".WindowVectors.literal") which can in some cases cause linking
+ // problems (the linker scripts don't place it anywhere).
+ // So leave it commented out:
+ //
+ //.begin literal_prefix .WindowVectors
+
+ .section .WindowVectors.text, "ax"
+
+//
+// GENERAL NOTES:
+//
+// These window exception handlers need not be modified.
+// They are specific to the windowed call ABI only.
+//
+// Underflow Handlers:
+//
+// The underflow handler for returning from call[i+1] to call[i]
+// must preserve all the registers from call[i+1]'s window.
+// In particular, a0 and a1 must be preserved because the RETW instruction
+// will be reexecuted (and may even underflow again if an intervening
+// exception has flushed call[i]'s registers).
+// Registers a2 and up may contain return values.
+//
+// The caller could also potentially assume that the callee's a0 and a1
+// (its own a4&a5 if call4, a8&a9 if call8, a12&a13 if call12)
+// are correct for whatever reason (not a clean thing to do in general,
+// but if it's possible, unless the ABI explicitly prohibits it,
+// it will eventually be done :) -- whether the the ABI needs to
+// prohibit this is a different question).
+//
+// Timing of Handlers:
+//
+// Here is an overview of the overhead of taking a window exception,
+// ie. the number of additional cycles taken relative to case where
+// an exception is not taken.
+// NOTE: these numbers do not take into account any cache misses,
+// write buffer stalls, or other external stalls, if they occur.
+// The totals consist of 5 cycles to enter the handler (or 6 or 7
+// for optional longer pipelines in Xtensa LX), the number of instructions
+// and interlocks (2nd and 3rd columns below), and 2 cycles jump delay
+// on return (3 cycles for optional longer I-side pipeline in Xtensa LX):
+//
+// Instruction+bubbles Totals (5-stage)
+// XEA1 XEA2 XEA1 XEA2
+// Overflow-4 7 5 14 12
+// Overflow-8 14 10 21 17
+// Overflow-12 18 14 25 21
+// Underflow-4 6 5 13 12
+// Underflow-8 14 10 21 17
+// Underflow-12 18 14 25 21
+//
+// Underflow-8 15 12 25 22 (7-stage; could be made 1 less)
+// Underflow-12 19 16 29 26 (7-stage; could be made 1 less)
+
+
+// 4-Register Window Overflow Vector (Handler)
+//
+// Invoked if a call[i] referenced a register (a4-a15)
+// that contains data from ancestor call[j];
+// call[j] had done a call4 to call[j+1].
+// On entry here:
+// window rotated to call[j] start point;
+// a0-a3 are registers to be saved;
+// a4-a15 must be preserved;
+// a5 is call[j+1]'s stack pointer.
+
+ .org 0x0
+_WindowOverflow4:
+ s32e a0, a5, -16 // save a0 to call[j+1]'s stack frame
+ s32e a1, a5, -12 // save a1 to call[j+1]'s stack frame
+ s32e a2, a5, -8 // save a2 to call[j+1]'s stack frame
+ s32e a3, a5, -4 // save a3 to call[j+1]'s stack frame
+ rfwo // rotates back to call[i] position
+
+ .size _WindowOverflow4, . - _WindowOverflow4
+
+
+// 4-Register Window Underflow Vector (Handler)
+//
+// Invoked by RETW returning from call[i+1] to call[i]
+// where call[i]'s registers must be reloaded (not live in ARs);
+// call[i] had done a call4 to call[i+1].
+// On entry here:
+// window rotated to call[i] start point;
+// a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
+// a4-a15 must be preserved (they are call[i+1].reg[0..11]);
+// a5 is call[i+1]'s stack pointer.
+
+ .org 0x40
+_WindowUnderflow4:
+ l32e a0, a5, -16 // restore a0 from call[i+1]'s stack frame
+ l32e a1, a5, -12 // restore a1 from call[i+1]'s stack frame
+ l32e a2, a5, -8 // restore a2 from call[i+1]'s stack frame
+ l32e a3, a5, -4 // restore a3 from call[i+1]'s stack frame
+ rfwu
+
+ .size _WindowUnderflow4, . - _WindowUnderflow4
+
+
+// 8-Register Window Overflow Vector (Handler)
+//
+// Invoked if a call[i] referenced a register (a4-a15)
+// that contains data from ancestor call[j];
+// call[j] had done a call8 to call[j+1].
+// On entry here:
+// window rotated to call[j] start point;
+// a0-a7 are registers to be saved;
+// a8-a15 must be preserved;
+// a9 is call[j+1]'s stack pointer.
+
+ .org 0x80
+_WindowOverflow8:
+ s32e a0, a9, -16 // save a0 to call[j+1]'s stack frame
+ l32e a0, a1, -12 // a0 <- call[j-1]'s sp (used to find end of call[j]'s frame)
+ s32e a1, a9, -12 // save a1 to call[j+1]'s stack frame
+ s32e a2, a9, -8 // save a2 to call[j+1]'s stack frame
+ s32e a3, a9, -4 // save a3 to call[j+1]'s stack frame
+ s32e a4, a0, -32 // save a4 to call[j]'s stack frame
+ s32e a5, a0, -28 // save a5 to call[j]'s stack frame
+ s32e a6, a0, -24 // save a6 to call[j]'s stack frame
+ s32e a7, a0, -20 // save a7 to call[j]'s stack frame
+ rfwo // rotates back to call[i] position
+
+ .size _WindowOverflow8, . - _WindowOverflow8
+
+
+// 8-Register Window Underflow Vector (Handler)
+//
+// Invoked by RETW returning from call[i+1] to call[i]
+// where call[i]'s registers must be reloaded (not live in ARs);
+// call[i] had done a call8 to call[i+1].
+// On entry here:
+// window rotated to call[i] start point;
+// a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
+// a8-a15 must be preserved (they are call[i+1].reg[0..7]);
+// a9 is call[i+1]'s stack pointer.
+
+ .org 0xC0
+_WindowUnderflow8:
+ l32e a0, a9, -16 // restore a0 from call[i+1]'s stack frame
+ l32e a1, a9, -12 // restore a1 from call[i+1]'s stack frame
+ l32e a2, a9, -8 // restore a2 from call[i+1]'s stack frame
+ l32e a7, a1, -12 // a7 <- call[i-1]'s sp (used to find end of call[i]'s frame)
+ l32e a3, a9, -4 // restore a3 from call[i+1]'s stack frame
+ l32e a4, a7, -32 // restore a4 from call[i]'s stack frame
+ l32e a5, a7, -28 // restore a5 from call[i]'s stack frame
+ l32e a6, a7, -24 // restore a6 from call[i]'s stack frame../../.././libgloss/xtensa/window-vectors.S
+ l32e a7, a7, -20 // restore a7 from call[i]'s stack frame
+ rfwu
+
+ .size _WindowUnderflow8, . - _WindowUnderflow8
+
+
+// 12-Register Window Overflow Vector (Handler)
+//
+// Invoked if a call[i] referenced a register (a4-a15)
+// that contains data from ancestor call[j];
+// call[j] had done a call12 to call[j+1].
+// On entry here:
+// window rotated to call[j] start point;
+// a0-a11 are registers to be saved;
+// a12-a15 must be preserved;
+// a13 is call[j+1]'s stack pointer.
+
+ .org 0x100
+_WindowOverflow12:
+ s32e a0, a13, -16 // save a0 to call[j+1]'s stack frame
+ l32e a0, a1, -12 // a0 <- call[j-1]'s sp (used to find end of call[j]'s frame)
+ s32e a1, a13, -12 // save a1 to call[j+1]'s stack frame
+ s32e a2, a13, -8 // save a2 to call[j+1]'s stack frame
+ s32e a3, a13, -4 // save a3 to call[j+1]'s stack frame
+ s32e a4, a0, -48 // save a4 to end of call[j]'s stack frame
+ s32e a5, a0, -44 // save a5 to end of call[j]'s stack frame
+ s32e a6, a0, -40 // save a6 to end of call[j]'s stack frame
+ s32e a7, a0, -36 // save a7 to end of call[j]'s stack frame
+ s32e a8, a0, -32 // save a8 to end of call[j]'s stack frame
+ s32e a9, a0, -28 // save a9 to end of call[j]'s stack frame
+ s32e a10, a0, -24 // save a10 to end of call[j]'s stack frame
+ s32e a11, a0, -20 // save a11 to end of call[j]'s stack frame
+ rfwo // rotates back to call[i] position
+
+ .size _WindowOverflow12, . - _WindowOverflow12
+
+
+// 12-Register Window Underflow Vector (Handler)
+//
+// Invoked by RETW returning from call[i+1] to call[i]
+// where call[i]'s registers must be reloaded (not live in ARs);
+// call[i] had done a call12 to call[i+1].
+// On entry here:
+// window rotated to call[i] start point;
+// a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
+// a12-a15 must be preserved (they are call[i+1].reg[0..3]);
+// a13 is call[i+1]'s stack pointer.
+
+ .org 0x140
+_WindowUnderflow12:
+ l32e a0, a13, -16 // restore a0 from call[i+1]'s stack frame
+ l32e a1, a13, -12 // restore a1 from call[i+1]'s stack frame
+ l32e a2, a13, -8 // restore a2 from call[i+1]'s stack frame
+ l32e a11, a1, -12 // a11 <- call[i-1]'s sp (used to find end of call[i]'s frame)
+ l32e a3, a13, -4 // restore a3 from call[i+1]'s stack frame
+ l32e a4, a11, -48 // restore a4 from end of call[i]'s stack frame
+ l32e a5, a11, -44 // restore a5 from end of call[i]'s stack frame
+ l32e a6, a11, -40 // restore a6 from end of call[i]'s stack frame
+ l32e a7, a11, -36 // restore a7 from end of call[i]'s stack frame
+ l32e a8, a11, -32 // restore a8 from end of call[i]'s stack frame
+ l32e a9, a11, -28 // restore a9 from end of call[i]'s stack frame
+ l32e a10, a11, -24 // restore a10 from end of call[i]'s stack frame
+ l32e a11, a11, -20 // restore a11 from end of call[i]'s stack frame
+ rfwu
+
+ .size _WindowUnderflow12, . - _WindowUnderflow12
+
+
+ //.end literal_prefix
+ .text
--
2.34.1
next prev parent reply other threads:[~2023-08-15 15:08 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-11 6:03 [PATCH, RFC 0/8] " Alexey Lapshin
2023-05-11 6:05 ` [PATCH, RFC 1/8] newlib: add system headers from include/$(sys_dir)/*/*.h Alexey Lapshin
2023-05-11 6:12 ` [PATCH, RFC 2/8] libc: sys: add xtensa port Alexey Lapshin
2023-05-11 6:18 ` [PATCH, RFC 3/8] libm: " Alexey Lapshin
2023-05-11 6:20 ` [PATCH, RFC 4/8] libc: " Alexey Lapshin
2023-05-11 6:21 ` [PATCH, RFC 5/8] libm: add attribute weak for __ieee754_sqrtf Alexey Lapshin
2023-05-11 6:22 ` [PATCH, RFC 6/8] libgloss: libnosys: add xtensa port Alexey Lapshin
2023-05-11 6:23 ` [PATCH, RFC 7/8] libgloss: " Alexey Lapshin
2023-05-11 6:25 ` [PATCH, RFC 8/8] libc: fix xtensa PSRAM cache bug Alexey Lapshin
2023-05-12 9:18 ` [PATCH, RFC 0/8] add xtensa port Max Filippov
2023-05-15 13:45 ` [PATCH, RFC v2 " Alexey Lapshin
2023-05-15 13:47 ` [PATCH, RFC v2 1/8] newlib: add system headers from include/$(sys_dir)/*/*.h Alexey Lapshin
2023-05-15 13:48 ` [PATCH, RFC v2 2/8] libc: sys: add xtensa port Alexey Lapshin
2023-05-15 13:49 ` [PATCH, RFC v2 3/8] libm: " Alexey Lapshin
2023-05-15 13:50 ` [PATCH, RFC v2 4/8] libc: " Alexey Lapshin
2023-05-15 13:51 ` [PATCH, RFC v2 5/8] libm: add attribute weak for __ieee754_sqrtf Alexey Lapshin
2023-05-15 13:53 ` [PATCH, RFC v2 6/8] libgloss: libnosys: add xtensa port Alexey Lapshin
2023-05-15 13:54 ` [PATCH, RFC v2 7/8] libgloss: " Alexey Lapshin
2023-05-15 13:55 ` [PATCH, RFC v2 8/8] libc: xtensa: fix PSRAM cache bug Alexey Lapshin
2023-05-30 19:58 ` [PATCH, RFC v2 0/8] add xtensa port Jeff Johnston
2023-05-31 7:53 ` Alexey Lapshin
2023-08-09 20:00 ` [PATCH, RFC v3 0/3] " Alexey Lapshin
2023-08-09 20:02 ` [PATCH, RFC v3 1/3] libc: fix nested sys-include dirs install Alexey Lapshin
2023-08-09 20:03 ` [PATCH, RFC v3 2/3] newlib: add Xtensa port Alexey Lapshin
2023-08-09 20:04 ` [PATCH, RFC v3 3/3] libgloss: " Alexey Lapshin
2023-08-10 18:20 ` [PATCH, RFC v3 0/3] add xtensa port Jeff Johnston
2023-08-10 19:50 ` Alexey Lapshin
2023-08-10 22:12 ` Jeff Johnston
2023-08-10 22:15 ` Alexey Lapshin
2023-08-10 22:18 ` Jeff Johnston
2023-08-15 7:20 ` Alexey Lapshin
2023-08-15 14:48 ` Jeff Johnston
2023-08-15 15:07 ` Alexey Lapshin [this message]
2023-08-15 17:53 ` Jeff Johnston
2023-08-15 19:20 ` Alexey Lapshin
2023-08-15 22:09 ` Jeff Johnston
2023-08-16 7:46 ` Alexey Lapshin
2023-08-16 18:55 ` Jeff Johnston
2023-08-17 20:38 ` Alexey Lapshin
2023-08-17 22:25 ` Jeff Johnston
2023-08-18 10:13 ` Alexey Lapshin
2023-08-23 20:57 ` Jeff Johnston
2023-08-23 21:28 ` Alexey Lapshin
2023-08-24 15:01 ` Jeff Johnston
2023-08-24 15:45 ` Alexey Lapshin
2023-09-11 12:07 ` [PATCH, RFC 0/8] " Sebastian Huber
2023-09-11 12:15 ` Alexey Lapshin
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