RE: Future of SID

["Mikael Starvik" <mikael.starvik@axis.com>]

[-- Attachment #1: Type: text/plain, Size: 1028 bytes --]

Long time since this email conversation took place but anyway. I have
attached the SID configuration files that we use to set up an entire system
with CPU, MMU, Ethernet etc that runs Linux 2.6. I have also attached the
small file we use to add a second CPU and run SMP. Works like a charm :-)

The components are not quite ready for submission yet.

/Mikael

-----Original Message-----
From: Frank Ch. Eigler [mailto:fche@redhat.com] 
Sent: Wednesday, March 30, 2005 12:16 AM
To: Mikael Starvik
Cc: sid@sources.redhat.com
Subject: Re: Future of SID


Hi -

On Tue, Mar 29, 2005 at 09:33:21AM +0200, Mikael Starvik wrote:
> [...]
> During the development of a new System-On-Chip ASIC we have developed SID
> components of most parts of the system including CPU, MMU, DMA, Ethernet,
> UART etc. We have used this to develop a working Linux port [...]

Wonderful!  Do you expect to be able to eventually share any of this
modelling effort outside Axis?  Even just the sid configuration files
you use would be informative.

- FChE

[-- Attachment #2: linux.conf --]
[-- Type: application/octet-stream, Size: 20617 bytes --]

# Load libraries
load libcache.la cache_component_library
load libcgencpu.la cgen_component_library
load libconsoles.la console_component_library
load libdma.la dma_component_library
load libethernet.la ethernet_component_library
load libgdb.la gdb_component_library
load libgloss.la gloss_component_library
load libglue.la glue_component_library
load libgpio.la gpio_component_library
load libinterrupt.la interrupt_component_library
load libloader.la loader_component_library
load libmapper.la mapper_component_library
load libmemory.la mem_component_library
load libmmu.la mmu_component_library
load libprof.la prof_component_library
load libsched.la sched_component_library
load libtimers.la timer_component_library
load libuart.la uart_component_library
load libcrypto_accel.la crypto_component_library
load libfamilies.la families_component_library

set main persistent? false

# Allocate components
new hw-cpu-crisv32 cpu
new hw-mmu-crisv32 insn-mmu
new hw-mmu-crisv32 data-mmu
new hw-mapper-basic cpu-mapper
new hw-glue-sequence-8 init-sequence
new hw-glue-sequence-8 hw-reset-net
new hw-glue-sequence-8 deinit-sequence
new hw-glue-sequence-1 yield-net
new hw-glue-sequence-2 cache-flush-net
new sid-sched-host-accurate host-sched
new sid-sched-sim target-sched
new hw-dma-crisv32 dma0
new hw-dma-crisv32 dma1
new hw-dma-crisv32 dma2
new hw-dma-crisv32 dma3
new hw-dma-crisv32 dma4
new hw-dma-crisv32 dma5
new hw-dma-crisv32 dma6
new hw-dma-crisv32 dma7
new hw-dma-crisv32 dma8
new hw-dma-crisv32 dma9
new hw-dmafifo-crisv32 fifo0
new hw-dmafifo-crisv32 fifo1
new hw-dmafifo-crisv32 fifo2
new hw-dmafifo-crisv32 fifo3
new hw-dmafifo-crisv32 fifo4
new hw-dmafifo-crisv32 fifo5
new hw-dmafifo-crisv32 fifo6
new hw-dmafifo-crisv32 fifo7
new hw-dmafifo-crisv32 fifo8
new hw-dmafifo-crisv32 fifo9
new hw-ethernet-crisv32 eth0
new hw-ethernet-crisv32 eth1
new hw-uart-crisv32 ser0
new hw-uart-crisv32 ser1
new hw-uart-crisv32 ser2
new hw-uart-crisv32 ser3
new hw-crypto-crisv32 strcop
new hw-timer-crisv32 timer
new hw-interrupt-crisv32 irq
new hw-gpio-crisv32 gpio
new hw-memory-flash-am29bds323d cse0
new hw-memory-flash-am29bds323d cse1
new hw-memory-nandflash-samsung_2816 nand_flash
new hw-memory-ram/rom-basic sdram
new hw-memory-ram/rom-basic intram
new hw-memory-ram/rom-basic bootrom
new hw-memory-ram/rom-basic dummy
new hw-config_regs-crisv32 config_regs

# Global connections
set host-sched num-clients 10 # large enough?
set target-sched num-clients 10 # large enough?
connect-pin main perform-activity -> host-sched advance
connect-pin main perform-activity -> target-sched advance
connect-pin main starting -> init-sequence input
connect-pin main stopping -> deinit-sequence input
connect-pin init-sequence output-0 -> hw-reset-net input
connect-pin hw-reset-net output-0 -> cpu reset!
connect-pin hw-reset-net output-1 -> insn-mmu reset 
connect-pin hw-reset-net output-2 -> data-mmu reset
connect-pin yield-net output-0 -> cpu yield
connect-pin yield-net output-0 -> host-sched yield

# Scheduler
connect-pin target-sched 0-event -> cpu step!
connect-pin target-sched 0-control <- cpu step-cycles
connect-pin target-sched time-query <- cpu time-query
connect-pin target-sched time-high -> cpu time-high
connect-pin target-sched time-low -> cpu time-low
set host-sched 0-regular? 1
set host-sched 0-time 150 # apprx. human perception limit

# CPU
set cpu step-insn-count 10000
set cpu engine-type pbb
set cpu endian little

# MMUs
connect-bus insn-mmu all cpu-mapper access-port
connect-bus data-mmu all cpu-mapper access-port
connect-bus cpu insn-memory insn-mmu access-port
connect-pin cpu user -> insn-mmu user
connect-pin cpu pid -> insn-mmu pid
connect-pin cpu enable-insn-mmu -> insn-mmu enable
connect-bus cpu support-function-register-bank-1 insn-mmu registers
connect-pin insn-mmu refill_fault -> cpu insn-refill-fault
connect-pin insn-mmu invalid_fault -> cpu insn-invalidaddr-fault
connect-pin insn-mmu access_fault -> cpu insn-access-fault
connect-pin insn-mmu ex_fault -> cpu insn-ex-fault
connect-pin insn-mmu fault_address -> cpu insn-fault-address
set insn-mmu accesses-are-fetches true
connect-bus cpu data-memory data-mmu access-port
connect-pin cpu user -> data-mmu user
connect-pin cpu pid -> data-mmu pid
connect-pin cpu enable-data-mmu -> data-mmu enable
connect-bus cpu support-function-register-bank-2 data-mmu registers
connect-pin data-mmu refill_fault -> cpu data-refill-fault
connect-pin data-mmu invalid_fault -> cpu data-invalidaddr-fault
connect-pin data-mmu access_fault -> cpu data-access-fault
connect-pin data-mmu we_fault -> cpu data-we-fault
connect-pin data-mmu fault_address -> cpu data-fault-address

# Ethernet interface 0
connect-pin hw-reset-net output-0 -> eth0 reset
connect-pin hw-reset-net output-0 -> fifo0 reset
connect-pin hw-reset-net output-0 -> fifo1 reset
connect-pin hw-reset-net output-0 -> dma0 reset
connect-pin hw-reset-net output-0 -> dma1 reset
connect-pin dma0 data_out -> fifo0 data_in
connect-pin dma0 eop_out -> fifo0 write_eop
connect-pin dma0 wait_out -> fifo0 write_wait
connect-bus dma0 memif cpu-mapper access-port
connect-bus dma1 memif cpu-mapper access-port
connect-pin fifo0 data_out -> eth0 data_out
connect-pin fifo0 read_eop -> eth0 eop_out
connect-pin fifo0 read_wait -> eth0 wait
connect-pin fifo1 read_eop -> dma1 eop_in
connect-pin fifo1 read_wait -> dma0 wait_ack
connect-pin fifo1 data_out -> dma1 data_in
connect-pin eth0 data_in -> fifo1 data_in
connect-pin eth0 eop_in -> fifo1 write_eop
connect-pin eth0 wait_ack -> fifo1 write_wait
connect-pin main perform-activity -> eth0 check
set dma0 direction? 0
set dma1 direction? 1
set eth0 device eth0

# Ethernet interface 1
connect-pin hw-reset-net output-0 -> eth1 reset
connect-pin hw-reset-net output-0 -> fifo6 reset
connect-pin hw-reset-net output-0 -> fifo7 reset
connect-pin hw-reset-net output-0 -> dma6 reset
connect-pin hw-reset-net output-0 -> dma7 reset
connect-pin dma6 data_out -> fifo6 data_in
connect-pin dma6 eop_out -> fifo6 write_eop
connect-pin dma6 wait_out -> fifo6 write_wait
connect-bus dma6 memif cpu-mapper access-port
connect-bus dma7 memif cpu-mapper access-port
connect-pin fifo6 data_out -> eth1 data_out
connect-pin fifo6 read_eop -> eth1 eop_out
connect-pin fifo6 read_wait -> eth1 wait
connect-pin fifo7 read_eop -> dma7 eop_in
connect-pin fifo7 read_wait -> dma6 wait_ack
connect-pin fifo7 data_out -> dma7 data_in
connect-pin eth1 data_in -> fifo7 data_in
connect-pin eth1 eop_in -> fifo7 write_eop
connect-pin eth1 wait_ack -> fifo7 write_wait
connect-pin main perform-activity -> eth1 check
set dma6 direction? 0
set dma7 direction? 1
set eth1 device eth1

# Serial port 0 (manual mode)
connect-pin hw-reset-net output-0 -> ser0 reset
connect-pin main perform-activity -> ser0 check
set ser0 device /dev/ttyS0
set ser0 slowdown 2
set ser0 speedup 1

# Serial port 1 (DMA)
connect-pin hw-reset-net output-0 -> ser1 reset
connect-pin hw-reset-net output-0 -> fifo4 reset
connect-pin hw-reset-net output-0 -> fifo5 reset
connect-pin hw-reset-net output-0 -> dma4 reset
connect-pin hw-reset-net output-0 -> dma5 reset
connect-pin dma4 data_out -> fifo4 data_in
connect-pin dma4 eop_out -> fifo4 write_eop
connect-pin dma4 wait_out -> fifo4 write_wait
connect-bus dma4 memif cpu-mapper access-port
connect-bus dma5 memif cpu-mapper access-port
connect-pin dma5 stop_input -> fifo5 stop_output
connect-pin fifo4 stop_input -> dma4 stop_output
connect-pin fifo4 data_out -> ser1 data_out
connect-pin fifo4 read_wait -> ser1 wait
connect-pin fifo5 data_out -> dma5 data_in
connect-pin fifo5 read_eop -> dma5 eop_in
connect-pin fifo5 read_wait -> dma4 wait_ack
connect-pin ser1 data_in -> fifo5 data_in
connect-pin ser1 wait_ack -> fifo5 write_wait
connect-pin ser1 stop_output -> fifo4 stop_output
connect-pin ser1 receive_timeout -> fifo5 flush_eop
connect-pin main perform-activity -> ser1 check
connect-pin ser1 receive_timer-control -> target-sched 1-control
connect-pin target-sched 1-event -> ser1 receive_timer-event
set dma4 direction? 0
set dma5 direction? 1
set ser1 device /dev/ttyS1
set ser1 slowdown 2
set ser1 speedup 1

# Serial port 2 (DMA)
connect-pin hw-reset-net output-0 -> ser2 reset
connect-pin hw-reset-net output-0 -> fifo2 reset
connect-pin hw-reset-net output-0 -> fifo3 reset
connect-pin hw-reset-net output-0 -> dma2 reset
connect-pin hw-reset-net output-0 -> dma3 reset
connect-pin dma2 data_out -> fifo2 data_in
connect-pin dma2 eop_out -> fifo2 write_eop
connect-pin dma2 wait_out -> fifo2 write_wait
connect-bus dma2 memif cpu-mapper access-port
connect-bus dma3 memif cpu-mapper access-port
connect-pin dma3 stop_input -> fifo3 stop_output
connect-pin fifo2 stop_input -> dma2 stop_output
connect-pin fifo2 data_out -> ser2 data_out
connect-pin fifo2 read_wait -> ser2 wait
connect-pin fifo3 data_out -> dma3 data_in
connect-pin fifo3 read_eop -> dma3 eop_in
connect-pin fifo3 read_wait -> dma2 wait_ack
connect-pin ser2 data_in -> fifo3 data_in
connect-pin ser2 wait_ack -> fifo3 write_wait
connect-pin ser2 stop_output -> fifo2 stop_output
connect-pin ser2 receive_timeout -> fifo3 flush_eop
connect-pin main perform-activity -> ser2 check
connect-pin ser2 receive_timer-control -> target-sched 2-control
connect-pin target-sched 2-event -> ser2 receive_timer-event
set dma2 direction? 0
set dma3 direction? 1
set ser2 device /dev/ttyS2
set ser2 slowdown 2
set ser2 speedup 1

# Serial port 3 (manual mode)
connect-pin hw-reset-net output-0 -> ser3 reset
connect-pin main perform-activity -> ser3 check
set ser3 device /dev/ttyS3
set ser3 slowdown 2
set ser3 speedup 1

# Strcop
connect-pin hw-reset-net output-0 -> strcop reset
connect-pin hw-reset-net output-0 -> fifo8 reset
connect-pin hw-reset-net output-0 -> fifo9 reset
connect-pin hw-reset-net output-0 -> dma8 reset
connect-pin hw-reset-net output-0 -> dma9 reset
connect-pin dma8 data_out -> fifo8 data_in
connect-pin dma8 eop_out -> fifo8 write_eop
connect-pin dma8 wait_out -> fifo8 write_wait
connect-bus dma8 memif cpu-mapper access-port
connect-bus dma8 metadata strcop metadata_out
connect-bus dma9 memif cpu-mapper access-port
connect-bus dma9 metadata strcop metadata_in
connect-pin dma9 stop_input -> fifo9 stop_output
connect-pin fifo8 stop_input -> dma8 stop_output
connect-pin fifo8 data_out -> strcop data_out
connect-pin fifo8 read_eop -> strcop eop_out
connect-pin fifo8 read_wait -> strcop wait
connect-pin fifo9 read_eop -> dma9 eop_in
connect-pin fifo9 read_wait -> dma8 wait_ack
connect-pin fifo9 data_out -> dma9 data_in
connect-pin strcop data_in -> fifo9 data_in
connect-pin strcop eop_in -> fifo9 write_eop
connect-pin strcop wait_ack -> fifo9 write_wait
connect-pin strcop force_flush -> fifo9 flush
connect-pin strcop force_flush_eop -> fifo9 flush_eop
set dma8 direction? 0
set dma9 direction? 1

# Timer
connect-pin hw-reset-net output-0 -> timer reset
connect-pin timer timer0-control -> target-sched 3-control
connect-pin target-sched 3-event -> timer timer0-event
connect-pin timer timer1-control -> target-sched 4-control
connect-pin target-sched 4-event -> timer timer1-event
connect-pin timer trig-control -> target-sched 5-control
connect-pin target-sched 5-event -> timer trig-event
connect-pin timer watchdog-control -> target-sched 6-control
connect-pin target-sched 6-event -> timer watchdog-event
connect-pin timer nmi -> cpu nmi
connect-pin timer reset_out -> init-sequence input
set timer slowdown 2
set timer speedup 1
set timer nmi_polarity 1

# Interrupt
connect-pin hw-reset-net output-0 -> irq reset
connect-pin dma0 irq_out -> irq irq6
connect-pin dma1 irq_out -> irq irq7
connect-pin dma2 irq_out -> irq irq8
connect-pin dma3 irq_out -> irq irq9
connect-pin dma4 irq_out -> irq irq10
connect-pin dma5 irq_out -> irq irq11
connect-pin dma6 irq_out -> irq irq12
connect-pin dma7 irq_out -> irq irq13
connect-pin dma8 irq_out -> irq irq14
connect-pin dma9 irq_out -> irq irq15
connect-pin ser0 irq_out -> irq irq19
connect-pin ser1 irq_out -> irq irq20
connect-pin ser2 irq_out -> irq irq21
connect-pin ser3 irq_out -> irq irq22
connect-pin timer irq -> irq irq26
connect-pin irq irq_out -> cpu irq
connect-bus cpu irq_vector irq irq_vector
set irq polarity 1

# NAND flash
connect-pin gpio pa5 -> nand_flash cle
connect-pin gpio pa6 -> nand_flash ale
connect-pin nand_flash busy -> gpio pa7 
connect-pin hw-reset-net output-0 -> nand_flash reset

# Config registers
connect-pin hw-reset-net output-0 -> config_regs reset

# Memory map
set cse0 image-file flash1
set cse1 image-file flash2
connect-pin init-sequence output-1 -> cse1 image-load
connect-bus cpu-mapper cse0:[0x00000000,0x003fffff] cse0 read-write-port
connect-bus cpu-mapper cse0:[0x80000000,0x803fffff] cse0 read-write-port
connect-bus cpu-mapper cse1:[0x04000000,0x043fffff] cse1 read-write-port
connect-bus cpu-mapper cse1:[0x84000000,0x843fffff] cse1 read-write-port
connect-bus cpu-mapper csp0:[0x90000000,0x90ffffff] nand_flash read-write-port
connect-bus cpu-mapper csp1:[0x94000000,0x94ffffff] nand_flash read-write-port
set sdram size 33554432
set sdram image-file kimage
connect-bus cpu-mapper sdram:[0x40000000,0x42000000] sdram read-write-port
connect-bus cpu-mapper sdram:[0xc0000000,0xc2000000] sdram read-write-port
set intram size 131072
connect-bus cpu-mapper intram:[0x38000000,0x38020000] intram read-write-port
set bootrom size 16384
set bootrom image-file bootrom.ima
connect-bus cpu-mapper intram:[0x3c000000,0x3c004000] bootrom read-write-port

connect-pin init-sequence output-1 -> cse0 image-load
connect-pin init-sequence output-1 -> sdram image-load
connect-pin init-sequence output-1 -> bootrom image-load

# The Linux kernel tries to probe flashes at addresses that are not
# mapped. The dummy devices below prevents SID from exiting due to
# unmapped address access.
set dummy size 8192
connect-bus cpu-mapper dummy:[0x80400000,0x80400fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x80600000,0x80600fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x80800000,0x80800fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x80a00000,0x80a00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x80c00000,0x80c00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x80e00000,0x80e00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x81000000,0x81000fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x81200000,0x81200fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x81400000,0x81400fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x81600000,0x81600fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x81800000,0x81800fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x81a00000,0x81a00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x81c00000,0x81c00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x81e00000,0x81e00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x82000000,0x82000fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x82200000,0x82200fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x82400000,0x82400fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x82600000,0x82600fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x82800000,0x82800fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x82a00000,0x82a00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x82c00000,0x82c00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x82e00000,0x82e00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x83000000,0x83000fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x83200000,0x83200fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x83400000,0x83400fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x83600000,0x83600fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x83800000,0x83800fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x83a00000,0x83a00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x83c00000,0x83c00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x83e00000,0x83e00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x84400000,0x84400fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x84600000,0x84600fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x84800000,0x84800fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x84a00000,0x84a00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x84c00000,0x84c00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x84e00000,0x84e00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x85000000,0x85000fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x85200000,0x85200fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x85400000,0x85400fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x85600000,0x85600fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x85800000,0x85800fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x85a00000,0x85a00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x85c00000,0x85c00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x85e00000,0x85e00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x86000000,0x86000fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x86200000,0x86200fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x86400000,0x86400fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x86600000,0x86600fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x86800000,0x86800fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x86a00000,0x86a00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x86c00000,0x86c00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x86e00000,0x86e00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x87000000,0x87000fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x87200000,0x87200fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x87400000,0x87400fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x87600000,0x87600fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x87800000,0x87800fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x87a00000,0x87a00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x87c00000,0x87c00fff] dummy read-write-port
connect-bus cpu-mapper dummy:[0x87e00000,0x87e00fff] dummy read-write-port

# Mode registers
connect-bus cpu-mapper dma0:[0xb0000000,0xb0001fff] dma0 registers
connect-bus cpu-mapper dma1:[0xb0002000,0xb0003fff] dma1 registers
connect-bus cpu-mapper dma2:[0xb0004000,0xb0005fff] dma2 registers
connect-bus cpu-mapper dma3:[0xb0006000,0xb0007fff] dma3 registers
connect-bus cpu-mapper dma4:[0xb0008000,0xb0009fff] dma4 registers
connect-bus cpu-mapper dma5:[0xb000a000,0xb000bfff] dma5 registers
connect-bus cpu-mapper dma6:[0xb000c000,0xb000dfff] dma6 registers
connect-bus cpu-mapper dma7:[0xb000e000,0xb000ffff] dma7 registers
connect-bus cpu-mapper dma8:[0xb0010000,0xb0011fff] dma8 registers
connect-bus cpu-mapper dma9:[0xb0012000,0xb0013fff] dma9 registers
connect-bus cpu-mapper gpio:[0xb001a000,0xb001bfff] gpio registers
connect-bus cpu-mapper timer:[0xb001e000,0xb001ffff] timer registers
connect-bus cpu-mapper irq:[0xb001c000,0xb001dfff] irq registers
connect-bus cpu-mapper ser0:[0xb0026000,0xb0027fff] ser0 registers
connect-bus cpu-mapper ser1:[0xb0028000,0xb0029fff] ser1 registers
connect-bus cpu-mapper ser2:[0xb002a000,0xb002bfff] ser2 registers
connect-bus cpu-mapper ser3:[0xb002c000,0xb002dfff] ser3 registers
connect-bus cpu-mapper strcop:[0xb0030000,0xb0031fff] strcop registers
connect-bus cpu-mapper eth0:[0xb0034000,0xb0035fff] eth0 registers
connect-bus cpu-mapper eth1:[0xb0036000,0xb0037fff] eth1 registers
# Set up dummy memory for mode registers not modelled
connect-bus cpu-mapper bif_core:[0xb0014000,0xb0015fff] dummy read-write-port
connect-bus cpu-mapper strmux:[0xb003a000,0xb003bfff] dummy read-write-port
connect-bus cpu-mapper config:[0xb003c000,0xb003dfff] config_regs registers
connect-bus cpu-mapper marb:[0xb003e000,0xb003ffff] dummy read-write-port
connect-bus cpu-mapper pinmux:[0xb0038000,0xb0039fff] dummy read-write-port
connect-bus cpu-mapper iop:[0xb0020000,0xb0021fff] dummy read-write-port

[-- Attachment #3: smp.conf --]
[-- Type: application/octet-stream, Size: 4705 bytes --]

# Load libraries
load libcache.la cache_component_library
load libcgencpu.la cgen_component_library
load libmmu.la mmu_component_library
load libinterrupt.la interrupt_component_library

# Allocate components
new hw-cpu-crisv32 cpu2
new hw-mmu-crisv32 insn-mmu2
new hw-mmu-crisv32 data-mmu2
new hw-cache-dummy icache
new hw-cache-dummy dcache
new hw-cache-dummy icache2
new hw-cache-dummy dcache2
new hw-interrupt-crisv32 irq2
new hw-timer-crisv32 timer2

# Global connections
connect-pin hw-reset-net output-0 -> cpu2 reset!
connect-pin hw-reset-net output-1 -> insn-mmu2 reset 
connect-pin hw-reset-net output-2 -> data-mmu2 reset
connect-pin yield-net output-0 -> cpu2 yield

# Scheduler
connect-pin target-sched 0-event -> cpu2 step!
connect-pin target-sched 0-control <- cpu2 step-cycles
connect-pin target-sched time-query <- cpu2 time-query
connect-pin target-sched time-high -> cpu2 time-high
connect-pin target-sched time-low -> cpu2 time-low

# Override settings from linux.conf
disconnect-bus insn-mmu all cpu-mapper access-port
disconnect-bus data-mmu all cpu-mapper access-port
connect-bus insn-mmu all icache upstream
connect-bus data-mmu all dcache upstream
set cpu crisv32-start-address 0

# CPU
set cpu2 step-insn-count 10000
set cpu2 engine-type pbb
set cpu2 endian little
set cpu2 crisv32-start-address 0

# MMUs
connect-bus insn-mmu2 all icache2 upstream
connect-bus data-mmu2 all dcache2 upstream
connect-bus cpu2 insn-memory insn-mmu2 access-port
connect-pin cpu2 user -> insn-mmu2 user
connect-pin cpu2 pid -> insn-mmu2 pid
connect-pin cpu2 enable-insn-mmu -> insn-mmu2 enable
connect-bus cpu2 support-function-register-bank-1 insn-mmu2 registers
connect-pin insn-mmu2 refill_fault -> cpu2 insn-refill-fault
connect-pin insn-mmu2 invalid_fault -> cpu2 insn-invalidaddr-fault
connect-pin insn-mmu2 access_fault -> cpu2 insn-access-fault
connect-pin insn-mmu2 ex_fault -> cpu2 insn-ex-fault
connect-pin insn-mmu2 fault_address -> cpu2 insn-fault-address
set insn-mmu2 accesses-are-fetches true
connect-bus cpu2 data-memory data-mmu2 access-port
connect-pin cpu2 user -> data-mmu2 user
connect-pin cpu2 pid -> data-mmu2 pid
connect-pin cpu2 enable-data-mmu -> data-mmu2 enable
connect-bus cpu2 support-function-register-bank-2 data-mmu2 registers
connect-pin data-mmu2 refill_fault -> cpu2 data-refill-fault
connect-pin data-mmu2 invalid_fault -> cpu2 data-invalidaddr-fault
connect-pin data-mmu2 access_fault -> cpu2 data-access-fault
connect-pin data-mmu2 we_fault -> cpu2 data-we-fault
connect-pin data-mmu2 fault_address -> cpu2 data-fault-address

# Cache
connect-bus icache downstream cpu-mapper access-port
connect-bus dcache downstream cpu-mapper access-port
connect-pin dcache write_miss -> cpu dcache-write-miss
connect-pin cpu dcache-abort-write -> dcache abort
connect-bus icache2 downstream cpu-mapper access-port
connect-bus dcache2 downstream cpu-mapper access-port
connect-pin dcache2 write_miss -> cpu2 dcache-write-miss
connect-pin cpu2 dcache-abort-write -> dcache2 abort
connect-pin dcache write_out -> dcache2 write_in
connect-pin dcache2 write_out -> dcache write_in

# Timer
connect-pin hw-reset-net output-0 -> timer2 reset
connect-pin timer2 timer0-control -> target-sched 3-control
connect-pin target-sched 3-event -> timer2 timer0-event
connect-pin timer2 timer1-control -> target-sched 4-control
connect-pin target-sched 4-event -> timer2 timer1-event
connect-pin timer2 trig-control -> target-sched 5-control
connect-pin target-sched 5-event -> timer2 trig-event
connect-pin timer2 watchdog-control -> target-sched 6-control
connect-pin target-sched 6-event -> timer2 watchdog-event
connect-pin timer2 nmi -> cpu2 nmi
set timer2 slowdown 2
set timer2 speedup 1
set timer2 nmi_polarity 1

# Interrupt
connect-pin hw-reset-net output-0 -> irq2 reset
connect-pin dma0 irq_out -> irq2 irq6
connect-pin dma1 irq_out -> irq2 irq7
connect-pin dma2 irq_out -> irq2 irq8
connect-pin dma3 irq_out -> irq2 irq9
connect-pin dma4 irq_out -> irq2 irq10
connect-pin dma5 irq_out -> irq2 irq11
connect-pin dma6 irq_out -> irq2 irq12
connect-pin dma7 irq_out -> irq2 irq13
connect-pin dma8 irq_out -> irq2 irq14
connect-pin dma9 irq_out -> irq2 irq15
connect-pin ser0 irq_out -> irq2 irq19
connect-pin ser1 irq_out -> irq2 irq20
connect-pin ser2 irq_out -> irq2 irq21
connect-pin ser3 irq_out -> irq2 irq22
connect-pin timer2 irq -> irq2 irq26
connect-pin irq2 ipi_out -> irq2 irq30
connect-pin irq ipi_out -> irq irq30
connect-pin irq2 irq_out -> cpu2 irq
connect-bus cpu2 irq_vector irq2 irq_vector
set irq2 polarity 1

# Memory map
connect-bus cpu-mapper irq2:[0xb005c000,0xb005dfff] irq2 registers
connect-bus cpu-mapper timer2:[0xb005e000,0xb005ffff] timer2 registers