* [PATCH 0/2] x86: further opcode table line length reduction
@ 2022-12-12 13:10 Jan Beulich
2022-12-12 13:12 ` [PATCH 1/2] x86: change representation of extension opcode Jan Beulich
2022-12-12 13:14 ` [PATCH 2/2] x86: omit Cpu prefixes from opcode table Jan Beulich
0 siblings, 2 replies; 4+ messages in thread
From: Jan Beulich @ 2022-12-12 13:10 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
[-- Attachment #1: Type: text/plain, Size: 581 bytes --]
Lines are still way too long in many cases, so this series takes
two further steps towards shrinking. While the 1st patch is
hopefully going to be uncontroversial, the 2nd one might be, and
has a respective RFC remark for this very reason. Due to their
size I'm attaching both patches here, and I'll include only
abridged variants (with only some opcode table hunks retained,
just to demonstrate the transformation done, but of course with
all changes to other [non-generated] files retained).
1: change representation of extension opcode
2: omit Cpu prefixes in opcode table
Jan
[-- Attachment #2: binutils-master.tb2 --]
[-- Type: application/octet-stream, Size: 58305 bytes --]
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] x86: change representation of extension opcode
2022-12-12 13:10 [PATCH 0/2] x86: further opcode table line length reduction Jan Beulich
@ 2022-12-12 13:12 ` Jan Beulich
2022-12-12 13:14 ` [PATCH 2/2] x86: omit Cpu prefixes from opcode table Jan Beulich
1 sibling, 0 replies; 4+ messages in thread
From: Jan Beulich @ 2022-12-12 13:12 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
x86: change representation of extension opcode
Having a "None" field in the vast majority of entries is needlessly
cluttering the overall table. Instead of this being a separate field,
use a representation matching that of Intel SDM and AMD PM for the main
use of the field: Append the value after a / as the separator.
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -1299,8 +1299,10 @@ output_i386_opcode (FILE *table, const c
/* Find base_opcode. */
base_opcode = next_field (str, ',', &str, last);
- /* Find extension_opcode. */
- extension_opcode = next_field (str, ',', &str, last);
+ /* Find extension_opcode, if any. */
+ extension_opcode = strchr (base_opcode, '/');
+ if (extension_opcode)
+ *extension_opcode++ = '\0';
/* Find cpu_flags. */
cpu_flags = next_field (str, ',', &str, last);
@@ -1385,7 +1387,8 @@ output_i386_opcode (FILE *table, const c
filename, lineno, name, 2 * length, opcode);
fprintf (table, " { \"%s\", 0x%0*llx%s, %lu, %s,\n",
- name, 2 * (int)length, opcode, end, i, extension_opcode);
+ name, 2 * (int)length, opcode, end, i,
+ extension_opcode ? extension_opcode : "None");
process_i386_opcode_modifier (table, opcode_modifier, space, prefix,
operand_types, lineno);
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -20,7 +20,6 @@
#define OPCODE_I386_H
#include "i386-opc.h"
-#undef None
// When necessary lines can be split in a non-standard way, by placing a
// trailing + on a to-be-continued line. This is intended mainly for non-insn
@@ -142,723 +141,723 @@
### MARKER ###
// Move instructions.
-mov, 0xa0, None, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
-mov, 0xa0, None, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
-movabs, 0xa0, None, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
-mov, 0x88, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+mov, 0xa0, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
+mov, 0xa0, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
+movabs, 0xa0, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
+mov, 0x88, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
// In the 64bit mode the short form mov immediate is redefined to have
// 64bit value.
-mov, 0xb0, None, 0, W|No_sSuf|No_qSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 }
-mov, 0xc6, 0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-mov, 0xb8, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 }
-movabs, 0xb8, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 }
+mov, 0xb0, 0, W|No_sSuf|No_qSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 }
+mov, 0xc6/0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+mov, 0xb8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 }
+movabs, 0xb8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 }
// The segment register moves accept WordReg so that a segment register
// can be copied to a 32 bit register, and vice versa, without using a
// size prefix. When moving to a 32 bit register, the upper 16 bits
// are set to an implementation defined value (on the Pentium Pro, the
// implementation defined value is zero).
-mov, 0x8c, None, 0, RegMem|No_bSuf|No_sSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 }
-mov, 0x8c, None, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { SReg, Word|Unspecified|BaseIndex }
-mov, 0x8e, None, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
+mov, 0x8c, 0, RegMem|No_bSuf|No_sSuf|NoRex64, { SReg, Reg16|Reg32|Reg64 }
+mov, 0x8c, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { SReg, Word|Unspecified|BaseIndex }
+mov, 0x8e, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
// Move to/from control debug registers. In the 16 or 32bit modes
// they are 32bit. In the 64bit mode they are 64bit.
-mov, 0xf20, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 }
-mov, 0xf20, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 }
-mov, 0xf21, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 }
-mov, 0xf21, None, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 }
-mov, 0xf24, None, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 }
+mov, 0xf20, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 }
+mov, 0xf20, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 }
+mov, 0xf21, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 }
+mov, 0xf21, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 }
+mov, 0xf24, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 }
// Move after swapping the bytes
-movbe, 0x0f38f0, None, CpuMovbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movbe, 0x0f38f0, CpuMovbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Move with sign extend.
-movsb, 0xfbe, None, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movsw, 0xfbf, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 }
-movsl, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 }
-movsx, 0xfbe, None, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movsx, 0x63, None, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
-movsxd, 0x63, None, Cpu64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
-movsxd, 0x63, None, Cpu64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
-movsxd, 0x63, None, Cpu64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 }
+movsb, 0xfbe, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movsw, 0xfbf, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 }
+movsl, 0x63, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 }
+movsx, 0xfbe, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movsx, 0x63, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
+movsxd, 0x63, Cpu64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
+movsxd, 0x63, Cpu64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
+movsxd, 0x63, Cpu64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 }
// Move with zero extend.
-movzb, 0xfb6, None, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movzw, 0xfb7, None, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
+movzb, 0xfb6, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movzw, 0xfb7, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
// The 64-bit variant is not particularly useful since the zero extend
// 32->64 is implicit, but we can encode them.
-movzx, 0xfb6, None, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movzx, 0xfb6, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Push instructions.
-push, 0x50, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
-push, 0xff, 6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
-push, 0x6a, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S }
-push, 0x68, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 }
-push, 0x6, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
+push, 0x50, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
+push, 0xff/6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
+push, 0x6a, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S }
+push, 0x68, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 }
+push, 0x6, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
// In 64bit mode, the operand size is implicitly 64bit.
-push, 0x50, None, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
-push, 0xff, 6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
-push, 0x6a, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S }
-push, 0x68, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S }
-push, 0xfa0, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
+push, 0x50, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
+push, 0xff/6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
+push, 0x6a, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S }
+push, 0x68, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S }
+push, 0xfa0, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
-pusha, 0x60, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+pusha, 0x60, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
// Pop instructions.
-pop, 0x58, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
-pop, 0x8f, 0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
-pop, 0x7, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
+pop, 0x58, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
+pop, 0x8f/0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
+pop, 0x7, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
// In 64bit mode, the operand size is implicitly 64bit.
-pop, 0x58, None, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
-pop, 0x8f, 0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
-pop, 0xfa1, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
+pop, 0x58, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
+pop, 0x8f/0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
+pop, 0xfa1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
-popa, 0x61, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+popa, 0x61, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
// Exchange instructions.
// xchg commutes: we allow both operand orders.
// In the 64bit code, xchg rax, rax is reused for new nop instruction.
-xchg, 0x90, None, 0, D|C|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
-xchg, 0x86, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+xchg, 0x90, 0, D|C|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
+xchg, 0x86, 0, D|W|C|CheckRegSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
// In/out from ports.
-in, 0xe4, None, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword }
-in, 0xec, None, 0, W|No_sSuf|No_qSuf, { InOutPortReg, Acc|Byte|Word|Dword }
-in, 0xe4, None, 0, W|No_sSuf|No_qSuf, { Imm8 }
-in, 0xec, None, 0, W|No_sSuf|No_qSuf, { InOutPortReg }
-out, 0xe6, None, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, Imm8 }
-out, 0xee, None, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, InOutPortReg }
-out, 0xe6, None, 0, W|No_sSuf|No_qSuf, { Imm8 }
-out, 0xee, None, 0, W|No_sSuf|No_qSuf, { InOutPortReg }
+in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword }
+in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg, Acc|Byte|Word|Dword }
+in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8 }
+in, 0xec, 0, W|No_sSuf|No_qSuf, { InOutPortReg }
+out, 0xe6, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, Imm8 }
+out, 0xee, 0, W|No_sSuf|No_qSuf, { Acc|Byte|Word|Dword, InOutPortReg }
+out, 0xe6, 0, W|No_sSuf|No_qSuf, { Imm8 }
+out, 0xee, 0, W|No_sSuf|No_qSuf, { InOutPortReg }
// Load effective address.
-lea, 0x8d, None, 0, Modrm|Anysize|No_bSuf|No_sSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 }
+lea, 0x8d, 0, Modrm|Anysize|No_bSuf|No_sSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 }
// Load segment registers from memory.
-lds, 0xc5, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-les, 0xc4, None, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lfs, 0xfb4, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lfs, 0xfb4, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lgs, 0xfb5, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lgs, 0xfb5, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lss, 0xfb2, None, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lss, 0xfb2, None, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lds, 0xc5, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+les, 0xc4, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lfs, 0xfb4, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lfs, 0xfb4, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lgs, 0xfb5, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lgs, 0xfb5, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lss, 0xfb2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lss, 0xfb2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Flags register instructions.
-clc, 0xf8, None, 0, NoSuf, {}
-cld, 0xfc, None, 0, NoSuf, {}
-cli, 0xfa, None, 0, NoSuf, {}
-clts, 0xf06, None, Cpu286, NoSuf, {}
-cmc, 0xf5, None, 0, NoSuf, {}
-lahf, 0x9f, None, 0, NoSuf, {}
-sahf, 0x9e, None, 0, NoSuf, {}
-pushf, 0x9c, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-pushf, 0x9c, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
-popf, 0x9d, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-popf, 0x9d, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
-stc, 0xf9, None, 0, NoSuf, {}
-std, 0xfd, None, 0, NoSuf, {}
-sti, 0xfb, None, 0, NoSuf, {}
+clc, 0xf8, 0, NoSuf, {}
+cld, 0xfc, 0, NoSuf, {}
+cli, 0xfa, 0, NoSuf, {}
+clts, 0xf06, Cpu286, NoSuf, {}
+cmc, 0xf5, 0, NoSuf, {}
+lahf, 0x9f, 0, NoSuf, {}
+sahf, 0x9e, 0, NoSuf, {}
+pushf, 0x9c, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+pushf, 0x9c, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
+popf, 0x9d, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+popf, 0x9d, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
+stc, 0xf9, 0, NoSuf, {}
+std, 0xfd, 0, NoSuf, {}
+sti, 0xfb, 0, NoSuf, {}
// Arithmetic.
-add, 0x0, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-add, 0x83, 0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-add, 0x4, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-add, 0x80, 0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-inc, 0x40, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
-inc, 0xfe, 0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-sub, 0x28, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sub, 0x83, 5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-sub, 0x2c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-sub, 0x80, 5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-dec, 0x48, None, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
-dec, 0xfe, 1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-sbb, 0x18, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sbb, 0x83, 3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-sbb, 0x1c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-sbb, 0x80, 3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-cmp, 0x38, None, 0, D|W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-cmp, 0x83, 7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-cmp, 0x3c, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-cmp, 0x80, 7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-test, 0x84, None, 0, D|W|C|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
-test, 0xa8, None, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-test, 0xf6, 0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-and, 0x20, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-and, 0x83, 4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-and, 0x24, None, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-and, 0x80, 4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-or, 0x8, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-or, 0x83, 1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-or, 0xc, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-or, 0x80, 1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-xor, 0x30, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-xor, 0x83, 6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-xor, 0x34, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-xor, 0x80, 6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+add, 0x0, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+inc, 0x40, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
+inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+sub, 0x28, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+dec, 0x48, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
+dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+sbb, 0x18, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+sbb, 0x1c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+sbb, 0x80/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+cmp, 0x38, 0, D|W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+cmp, 0x3c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+cmp, 0x80/7, 0, W|Modrm|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+test, 0x84, 0, D|W|C|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+test, 0xa8, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+test, 0xf6/0, 0, W|Modrm|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+and, 0x20, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+and, 0x83/4, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock|Optimize, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+and, 0x24, 0, W|No_sSuf|Optimize, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+and, 0x80/4, 0, W|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+or, 0x8, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+or, 0x83/1, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+xor, 0x30, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+xor, 0x34, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+xor, 0x80/6, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
// clr with 1 operand is really xor with 2 operands.
-clr, 0x30, None, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 }
+clr, 0x30, 0, W|Modrm|No_sSuf|RegKludge|Optimize, { Reg8|Reg16|Reg32|Reg64 }
-adc, 0x10, None, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-adc, 0x83, 2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-adc, 0x14, None, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
-adc, 0x80, 2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-neg, 0xf6, 3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-not, 0xf6, 2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-aaa, 0x37, None, CpuNo64, NoSuf, {}
-aas, 0x3f, None, CpuNo64, NoSuf, {}
-daa, 0x27, None, CpuNo64, NoSuf, {}
-das, 0x2f, None, CpuNo64, NoSuf, {}
-aad, 0xd50a, None, CpuNo64, NoSuf, {}
-aad, 0xd5, None, CpuNo64, NoSuf, { Imm8 }
-aam, 0xd40a, None, CpuNo64, NoSuf, {}
-aam, 0xd4, None, CpuNo64, NoSuf, { Imm8 }
+adc, 0x10, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+adc, 0x83/2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+adc, 0x14, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
+adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+aaa, 0x37, CpuNo64, NoSuf, {}
+aas, 0x3f, CpuNo64, NoSuf, {}
+daa, 0x27, CpuNo64, NoSuf, {}
+das, 0x2f, CpuNo64, NoSuf, {}
+aad, 0xd50a, CpuNo64, NoSuf, {}
+aad, 0xd5, CpuNo64, NoSuf, { Imm8 }
+aam, 0xd40a, CpuNo64, NoSuf, {}
+aam, 0xd4, CpuNo64, NoSuf, { Imm8 }
// Conversion insns.
// Intel naming
-cbw, 0x98, None, 0, Size16|NoSuf, {}
-cwde, 0x98, None, Cpu386, Size32|NoSuf, {}
-cdqe, 0x98, None, Cpu64, Size64|NoSuf, {}
-cwd, 0x99, None, 0, Size16|NoSuf, {}
-cdq, 0x99, None, Cpu386, Size32|NoSuf, {}
-cqo, 0x99, None, Cpu64, Size64|NoSuf, {}
+cbw, 0x98, 0, Size16|NoSuf, {}
+cwde, 0x98, Cpu386, Size32|NoSuf, {}
+cdqe, 0x98, Cpu64, Size64|NoSuf, {}
+cwd, 0x99, 0, Size16|NoSuf, {}
+cdq, 0x99, Cpu386, Size32|NoSuf, {}
+cqo, 0x99, Cpu64, Size64|NoSuf, {}
// AT&T naming
-cbtw, 0x98, None, 0, Size16|NoSuf, {}
-cwtl, 0x98, None, Cpu386, Size32|NoSuf, {}
-cltq, 0x98, None, Cpu64, Size64|NoSuf, {}
-cwtd, 0x99, None, 0, Size16|NoSuf, {}
-cltd, 0x99, None, Cpu386, Size32|NoSuf, {}
-cqto, 0x99, None, Cpu64, Size64|NoSuf, {}
+cbtw, 0x98, 0, Size16|NoSuf, {}
+cwtl, 0x98, Cpu386, Size32|NoSuf, {}
+cltq, 0x98, Cpu64, Size64|NoSuf, {}
+cwtd, 0x99, 0, Size16|NoSuf, {}
+cltd, 0x99, Cpu386, Size32|NoSuf, {}
+cqto, 0x99, Cpu64, Size64|NoSuf, {}
// Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
// expanding 64-bit multiplies, and *cannot* be selected to accomplish
// 'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
// These multiplies can only be selected with single operand forms.
-mul, 0xf6, 4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-imul, 0xf6, 5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-imul, 0xfaf, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 }
-imul, 0x6b, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-imul, 0x69, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+imul, 0xfaf, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0x6b, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0x69, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// imul with 2 operands mimics imul with 3 by putting the register in
// both i.rm.reg & i.rm.regmem fields. RegKludge enables this
// transformation.
-imul, 0x6b, None, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 }
-imul, 0x69, None, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
+imul, 0x6b, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 }
+imul, 0x69, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
-div, 0xf6, 6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-div, 0xf6, 6, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-idiv, 0xf6, 7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-idiv, 0xf6, 7, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-
-rol, 0xd0, 0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rol, 0xc0, 0, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rol, 0xd2, 0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rol, 0xd0, 0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-ror, 0xd0, 1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ror, 0xc0, 1, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ror, 0xd2, 1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ror, 0xd0, 1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-rcl, 0xd0, 2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rcl, 0xc0, 2, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rcl, 0xd2, 2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rcl, 0xd0, 2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-rcr, 0xd0, 3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rcr, 0xc0, 3, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rcr, 0xd2, 3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rcr, 0xd0, 3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-sal, 0xd0, 4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sal, 0xc0, 4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sal, 0xd2, 4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sal, 0xd0, 4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-shl, 0xd0, 4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shl, 0xc0, 4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shl, 0xd2, 4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shl, 0xd0, 4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-shr, 0xd0, 5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shr, 0xc0, 5, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shr, 0xd2, 5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shr, 0xd0, 5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-sar, 0xd0, 7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sar, 0xc0, 7, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sar, 0xd2, 7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sar, 0xd0, 7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-
-shld, 0xfa4, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shld, 0xfa5, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shld, 0xfa5, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-
-shrd, 0xfac, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shrd, 0xfad, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shrd, 0xfad, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+div, 0xf6/6, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+idiv, 0xf6/7, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+
+rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rol, 0xc0/0, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ror, 0xc0/1, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rcl, 0xc0/2, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rcr, 0xc0/3, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rcr, 0xd2/3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sal, 0xc0/4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sal, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shl, 0xc0/4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shr, 0xc0/5, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sar, 0xc0/7, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shld, 0xfa4, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shld, 0xfa5, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shld, 0xfa5, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shrd, 0xfac, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shrd, 0xfad, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shrd, 0xfad, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
// Control transfer instructions.
-call, 0xe8, None, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 }
-call, 0xe8, None, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 }
-call, 0xe8, None, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 }
-call, 0xff, 2, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
-call, 0xff, 2, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
-call, 0xff, 2, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
+call, 0xe8, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 }
+call, 0xe8, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 }
+call, 0xe8, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 }
+call, 0xff/2, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
+call, 0xff/2, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
+call, 0xff/2, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
// Intel Syntax remaining call instances.
-call, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
-call, 0xff, 3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|NoSuf, { Dword|Fword|BaseIndex }
-call, 0xff, 3, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
-lcall, 0x9a, None, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
-lcall, 0xff, 3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex }
-lcall, 0xff, 3, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
-
-jmp, 0xeb, None, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
-jmp, 0xeb, None, Cpu64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 }
-jmp, 0xff, 4, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
-jmp, 0xff, 4, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
-jmp, 0xff, 4, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
+call, 0x9a, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+call, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|NoSuf, { Dword|Fword|BaseIndex }
+call, 0xff/3, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
+lcall, 0x9a, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+lcall, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex }
+lcall, 0xff/3, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
+
+jmp, 0xeb, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
+jmp, 0xeb, Cpu64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 }
+jmp, 0xff/4, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
+jmp, 0xff/4, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
+jmp, 0xff/4, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
// Intel Syntax remaining jmp instances.
-jmp, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
-jmp, 0xff, 5, 0, Amd64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|BaseIndex }
-jmp, 0xff, 5, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
-ljmp, 0xea, None, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
-ljmp, 0xff, 5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex }
-ljmp, 0xff, 5, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
-
-ret, 0xc3, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, None, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
-ret, 0xc3, None, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, None, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
-ret, 0xc3, None, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, None, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
-lret, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf, {}
-lret, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 }
+jmp, 0xea, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+jmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|BaseIndex }
+jmp, 0xff/5, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
+ljmp, 0xea, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+ljmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex }
+ljmp, 0xff/5, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
+
+ret, 0xc3, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {}
+ret, 0xc2, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0xc3, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
+ret, 0xc2, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0xc3, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
+ret, 0xc2, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
+lret, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {}
+lret, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 }
// Intel Syntax.
-retf, 0xcb, None, 0, DefaultSize|No_bSuf|No_sSuf, {}
-retf, 0xca, None, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 }
+retf, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {}
+retf, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 }
-enter, 0xc8, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 }
-enter, 0xc8, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 }
-leave, 0xc9, None, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-leave, 0xc9, None, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
+enter, 0xc8, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 }
+enter, 0xc8, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 }
+leave, 0xc9, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+leave, 0xc9, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
<cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, +
s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
// Conditional jumps.
-j<cc>, 0x7<cc:opc>, None, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
+j<cc>, 0x7<cc:opc>, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
// jcxz vs. jecxz is chosen on the basis of the address size prefix.
-jcxz, 0xe3, None, CpuNo64, JumpByte|Size16|NoSuf, { Disp8 }
-jecxz, 0xe3, None, Cpu386, JumpByte|Size32|NoSuf, { Disp8 }
-jrcxz, 0xe3, None, Cpu64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 }
+jcxz, 0xe3, CpuNo64, JumpByte|Size16|NoSuf, { Disp8 }
+jecxz, 0xe3, Cpu386, JumpByte|Size32|NoSuf, { Disp8 }
+jrcxz, 0xe3, Cpu64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 }
// The loop instructions also use the address size prefix to select
// %cx rather than %ecx for the loop count, so the `w' form of these
// instructions emit an address size prefix rather than a data size
// prefix.
-loop, 0xe2, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loop, 0xe2, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopz, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopz, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loope, 0xe1, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loope, 0xe1, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopnz, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopnz, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopne, 0xe0, None, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopne, 0xe0, None, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loop, 0xe2, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loop, 0xe2, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loopz, 0xe1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loopz, 0xe1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loope, 0xe1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loope, 0xe1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loopnz, 0xe0, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loopnz, 0xe0, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loopne, 0xe0, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loopne, 0xe0, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
// Set byte on flag instructions.
-set<cc>, 0xf9<cc:opc>, 0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex }
+set<cc>, 0xf9<cc:opc>/0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex }
// String manipulation.
-cmps, 0xa6, None, 0, W|No_sSuf|RepPrefixOk, {}
-cmps, 0xa6, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-scmp, 0xa6, None, 0, W|No_sSuf|RepPrefixOk, {}
-scmp, 0xa6, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
-ins, 0x6c, None, Cpu186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex }
-outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
-outs, 0x6e, None, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
-lods, 0xac, None, 0, W|No_sSuf|RepPrefixOk, {}
-lods, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-lods, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-slod, 0xac, None, 0, W|No_sSuf|RepPrefixOk, {}
-slod, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-slod, 0xac, None, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-movs, 0xa4, None, 0, W|No_sSuf|RepPrefixOk, {}
-movs, 0xa4, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-smov, 0xa4, None, 0, W|No_sSuf|RepPrefixOk, {}
-smov, 0xa4, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-scas, 0xae, None, 0, W|No_sSuf|RepPrefixOk, {}
-scas, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-scas, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-ssca, 0xae, None, 0, W|No_sSuf|RepPrefixOk, {}
-ssca, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ssca, 0xae, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
-stos, 0xaa, None, 0, W|No_sSuf|RepPrefixOk, {}
-stos, 0xaa, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-stos, 0xaa, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ssto, 0xaa, None, 0, W|No_sSuf|RepPrefixOk, {}
-ssto, 0xaa, None, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ssto, 0xaa, None, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {}
-xlat, 0xd7, None, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex }
+cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk, {}
+cmps, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+scmp, 0xa6, 0, W|No_sSuf|RepPrefixOk, {}
+scmp, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ins, 0x6c, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
+ins, 0x6c, Cpu186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex }
+outs, 0x6e, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
+outs, 0x6e, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
+lods, 0xac, 0, W|No_sSuf|RepPrefixOk, {}
+lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+slod, 0xac, 0, W|No_sSuf|RepPrefixOk, {}
+slod, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+slod, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+movs, 0xa4, 0, W|No_sSuf|RepPrefixOk, {}
+movs, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+smov, 0xa4, 0, W|No_sSuf|RepPrefixOk, {}
+smov, 0xa4, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+scas, 0xae, 0, W|No_sSuf|RepPrefixOk, {}
+scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+scas, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+ssca, 0xae, 0, W|No_sSuf|RepPrefixOk, {}
+ssca, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ssca, 0xae, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
+stos, 0xaa, 0, W|No_sSuf|RepPrefixOk, {}
+stos, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+stos, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ssto, 0xaa, 0, W|No_sSuf|RepPrefixOk, {}
+ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ssto, 0xaa, 0, W|No_sSuf|IsStringEsOp1|RepPrefixOk, { Acc|Byte|Word|Dword|Qword, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf, {}
+xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex }
// Bit manipulation.
-bsf, 0xfbc, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-bsr, 0xfbd, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-bt, 0xfa3, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-bt, 0xfba, 4, Cpu386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-btc, 0xfbb, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-btc, 0xfba, 7, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-btr, 0xfb3, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-btr, 0xfba, 6, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-bts, 0xfab, None, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-bts, 0xfba, 5, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+bsf, 0xfbc, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+bsr, 0xfbd, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+bt, 0xfa3, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+bt, 0xfba/4, Cpu386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+btc, 0xfbb, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+btc, 0xfba/7, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+btr, 0xfb3, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+btr, 0xfba/6, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+bts, 0xfab, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+bts, 0xfba/5, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
// Interrupts & op. sys insns.
// See gas/config/tc-i386.c for conversion of 'int $3' into the special
// int 3 insn.
-int, 0xcd, None, 0, NoSuf, { Imm8 }
-int1, 0xf1, None, 0, NoSuf, {}
-int3, 0xcc, None, 0, NoSuf, {}
-into, 0xce, None, CpuNo64, NoSuf, {}
-iret, 0xcf, None, 0, DefaultSize|No_bSuf|No_sSuf, {}
+int, 0xcd, 0, NoSuf, { Imm8 }
+int1, 0xf1, 0, NoSuf, {}
+int3, 0xcc, 0, NoSuf, {}
+into, 0xce, CpuNo64, NoSuf, {}
+iret, 0xcf, 0, DefaultSize|No_bSuf|No_sSuf, {}
// i386sl, i486sl, later 486, and Pentium.
-rsm, 0xfaa, None, Cpu386, NoSuf, {}
+rsm, 0xfaa, Cpu386, NoSuf, {}
-bound, 0x62, None, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex }
+bound, 0x62, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex }
-hlt, 0xf4, None, 0, NoSuf, {}
+hlt, 0xf4, 0, NoSuf, {}
-nop, 0xf1f, 0, CpuNop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+nop, 0xf1f/0, CpuNop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
// nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
// 32bit mode and "xchg %rax,%rax" in 64bit mode.
-nop, 0x90, None, 0, NoSuf|RepPrefixOk, {}
+nop, 0x90, 0, NoSuf|RepPrefixOk, {}
// Protection control.
-arpl, 0x63, None, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
-lar, 0xf02, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lar, 0xf02, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lgdt, 0xf01, 2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
-lgdt, 0xf01, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-lidt, 0xf01, 3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
-lidt, 0xf01, 3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-lldt, 0xf00, 2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-lmsw, 0xf01, 6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-lsl, 0xf03, None, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lsl, 0xf03, None, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-ltr, 0xf00, 3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-
-sgdt, 0xf01, 0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
-sgdt, 0xf01, 0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-sidt, 0xf01, 1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
-sidt, 0xf01, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-sldt, 0xf00, 0, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
-sldt, 0xf00, 0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-smsw, 0xf01, 4, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 }
-smsw, 0xf01, 4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-str, 0xf00, 1, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
-str, 0xf00, 1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+arpl, 0x63, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
+lar, 0xf02, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lar, 0xf02, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lgdt, 0xf01/2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+lgdt, 0xf01/2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
+lidt, 0xf01/3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+lidt, 0xf01/3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
+lldt, 0xf00/2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+lmsw, 0xf01/6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+lsl, 0xf03, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lsl, 0xf03, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+ltr, 0xf00/3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+
+sgdt, 0xf01/0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+sgdt, 0xf01/0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
+sidt, 0xf01/1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+sidt, 0xf01/1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
+sldt, 0xf00/0, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+sldt, 0xf00/0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+smsw, 0xf01/4, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 }
+smsw, 0xf01/4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+str, 0xf00/1, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+str, 0xf00/1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-verr, 0xf00, 4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-verw, 0xf00, 5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+verr, 0xf00/4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+verw, 0xf00/5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
// Floating point instructions.
// load
-fld, 0xd9c0, None, CpuFP, NoSuf, { FloatReg }
-fld, 0xd9, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fld, 0xd9c0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+fld, 0xd9c0, CpuFP, NoSuf, { FloatReg }
+fld, 0xd9/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fld, 0xd9c0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
// Intel Syntax
-fld, 0xdb, 5, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
-fild, 0xdf, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fild, 0xdf, 5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex }
-fildll, 0xdf, 5, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex }
-fldt, 0xdb, 5, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex }
-fbld, 0xdf, 4, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
+fld, 0xdb/5, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
+fild, 0xdf/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fild, 0xdf/5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex }
+fildll, 0xdf/5, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex }
+fldt, 0xdb/5, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex }
+fbld, 0xdf/4, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
// store (no pop)
-fst, 0xddd0, None, CpuFP, NoSuf, { FloatReg }
-fst, 0xd9, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fst, 0xddd0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
-fist, 0xdf, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fst, 0xddd0, CpuFP, NoSuf, { FloatReg }
+fst, 0xd9/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fst, 0xddd0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+fist, 0xdf/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
// store (with pop)
-fstp, 0xddd8, None, CpuFP, NoSuf, { FloatReg }
-fstp, 0xd9, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fstp, 0xddd8, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+fstp, 0xddd8, CpuFP, NoSuf, { FloatReg }
+fstp, 0xd9/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fstp, 0xddd8, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
// Intel Syntax
-fstp, 0xdb, 7, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
-fistp, 0xdf, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fistp, 0xdf, 7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex }
-fistpll, 0xdf, 7, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex }
-fstpt, 0xdb, 7, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex }
-fbstp, 0xdf, 6, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
+fstp, 0xdb/7, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
+fistp, 0xdf/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fistp, 0xdf/7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex }
+fistpll, 0xdf/7, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex }
+fstpt, 0xdb/7, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex }
+fbstp, 0xdf/6, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
// exchange %st<n> with %st0
-fxch, 0xd9c8, None, CpuFP, NoSuf, { FloatReg }
+fxch, 0xd9c8, CpuFP, NoSuf, { FloatReg }
// alias for fxch %st(1)
-fxch, 0xd9c9, None, CpuFP, NoSuf, {}
+fxch, 0xd9c9, CpuFP, NoSuf, {}
// comparison (without pop)
-fcom, 0xd8d0, None, CpuFP, NoSuf, { FloatReg }
+fcom, 0xd8d0, CpuFP, NoSuf, { FloatReg }
// alias for fcom %st(1)
-fcom, 0xd8d1, None, CpuFP, NoSuf, {}
-fcom, 0xd8, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fcom, 0xd8d0, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
-ficom, 0xde, 2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fcom, 0xd8d1, CpuFP, NoSuf, {}
+fcom, 0xd8/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fcom, 0xd8d0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+ficom, 0xde/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
// comparison (with pop)
-fcomp, 0xd8d8, None, CpuFP, NoSuf, { FloatReg }
+fcomp, 0xd8d8, CpuFP, NoSuf, { FloatReg }
// alias for fcomp %st(1)
-fcomp, 0xd8d9, None, CpuFP, NoSuf, {}
-fcomp, 0xd8, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fcomp, 0xd8d8, None, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
-ficomp, 0xde, 3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fcompp, 0xded9, None, CpuFP, NoSuf, {}
+fcomp, 0xd8d9, CpuFP, NoSuf, {}
+fcomp, 0xd8/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fcomp, 0xd8d8, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+ficomp, 0xde/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fcompp, 0xded9, CpuFP, NoSuf, {}
// unordered comparison (with pop)
-fucom, 0xdde0, None, Cpu387, NoSuf, { FloatReg }
+fucom, 0xdde0, Cpu387, NoSuf, { FloatReg }
// alias for fucom %st(1)
-fucom, 0xdde1, None, Cpu387, NoSuf, {}
-fucomp, 0xdde8, None, Cpu387, NoSuf, { FloatReg }
+fucom, 0xdde1, Cpu387, NoSuf, {}
+fucomp, 0xdde8, Cpu387, NoSuf, { FloatReg }
// alias for fucomp %st(1)
-fucomp, 0xdde9, None, Cpu387, NoSuf, {}
-fucompp, 0xdae9, None, Cpu387, NoSuf, {}
+fucomp, 0xdde9, Cpu387, NoSuf, {}
+fucompp, 0xdae9, Cpu387, NoSuf, {}
-ftst, 0xd9e4, None, CpuFP, NoSuf, {}
-fxam, 0xd9e5, None, CpuFP, NoSuf, {}
+ftst, 0xd9e4, CpuFP, NoSuf, {}
+fxam, 0xd9e5, CpuFP, NoSuf, {}
// load constants into %st0
-fld1, 0xd9e8, None, CpuFP, NoSuf, {}
-fldl2t, 0xd9e9, None, CpuFP, NoSuf, {}
-fldl2e, 0xd9ea, None, CpuFP, NoSuf, {}
-fldpi, 0xd9eb, None, CpuFP, NoSuf, {}
-fldlg2, 0xd9ec, None, CpuFP, NoSuf, {}
-fldln2, 0xd9ed, None, CpuFP, NoSuf, {}
-fldz, 0xd9ee, None, CpuFP, NoSuf, {}
+fld1, 0xd9e8, CpuFP, NoSuf, {}
+fldl2t, 0xd9e9, CpuFP, NoSuf, {}
+fldl2e, 0xd9ea, CpuFP, NoSuf, {}
+fldpi, 0xd9eb, CpuFP, NoSuf, {}
+fldlg2, 0xd9ec, CpuFP, NoSuf, {}
+fldln2, 0xd9ed, CpuFP, NoSuf, {}
+fldz, 0xd9ee, CpuFP, NoSuf, {}
// Arithmetic.
// add
-fadd, 0xd8c0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fadd, 0xd8c0, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fadd %st(i), %st
-fadd, 0xd8c0, None, CpuFP, NoSuf, { FloatReg }
+fadd, 0xd8c0, CpuFP, NoSuf, { FloatReg }
// alias for faddp
-fadd, 0xdec1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fadd, 0xd8, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fiadd, 0xde, 0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fadd, 0xdec1, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
+fadd, 0xd8/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fiadd, 0xde/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-faddp, 0xdec0, None, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg }
-faddp, 0xdec0, None, CpuFP, NoSuf, { FloatReg }
+faddp, 0xdec0, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg }
+faddp, 0xdec0, CpuFP, NoSuf, { FloatReg }
// alias for faddp %st, %st(1)
-faddp, 0xdec1, None, CpuFP, NoSuf, {}
+faddp, 0xdec1, CpuFP, NoSuf, {}
// subtract
-fsub, 0xd8e0, None, CpuFP, NoSuf, { FloatReg }
-fsub, 0xd8e0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fsub, 0xd8e0, CpuFP, NoSuf, { FloatReg }
+fsub, 0xd8e0, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fsubp
-fsub, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fsub, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fsub, 0xd8, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fisub, 0xde, 4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-
-fsubp, 0xdee0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fsubp, 0xdee0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fsubp, 0xdee1, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
-fsubp, 0xdee8, None, CpuFP, NoSuf, { FloatAcc, FloatReg }
-fsubp, 0xdee8, None, CpuFP, NoSuf, { FloatReg }
-fsubp, 0xdee9, None, CpuFP, NoSuf, {}
+fsub, 0xdee1, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
+fsub, 0xdee9, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
+fsub, 0xd8/4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fisub, 0xde/4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+
+fsubp, 0xdee0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fsubp, 0xdee0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fsubp, 0xdee1, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fsubp, 0xdee8, CpuFP, NoSuf, { FloatAcc, FloatReg }
+fsubp, 0xdee8, CpuFP, NoSuf, { FloatReg }
+fsubp, 0xdee9, CpuFP, NoSuf, {}
// subtract reverse
-fsubr, 0xd8e8, None, CpuFP, NoSuf, { FloatReg }
-fsubr, 0xd8e8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fsubr, 0xd8e8, CpuFP, NoSuf, { FloatReg }
+fsubr, 0xd8e8, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fsubrp
-fsubr, 0xdee9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fsubr, 0xdee1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fsubr, 0xd8, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fisubr, 0xde, 5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-
-fsubrp, 0xdee8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fsubrp, 0xdee8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fsubrp, 0xdee9, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
-fsubrp, 0xdee0, None, CpuFP, NoSuf, { FloatAcc, FloatReg }
-fsubrp, 0xdee0, None, CpuFP, NoSuf, { FloatReg }
-fsubrp, 0xdee1, None, CpuFP, NoSuf, {}
+fsubr, 0xdee9, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
+fsubr, 0xdee1, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
+fsubr, 0xd8/5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fisubr, 0xde/5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+
+fsubrp, 0xdee8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fsubrp, 0xdee8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fsubrp, 0xdee9, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fsubrp, 0xdee0, CpuFP, NoSuf, { FloatAcc, FloatReg }
+fsubrp, 0xdee0, CpuFP, NoSuf, { FloatReg }
+fsubrp, 0xdee1, CpuFP, NoSuf, {}
// multiply
-fmul, 0xd8c8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
-fmul, 0xd8c8, None, CpuFP, NoSuf, { FloatReg }
+fmul, 0xd8c8, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fmul, 0xd8c8, CpuFP, NoSuf, { FloatReg }
// alias for fmulp
-fmul, 0xdec9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fmul, 0xd8, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fimul, 0xde, 1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fmul, 0xdec9, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
+fmul, 0xd8/1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fimul, 0xde/1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fmulp, 0xdec8, None, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg }
-fmulp, 0xdec8, None, CpuFP, NoSuf, { FloatReg }
+fmulp, 0xdec8, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg }
+fmulp, 0xdec8, CpuFP, NoSuf, { FloatReg }
// alias for fmulp %st, %st(1)
-fmulp, 0xdec9, None, CpuFP, NoSuf, {}
+fmulp, 0xdec9, CpuFP, NoSuf, {}
// divide
-fdiv, 0xd8f0, None, CpuFP, NoSuf, { FloatReg }
-fdiv, 0xd8f0, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fdiv, 0xd8f0, CpuFP, NoSuf, { FloatReg }
+fdiv, 0xd8f0, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fdivp
-fdiv, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fdiv, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fdiv, 0xd8, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fidiv, 0xde, 6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-
-fdivp, 0xdef0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fdivp, 0xdef0, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fdivp, 0xdef1, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
-fdivp, 0xdef8, None, CpuFP, NoSuf, { FloatAcc, FloatReg }
-fdivp, 0xdef8, None, CpuFP, NoSuf, { FloatReg }
-fdivp, 0xdef9, None, CpuFP, NoSuf, {}
+fdiv, 0xdef1, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
+fdiv, 0xdef9, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
+fdiv, 0xd8/6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fidiv, 0xde/6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+
+fdivp, 0xdef0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fdivp, 0xdef0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fdivp, 0xdef1, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fdivp, 0xdef8, CpuFP, NoSuf, { FloatAcc, FloatReg }
+fdivp, 0xdef8, CpuFP, NoSuf, { FloatReg }
+fdivp, 0xdef9, CpuFP, NoSuf, {}
// divide reverse
-fdivr, 0xd8f8, None, CpuFP, NoSuf, { FloatReg }
-fdivr, 0xd8f8, None, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fdivr, 0xd8f8, CpuFP, NoSuf, { FloatReg }
+fdivr, 0xd8f8, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fdivrp
-fdivr, 0xdef9, None, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fdivr, 0xdef1, None, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fdivr, 0xd8, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fidivr, 0xde, 7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-
-fdivrp, 0xdef8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fdivrp, 0xdef8, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fdivrp, 0xdef9, None, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
-fdivrp, 0xdef0, None, CpuFP, NoSuf, { FloatAcc, FloatReg }
-fdivrp, 0xdef0, None, CpuFP, NoSuf, { FloatReg }
-fdivrp, 0xdef1, None, CpuFP, NoSuf, {}
-
-f2xm1, 0xd9f0, None, CpuFP, NoSuf, {}
-fyl2x, 0xd9f1, None, CpuFP, NoSuf, {}
-fptan, 0xd9f2, None, CpuFP, NoSuf, {}
-fpatan, 0xd9f3, None, CpuFP, NoSuf, {}
-fxtract, 0xd9f4, None, CpuFP, NoSuf, {}
-fprem1, 0xd9f5, None, Cpu387, NoSuf, {}
-fdecstp, 0xd9f6, None, CpuFP, NoSuf, {}
-fincstp, 0xd9f7, None, CpuFP, NoSuf, {}
-fprem, 0xd9f8, None, CpuFP, NoSuf, {}
-fyl2xp1, 0xd9f9, None, CpuFP, NoSuf, {}
-fsqrt, 0xd9fa, None, CpuFP, NoSuf, {}
-fsincos, 0xd9fb, None, Cpu387, NoSuf, {}
-frndint, 0xd9fc, None, CpuFP, NoSuf, {}
-fscale, 0xd9fd, None, CpuFP, NoSuf, {}
-fsin, 0xd9fe, None, Cpu387, NoSuf, {}
-fcos, 0xd9ff, None, Cpu387, NoSuf, {}
-fchs, 0xd9e0, None, CpuFP, NoSuf, {}
-fabs, 0xd9e1, None, CpuFP, NoSuf, {}
+fdivr, 0xdef9, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
+fdivr, 0xdef1, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
+fdivr, 0xd8/7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fidivr, 0xde/7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+
+fdivrp, 0xdef8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fdivrp, 0xdef8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fdivrp, 0xdef9, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fdivrp, 0xdef0, CpuFP, NoSuf, { FloatAcc, FloatReg }
+fdivrp, 0xdef0, CpuFP, NoSuf, { FloatReg }
+fdivrp, 0xdef1, CpuFP, NoSuf, {}
+
+f2xm1, 0xd9f0, CpuFP, NoSuf, {}
+fyl2x, 0xd9f1, CpuFP, NoSuf, {}
+fptan, 0xd9f2, CpuFP, NoSuf, {}
+fpatan, 0xd9f3, CpuFP, NoSuf, {}
+fxtract, 0xd9f4, CpuFP, NoSuf, {}
+fprem1, 0xd9f5, Cpu387, NoSuf, {}
+fdecstp, 0xd9f6, CpuFP, NoSuf, {}
+fincstp, 0xd9f7, CpuFP, NoSuf, {}
+fprem, 0xd9f8, CpuFP, NoSuf, {}
+fyl2xp1, 0xd9f9, CpuFP, NoSuf, {}
+fsqrt, 0xd9fa, CpuFP, NoSuf, {}
+fsincos, 0xd9fb, Cpu387, NoSuf, {}
+frndint, 0xd9fc, CpuFP, NoSuf, {}
+fscale, 0xd9fd, CpuFP, NoSuf, {}
+fsin, 0xd9fe, Cpu387, NoSuf, {}
+fcos, 0xd9ff, Cpu387, NoSuf, {}
+fchs, 0xd9e0, CpuFP, NoSuf, {}
+fabs, 0xd9e1, CpuFP, NoSuf, {}
// processor control
-fninit, 0xdbe3, None, CpuFP, NoSuf, {}
-finit, 0xdbe3, None, CpuFP, NoSuf|FWait, {}
-fldcw, 0xd9, 5, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-fnstcw, 0xd9, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-fstcw, 0xd9, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex }
-fnstsw, 0xdfe0, None, Cpu287|Cpu387, IgnoreSize|NoSuf, { Acc|Word }
-fnstsw, 0xdd, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-fnstsw, 0xdfe0, None, Cpu287|Cpu387, NoSuf, {}
-fstsw, 0xdfe0, None, Cpu287|Cpu387, IgnoreSize|NoSuf|FWait, { Acc|Word }
-fstsw, 0xdd, 7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex }
-fstsw, 0xdfe0, None, Cpu287|Cpu387, NoSuf|FWait, {}
-fnclex, 0xdbe2, None, CpuFP, NoSuf, {}
-fclex, 0xdbe2, None, CpuFP, NoSuf|FWait, {}
+fninit, 0xdbe3, CpuFP, NoSuf, {}
+finit, 0xdbe3, CpuFP, NoSuf|FWait, {}
+fldcw, 0xd9/5, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+fnstcw, 0xd9/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+fstcw, 0xd9/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex }
+fnstsw, 0xdfe0, Cpu287|Cpu387, IgnoreSize|NoSuf, { Acc|Word }
+fnstsw, 0xdd/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+fnstsw, 0xdfe0, Cpu287|Cpu387, NoSuf, {}
+fstsw, 0xdfe0, Cpu287|Cpu387, IgnoreSize|NoSuf|FWait, { Acc|Word }
+fstsw, 0xdd/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex }
+fstsw, 0xdfe0, Cpu287|Cpu387, NoSuf|FWait, {}
+fnclex, 0xdbe2, CpuFP, NoSuf, {}
+fclex, 0xdbe2, CpuFP, NoSuf|FWait, {}
// Short forms of fldenv, fstenv, fsave, and frstor use data size prefix.
-fnstenv, 0xd9, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fstenv, 0xd9, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
-fldenv, 0xd9, 4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fnsave, 0xdd, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fsave, 0xdd, 6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
-frstor, 0xdd, 4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fnstenv, 0xd9/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fstenv, 0xd9/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
+fldenv, 0xd9/4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fnsave, 0xdd/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fsave, 0xdd/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
+frstor, 0xdd/4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
// 8087 only
-fneni, 0xdbe0, None, Cpu8087, NoSuf, {}
-feni, 0xdbe0, None, Cpu8087, NoSuf|FWait, {}
-fndisi, 0xdbe1, None, Cpu8087, NoSuf, {}
-fdisi, 0xdbe1, None, Cpu8087, NoSuf|FWait, {}
+fneni, 0xdbe0, Cpu8087, NoSuf, {}
+feni, 0xdbe0, Cpu8087, NoSuf|FWait, {}
+fndisi, 0xdbe1, Cpu8087, NoSuf, {}
+fdisi, 0xdbe1, Cpu8087, NoSuf|FWait, {}
// 287 only
-fnsetpm, 0xdbe4, None, Cpu287, NoSuf, {}
-fsetpm, 0xdbe4, None, Cpu287, NoSuf|FWait, {}
-frstpm, 0xdbe5, None, Cpu287, NoSuf, {}
+fnsetpm, 0xdbe4, Cpu287, NoSuf, {}
+fsetpm, 0xdbe4, Cpu287, NoSuf|FWait, {}
+frstpm, 0xdbe5, Cpu287, NoSuf, {}
-ffree, 0xddc0, None, CpuFP, NoSuf, { FloatReg }
+ffree, 0xddc0, CpuFP, NoSuf, { FloatReg }
// P6:free st(i), pop st
-ffreep, 0xdfc0, None, Cpu687, NoSuf, { FloatReg }
-fnop, 0xd9d0, None, CpuFP, NoSuf, {}
-fwait, 0x9b, None, CpuFP, NoSuf, {}
+ffreep, 0xdfc0, Cpu687, NoSuf, { FloatReg }
+fnop, 0xd9d0, CpuFP, NoSuf, {}
+fwait, 0x9b, CpuFP, NoSuf, {}
// Opcode prefixes; we allow them as separate insns too.
-addr16, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {}
-addr32, 0x67, None, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {}
-aword, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {}
-adword, 0x67, None, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {}
-data16, 0x66, None, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {}
-data32, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {}
-word, 0x66, None, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {}
-dword, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {}
-lock, 0xf0, None, 0, NoSuf|IsPrefix, {}
-wait, 0x9b, None, 0, NoSuf|IsPrefix, {}
-cs, 0x2e, None, 0, NoSuf|IsPrefix, {}
-ds, 0x3e, None, 0, NoSuf|IsPrefix, {}
-es, 0x26, None, CpuNo64, NoSuf|IsPrefix, {}
-fs, 0x64, None, Cpu386, NoSuf|IsPrefix, {}
-gs, 0x65, None, Cpu386, NoSuf|IsPrefix, {}
-ss, 0x36, None, CpuNo64, NoSuf|IsPrefix, {}
-rep, 0xf3, None, 0, NoSuf|IsPrefix, {}
-repe, 0xf3, None, 0, NoSuf|IsPrefix, {}
-repz, 0xf3, None, 0, NoSuf|IsPrefix, {}
-repne, 0xf2, None, 0, NoSuf|IsPrefix, {}
-repnz, 0xf2, None, 0, NoSuf|IsPrefix, {}
-ht, 0x3e, None, 0, NoSuf|IsPrefix, {}
-hnt, 0x2e, None, 0, NoSuf|IsPrefix, {}
-rex, 0x40, None, Cpu64, NoSuf|IsPrefix, {}
-rexz, 0x41, None, Cpu64, NoSuf|IsPrefix, {}
-rexy, 0x42, None, Cpu64, NoSuf|IsPrefix, {}
-rexyz, 0x43, None, Cpu64, NoSuf|IsPrefix, {}
-rexx, 0x44, None, Cpu64, NoSuf|IsPrefix, {}
-rexxz, 0x45, None, Cpu64, NoSuf|IsPrefix, {}
-rexxy, 0x46, None, Cpu64, NoSuf|IsPrefix, {}
-rexxyz, 0x47, None, Cpu64, NoSuf|IsPrefix, {}
-rex64, 0x48, None, Cpu64, NoSuf|IsPrefix, {}
-rex64z, 0x49, None, Cpu64, NoSuf|IsPrefix, {}
-rex64y, 0x4a, None, Cpu64, NoSuf|IsPrefix, {}
-rex64yz, 0x4b, None, Cpu64, NoSuf|IsPrefix, {}
-rex64x, 0x4c, None, Cpu64, NoSuf|IsPrefix, {}
-rex64xz, 0x4d, None, Cpu64, NoSuf|IsPrefix, {}
-rex64xy, 0x4e, None, Cpu64, NoSuf|IsPrefix, {}
-rex64xyz, 0x4f, None, Cpu64, NoSuf|IsPrefix, {}
-rex.b, 0x41, None, Cpu64, NoSuf|IsPrefix, {}
-rex.x, 0x42, None, Cpu64, NoSuf|IsPrefix, {}
-rex.xb, 0x43, None, Cpu64, NoSuf|IsPrefix, {}
-rex.r, 0x44, None, Cpu64, NoSuf|IsPrefix, {}
-rex.rb, 0x45, None, Cpu64, NoSuf|IsPrefix, {}
-rex.rx, 0x46, None, Cpu64, NoSuf|IsPrefix, {}
-rex.rxb, 0x47, None, Cpu64, NoSuf|IsPrefix, {}
-rex.w, 0x48, None, Cpu64, NoSuf|IsPrefix, {}
-rex.wb, 0x49, None, Cpu64, NoSuf|IsPrefix, {}
-rex.wx, 0x4a, None, Cpu64, NoSuf|IsPrefix, {}
-rex.wxb, 0x4b, None, Cpu64, NoSuf|IsPrefix, {}
-rex.wr, 0x4c, None, Cpu64, NoSuf|IsPrefix, {}
-rex.wrb, 0x4d, None, Cpu64, NoSuf|IsPrefix, {}
-rex.wrx, 0x4e, None, Cpu64, NoSuf|IsPrefix, {}
-rex.wrxb, 0x4f, None, Cpu64, NoSuf|IsPrefix, {}
+addr16, 0x67, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {}
+addr32, 0x67, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {}
+aword, 0x67, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {}
+adword, 0x67, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {}
+data16, 0x66, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {}
+data32, 0x66, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {}
+word, 0x66, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {}
+dword, 0x66, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {}
+lock, 0xf0, 0, NoSuf|IsPrefix, {}
+wait, 0x9b, 0, NoSuf|IsPrefix, {}
+cs, 0x2e, 0, NoSuf|IsPrefix, {}
+ds, 0x3e, 0, NoSuf|IsPrefix, {}
+es, 0x26, CpuNo64, NoSuf|IsPrefix, {}
+fs, 0x64, Cpu386, NoSuf|IsPrefix, {}
+gs, 0x65, Cpu386, NoSuf|IsPrefix, {}
+ss, 0x36, CpuNo64, NoSuf|IsPrefix, {}
+rep, 0xf3, 0, NoSuf|IsPrefix, {}
+repe, 0xf3, 0, NoSuf|IsPrefix, {}
+repz, 0xf3, 0, NoSuf|IsPrefix, {}
+repne, 0xf2, 0, NoSuf|IsPrefix, {}
+repnz, 0xf2, 0, NoSuf|IsPrefix, {}
+ht, 0x3e, 0, NoSuf|IsPrefix, {}
+hnt, 0x2e, 0, NoSuf|IsPrefix, {}
+rex, 0x40, Cpu64, NoSuf|IsPrefix, {}
+rexz, 0x41, Cpu64, NoSuf|IsPrefix, {}
+rexy, 0x42, Cpu64, NoSuf|IsPrefix, {}
+rexyz, 0x43, Cpu64, NoSuf|IsPrefix, {}
+rexx, 0x44, Cpu64, NoSuf|IsPrefix, {}
+rexxz, 0x45, Cpu64, NoSuf|IsPrefix, {}
+rexxy, 0x46, Cpu64, NoSuf|IsPrefix, {}
+rexxyz, 0x47, Cpu64, NoSuf|IsPrefix, {}
+rex64, 0x48, Cpu64, NoSuf|IsPrefix, {}
+rex64z, 0x49, Cpu64, NoSuf|IsPrefix, {}
+rex64y, 0x4a, Cpu64, NoSuf|IsPrefix, {}
+rex64yz, 0x4b, Cpu64, NoSuf|IsPrefix, {}
+rex64x, 0x4c, Cpu64, NoSuf|IsPrefix, {}
+rex64xz, 0x4d, Cpu64, NoSuf|IsPrefix, {}
+rex64xy, 0x4e, Cpu64, NoSuf|IsPrefix, {}
+rex64xyz, 0x4f, Cpu64, NoSuf|IsPrefix, {}
+rex.b, 0x41, Cpu64, NoSuf|IsPrefix, {}
+rex.x, 0x42, Cpu64, NoSuf|IsPrefix, {}
+rex.xb, 0x43, Cpu64, NoSuf|IsPrefix, {}
+rex.r, 0x44, Cpu64, NoSuf|IsPrefix, {}
+rex.rb, 0x45, Cpu64, NoSuf|IsPrefix, {}
+rex.rx, 0x46, Cpu64, NoSuf|IsPrefix, {}
+rex.rxb, 0x47, Cpu64, NoSuf|IsPrefix, {}
+rex.w, 0x48, Cpu64, NoSuf|IsPrefix, {}
+rex.wb, 0x49, Cpu64, NoSuf|IsPrefix, {}
+rex.wx, 0x4a, Cpu64, NoSuf|IsPrefix, {}
+rex.wxb, 0x4b, Cpu64, NoSuf|IsPrefix, {}
+rex.wr, 0x4c, Cpu64, NoSuf|IsPrefix, {}
+rex.wrb, 0x4d, Cpu64, NoSuf|IsPrefix, {}
+rex.wrx, 0x4e, Cpu64, NoSuf|IsPrefix, {}
+rex.wrxb, 0x4f, Cpu64, NoSuf|IsPrefix, {}
// Pseudo prefixes (base_opcode == PSEUDO_PREFIX)
@@ ...
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/2] x86: omit Cpu prefixes from opcode table
2022-12-12 13:10 [PATCH 0/2] x86: further opcode table line length reduction Jan Beulich
2022-12-12 13:12 ` [PATCH 1/2] x86: change representation of extension opcode Jan Beulich
@ 2022-12-12 13:14 ` Jan Beulich
2022-12-13 7:29 ` Jan Beulich
1 sibling, 1 reply; 4+ messages in thread
From: Jan Beulich @ 2022-12-12 13:14 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
These enumerators can be used in only one specific field, and hence the
Cpu prefix isn't needed ther for disambiguation / name space separation.
---
RFC: I will admit that I'm not entirely happy with the result,
specifically because of the purely numeric "identifiers" which we
end up with now (e.g. 286 or 64). Since for things like AVX the
change is (imo) a clear improvement, I wonder whether some hybrid
approach might be best to take, or whether we could go with e.g.
CpuI286 and CpuX64.
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -46,435 +46,435 @@ typedef struct initializer
static initializer cpu_flag_init[] =
{
{ "CPU_UNKNOWN_FLAGS",
- "~CpuIAMCU" },
+ "~IAMCU" },
{ "CPU_GENERIC32_FLAGS",
- "Cpu186|Cpu286|Cpu386" },
+ "186|286|386" },
{ "CPU_GENERIC64_FLAGS",
- "CPU_PENTIUMPRO_FLAGS|CpuClflush|CpuSYSCALL|CPU_MMX_FLAGS|CPU_SSE2_FLAGS|CpuLM" },
+ "CPU_PENTIUMPRO_FLAGS|Clflush|SYSCALL|CPU_MMX_FLAGS|CPU_SSE2_FLAGS|LM" },
{ "CPU_NONE_FLAGS",
"0" },
{ "CPU_I186_FLAGS",
- "Cpu186" },
+ "186" },
{ "CPU_I286_FLAGS",
- "CPU_I186_FLAGS|Cpu286" },
+ "CPU_I186_FLAGS|286" },
{ "CPU_I386_FLAGS",
- "CPU_I286_FLAGS|Cpu386" },
+ "CPU_I286_FLAGS|386" },
{ "CPU_I486_FLAGS",
- "CPU_I386_FLAGS|Cpu486" },
+ "CPU_I386_FLAGS|486" },
{ "CPU_I586_FLAGS",
- "CPU_I486_FLAGS|Cpu387|Cpu586" },
+ "CPU_I486_FLAGS|387|586" },
{ "CPU_I686_FLAGS",
- "CPU_I586_FLAGS|Cpu686|Cpu687|CpuCMOV|CpuFXSR" },
+ "CPU_I586_FLAGS|686|687|CMOV|FXSR" },
{ "CPU_PENTIUMPRO_FLAGS",
- "CPU_I686_FLAGS|CpuNop" },
+ "CPU_I686_FLAGS|Nop" },
{ "CPU_P2_FLAGS",
"CPU_PENTIUMPRO_FLAGS|CPU_MMX_FLAGS" },
{ "CPU_P3_FLAGS",
"CPU_P2_FLAGS|CPU_SSE_FLAGS" },
{ "CPU_P4_FLAGS",
- "CPU_P3_FLAGS|CpuClflush|CPU_SSE2_FLAGS" },
+ "CPU_P3_FLAGS|Clflush|CPU_SSE2_FLAGS" },
{ "CPU_NOCONA_FLAGS",
- "CPU_GENERIC64_FLAGS|CpuFISTTP|CPU_SSE3_FLAGS|CpuCX16" },
+ "CPU_GENERIC64_FLAGS|FISTTP|CPU_SSE3_FLAGS|CX16" },
{ "CPU_CORE_FLAGS",
- "CPU_P4_FLAGS|CpuFISTTP|CPU_SSE3_FLAGS|CpuCX16" },
+ "CPU_P4_FLAGS|FISTTP|CPU_SSE3_FLAGS|CX16" },
{ "CPU_CORE2_FLAGS",
"CPU_NOCONA_FLAGS|CPU_SSSE3_FLAGS" },
{ "CPU_COREI7_FLAGS",
- "CPU_CORE2_FLAGS|CPU_SSE4_2_FLAGS|CpuRdtscp" },
+ "CPU_CORE2_FLAGS|CPU_SSE4_2_FLAGS|Rdtscp" },
{ "CPU_K6_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuSYSCALL|Cpu387|CPU_MMX_FLAGS" },
+ "186|286|386|486|586|SYSCALL|387|CPU_MMX_FLAGS" },
{ "CPU_K6_2_FLAGS",
- "CPU_K6_FLAGS|Cpu3dnow" },
+ "CPU_K6_FLAGS|3dnow" },
{ "CPU_ATHLON_FLAGS",
- "CPU_K6_2_FLAGS|Cpu686|Cpu687|CpuNop|Cpu3dnowA" },
+ "CPU_K6_2_FLAGS|686|687|Nop|3dnowA" },
{ "CPU_K8_FLAGS",
- "CPU_ATHLON_FLAGS|CpuRdtscp|CPU_SSE2_FLAGS|CpuLM" },
+ "CPU_ATHLON_FLAGS|Rdtscp|CPU_SSE2_FLAGS|LM" },
{ "CPU_AMDFAM10_FLAGS",
- "CPU_K8_FLAGS|CpuFISTTP|CPU_SSE4A_FLAGS|CpuLZCNT|CpuPOPCNT" },
+ "CPU_K8_FLAGS|FISTTP|CPU_SSE4A_FLAGS|LZCNT|POPCNT" },
{ "CPU_BDVER1_FLAGS",
- "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_XOP_FLAGS|CpuLZCNT|CpuPOPCNT|CpuLWP|CpuSVME|CpuAES|CpuPCLMUL|CpuPRFCHW" },
+ "CPU_GENERIC64_FLAGS|FISTTP|Rdtscp|CX16|CPU_XOP_FLAGS|LZCNT|POPCNT|LWP|SVME|AES|PCLMUL|PRFCHW" },
{ "CPU_BDVER2_FLAGS",
- "CPU_BDVER1_FLAGS|CpuFMA|CpuBMI|CpuTBM|CpuF16C" },
+ "CPU_BDVER1_FLAGS|FMA|BMI|TBM|F16C" },
{ "CPU_BDVER3_FLAGS",
- "CPU_BDVER2_FLAGS|CpuXsaveopt|CpuFSGSBase" },
+ "CPU_BDVER2_FLAGS|Xsaveopt|FSGSBase" },
{ "CPU_BDVER4_FLAGS",
- "CPU_BDVER3_FLAGS|CpuAVX2|CpuMovbe|CpuBMI2|CpuRdRnd|CpuMWAITX" },
+ "CPU_BDVER3_FLAGS|AVX2|Movbe|BMI2|RdRnd|MWAITX" },
{ "CPU_ZNVER1_FLAGS",
- "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuRdtscp|CpuCX16|CPU_AVX2_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuSVME|CpuAES|CpuPCLMUL|CpuPRFCHW|CpuFMA|CpuBMI|CpuF16C|CpuXsaveopt|CpuFSGSBase|CpuMovbe|CpuBMI2|CpuRdRnd|CpuADX|CpuRdSeed|CpuSMAP|CpuSHA|CpuXSAVEC|CpuXSAVES|CpuClflushOpt|CpuCLZERO|CpuMWAITX" },
+ "CPU_GENERIC64_FLAGS|FISTTP|Rdtscp|CX16|CPU_AVX2_FLAGS|SSE4A|LZCNT|POPCNT|SVME|AES|PCLMUL|PRFCHW|FMA|BMI|F16C|Xsaveopt|FSGSBase|Movbe|BMI2|RdRnd|ADX|RdSeed|SMAP|SHA|XSAVEC|XSAVES|ClflushOpt|CLZERO|MWAITX" },
{ "CPU_ZNVER2_FLAGS",
- "CPU_ZNVER1_FLAGS|CpuCLWB|CpuRDPID|CpuRDPRU|CpuMCOMMIT|CpuWBNOINVD" },
+ "CPU_ZNVER1_FLAGS|CLWB|RDPID|RDPRU|MCOMMIT|WBNOINVD" },
{ "CPU_ZNVER3_FLAGS",
- "CPU_ZNVER2_FLAGS|CpuINVLPGB|CpuTLBSYNC|CpuVAES|CpuVPCLMULQDQ|CpuINVPCID|CpuSNP|CpuOSPKE" },
+ "CPU_ZNVER2_FLAGS|INVLPGB|TLBSYNC|VAES|VPCLMULQDQ|INVPCID|SNP|OSPKE" },
{ "CPU_ZNVER4_FLAGS",
- "CPU_ZNVER3_FLAGS|CpuAVX512F|CpuAVX512DQ|CpuAVX512IFMA|CpuAVX512CD|CpuAVX512BW|CpuAVX512VL|CpuAVX512_BF16|CpuAVX512VBMI|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_VPOPCNTDQ|CpuGFNI|CpuRMPQUERY" },
+ "CPU_ZNVER3_FLAGS|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
{ "CPU_BTVER1_FLAGS",
- "CPU_GENERIC64_FLAGS|CpuFISTTP|CpuCX16|CpuRdtscp|CPU_SSSE3_FLAGS|CpuSSE4A|CpuLZCNT|CpuPOPCNT|CpuPRFCHW|CpuCX16|CpuClflush|CpuFISTTP|CpuSVME" },
+ "CPU_GENERIC64_FLAGS|FISTTP|CX16|Rdtscp|CPU_SSSE3_FLAGS|SSE4A|LZCNT|POPCNT|PRFCHW|CX16|Clflush|FISTTP|SVME" },
{ "CPU_BTVER2_FLAGS",
- "CPU_BTVER1_FLAGS|CPU_AVX_FLAGS|CpuBMI|CpuF16C|CpuAES|CpuPCLMUL|CpuMovbe|CpuXsaveopt|CpuPRFCHW" },
+ "CPU_BTVER1_FLAGS|CPU_AVX_FLAGS|BMI|F16C|AES|PCLMUL|Movbe|Xsaveopt|PRFCHW" },
{ "CPU_8087_FLAGS",
- "Cpu8087" },
+ "8087" },
{ "CPU_287_FLAGS",
- "Cpu287" },
+ "287" },
{ "CPU_387_FLAGS",
- "Cpu387" },
+ "387" },
{ "CPU_687_FLAGS",
- "CPU_387_FLAGS|Cpu687" },
+ "CPU_387_FLAGS|687" },
{ "CPU_CMOV_FLAGS",
- "CpuCMOV" },
+ "CMOV" },
{ "CPU_FXSR_FLAGS",
- "CpuFXSR" },
+ "FXSR" },
{ "CPU_CLFLUSH_FLAGS",
- "CpuClflush" },
+ "Clflush" },
{ "CPU_NOP_FLAGS",
- "CpuNop" },
+ "Nop" },
{ "CPU_SYSCALL_FLAGS",
- "CpuSYSCALL" },
+ "SYSCALL" },
{ "CPU_MMX_FLAGS",
- "CpuMMX" },
+ "MMX" },
{ "CPU_SSE_FLAGS",
- "CpuSSE" },
+ "SSE" },
{ "CPU_SSE2_FLAGS",
- "CPU_SSE_FLAGS|CpuSSE2" },
+ "CPU_SSE_FLAGS|SSE2" },
{ "CPU_SSE3_FLAGS",
- "CPU_SSE2_FLAGS|CpuSSE3" },
+ "CPU_SSE2_FLAGS|SSE3" },
{ "CPU_SSSE3_FLAGS",
- "CPU_SSE3_FLAGS|CpuSSSE3" },
+ "CPU_SSE3_FLAGS|SSSE3" },
{ "CPU_SSE4_1_FLAGS",
- "CPU_SSSE3_FLAGS|CpuSSE4_1" },
+ "CPU_SSSE3_FLAGS|SSE4_1" },
{ "CPU_SSE4_2_FLAGS",
- "CPU_SSE4_1_FLAGS|CpuSSE4_2|CpuPOPCNT" },
+ "CPU_SSE4_1_FLAGS|SSE4_2|POPCNT" },
{ "CPU_VMX_FLAGS",
- "CpuVMX" },
+ "VMX" },
{ "CPU_SMX_FLAGS",
- "CpuSMX" },
+ "SMX" },
{ "CPU_XSAVE_FLAGS",
- "CpuXsave" },
+ "Xsave" },
{ "CPU_XSAVEOPT_FLAGS",
- "CPU_XSAVE_FLAGS|CpuXsaveopt" },
+ "CPU_XSAVE_FLAGS|Xsaveopt" },
{ "CPU_AES_FLAGS",
- "CPU_SSE2_FLAGS|CpuAES" },
+ "CPU_SSE2_FLAGS|AES" },
{ "CPU_PCLMUL_FLAGS",
- "CPU_SSE2_FLAGS|CpuPCLMUL" },
+ "CPU_SSE2_FLAGS|PCLMUL" },
{ "CPU_FMA_FLAGS",
- "CPU_AVX_FLAGS|CpuFMA" },
+ "CPU_AVX_FLAGS|FMA" },
{ "CPU_FMA4_FLAGS",
- "CPU_AVX_FLAGS|CpuFMA4" },
+ "CPU_AVX_FLAGS|FMA4" },
{ "CPU_XOP_FLAGS",
- "CPU_SSE4A_FLAGS|CPU_FMA4_FLAGS|CpuXOP" },
+ "CPU_SSE4A_FLAGS|CPU_FMA4_FLAGS|XOP" },
{ "CPU_LWP_FLAGS",
- "CPU_XSAVE_FLAGS|CpuLWP" },
+ "CPU_XSAVE_FLAGS|LWP" },
{ "CPU_BMI_FLAGS",
- "CpuBMI" },
+ "BMI" },
{ "CPU_TBM_FLAGS",
- "CpuTBM" },
+ "TBM" },
{ "CPU_MOVBE_FLAGS",
- "CpuMovbe" },
+ "Movbe" },
{ "CPU_CX16_FLAGS",
- "CpuCX16" },
+ "CX16" },
{ "CPU_RDTSCP_FLAGS",
- "CpuRdtscp" },
+ "Rdtscp" },
{ "CPU_EPT_FLAGS",
- "CpuEPT" },
+ "EPT" },
{ "CPU_FSGSBASE_FLAGS",
- "CpuFSGSBase" },
+ "FSGSBase" },
{ "CPU_RDRND_FLAGS",
- "CpuRdRnd" },
+ "RdRnd" },
{ "CPU_F16C_FLAGS",
- "CPU_AVX_FLAGS|CpuF16C" },
+ "CPU_AVX_FLAGS|F16C" },
{ "CPU_BMI2_FLAGS",
- "CpuBMI2" },
+ "BMI2" },
{ "CPU_LZCNT_FLAGS",
- "CpuLZCNT" },
+ "LZCNT" },
{ "CPU_POPCNT_FLAGS",
- "CpuPOPCNT" },
+ "POPCNT" },
{ "CPU_HLE_FLAGS",
- "CpuHLE" },
+ "HLE" },
{ "CPU_RTM_FLAGS",
- "CpuRTM" },
+ "RTM" },
{ "CPU_INVPCID_FLAGS",
- "CpuINVPCID" },
+ "INVPCID" },
{ "CPU_VMFUNC_FLAGS",
- "CpuVMFUNC" },
+ "VMFUNC" },
{ "CPU_3DNOW_FLAGS",
- "CPU_MMX_FLAGS|Cpu3dnow" },
+ "CPU_MMX_FLAGS|3dnow" },
{ "CPU_3DNOWA_FLAGS",
- "CPU_3DNOW_FLAGS|Cpu3dnowA" },
+ "CPU_3DNOW_FLAGS|3dnowA" },
{ "CPU_PADLOCK_FLAGS",
- "CpuPadLock" },
+ "PadLock" },
{ "CPU_SVME_FLAGS",
- "CpuSVME" },
+ "SVME" },
{ "CPU_SSE4A_FLAGS",
- "CPU_SSE3_FLAGS|CpuSSE4a" },
+ "CPU_SSE3_FLAGS|SSE4a" },
{ "CPU_ABM_FLAGS",
- "CpuLZCNT|CpuPOPCNT" },
+ "LZCNT|POPCNT" },
{ "CPU_AVX_FLAGS",
- "CPU_SSE4_2_FLAGS|CPU_XSAVE_FLAGS|CpuAVX" },
+ "CPU_SSE4_2_FLAGS|CPU_XSAVE_FLAGS|AVX" },
{ "CPU_AVX2_FLAGS",
- "CPU_AVX_FLAGS|CpuAVX2" },
+ "CPU_AVX_FLAGS|AVX2" },
{ "CPU_AVX_VNNI_FLAGS",
- "CPU_AVX2_FLAGS|CpuAVX_VNNI" },
+ "CPU_AVX2_FLAGS|AVX_VNNI" },
{ "CPU_AVX512F_FLAGS",
- "CPU_AVX2_FLAGS|CpuAVX512F" },
+ "CPU_AVX2_FLAGS|AVX512F" },
{ "CPU_AVX512CD_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512CD" },
+ "CPU_AVX512F_FLAGS|AVX512CD" },
{ "CPU_AVX512ER_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512ER" },
+ "CPU_AVX512F_FLAGS|AVX512ER" },
{ "CPU_AVX512PF_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512PF" },
+ "CPU_AVX512F_FLAGS|AVX512PF" },
{ "CPU_AVX512DQ_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512DQ" },
+ "CPU_AVX512F_FLAGS|AVX512DQ" },
{ "CPU_AVX512BW_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512BW" },
+ "CPU_AVX512F_FLAGS|AVX512BW" },
{ "CPU_AVX512VL_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512VL" },
+ "CPU_AVX512F_FLAGS|AVX512VL" },
{ "CPU_AVX512IFMA_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512IFMA" },
+ "CPU_AVX512F_FLAGS|AVX512IFMA" },
{ "CPU_AVX512VBMI_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512VBMI" },
+ "CPU_AVX512F_FLAGS|AVX512VBMI" },
{ "CPU_AVX512_4FMAPS_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512_4FMAPS" },
+ "CPU_AVX512F_FLAGS|AVX512_4FMAPS" },
{ "CPU_AVX512_4VNNIW_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512_4VNNIW" },
+ "CPU_AVX512F_FLAGS|AVX512_4VNNIW" },
{ "CPU_AVX512_VPOPCNTDQ_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512_VPOPCNTDQ" },
+ "CPU_AVX512F_FLAGS|AVX512_VPOPCNTDQ" },
{ "CPU_AVX512_VBMI2_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512_VBMI2" },
+ "CPU_AVX512F_FLAGS|AVX512_VBMI2" },
{ "CPU_AVX512_VNNI_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512_VNNI" },
+ "CPU_AVX512F_FLAGS|AVX512_VNNI" },
{ "CPU_AVX512_BITALG_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512_BITALG" },
+ "CPU_AVX512F_FLAGS|AVX512_BITALG" },
{ "CPU_AVX512_BF16_FLAGS",
- "CPU_AVX512F_FLAGS|CpuAVX512_BF16" },
+ "CPU_AVX512F_FLAGS|AVX512_BF16" },
{ "CPU_AVX512_FP16_FLAGS",
- "CPU_AVX512BW_FLAGS|CpuAVX512_FP16" },
+ "CPU_AVX512BW_FLAGS|AVX512_FP16" },
{ "CPU_PREFETCHI_FLAGS",
- "CpuPREFETCHI"},
+ "PREFETCHI"},
{ "CPU_AVX_IFMA_FLAGS",
- "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
+ "CPU_AVX2_FLAGS|AVX_IFMA" },
{ "CPU_AVX_VNNI_INT8_FLAGS",
- "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
+ "CPU_AVX2_FLAGS|AVX_VNNI_INT8" },
{ "CPU_CMPCCXADD_FLAGS",
- "CpuCMPCCXADD" },
+ "CMPCCXADD" },
{ "CPU_WRMSRNS_FLAGS",
- "CpuWRMSRNS" },
+ "WRMSRNS" },
{ "CPU_MSRLIST_FLAGS",
- "CpuMSRLIST" },
+ "MSRLIST" },
{ "CPU_AVX_NE_CONVERT_FLAGS",
- "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
+ "CPU_AVX2_FLAGS|AVX_NE_CONVERT" },
{ "CPU_RAO_INT_FLAGS",
- "CpuRAO_INT" },
+ "RAO_INT" },
{ "CPU_IAMCU_FLAGS",
- "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
+ "186|286|386|486|586|IAMCU" },
{ "CPU_ADX_FLAGS",
- "CpuADX" },
+ "ADX" },
{ "CPU_RDSEED_FLAGS",
- "CpuRdSeed" },
+ "RdSeed" },
{ "CPU_PRFCHW_FLAGS",
- "CpuPRFCHW" },
+ "PRFCHW" },
{ "CPU_SMAP_FLAGS",
- "CpuSMAP" },
+ "SMAP" },
{ "CPU_MPX_FLAGS",
- "CPU_XSAVE_FLAGS|CpuMPX" },
+ "CPU_XSAVE_FLAGS|MPX" },
{ "CPU_SHA_FLAGS",
- "CPU_SSE2_FLAGS|CpuSHA" },
+ "CPU_SSE2_FLAGS|SHA" },
{ "CPU_CLFLUSHOPT_FLAGS",
- "CpuClflushOpt" },
+ "ClflushOpt" },
{ "CPU_XSAVES_FLAGS",
- "CPU_XSAVE_FLAGS|CpuXSAVES" },
+ "CPU_XSAVE_FLAGS|XSAVES" },
{ "CPU_XSAVEC_FLAGS",
- "CPU_XSAVE_FLAGS|CpuXSAVEC" },
+ "CPU_XSAVE_FLAGS|XSAVEC" },
{ "CPU_PREFETCHWT1_FLAGS",
- "CpuPREFETCHWT1" },
+ "PREFETCHWT1" },
{ "CPU_SE1_FLAGS",
- "CpuSE1" },
+ "SE1" },
{ "CPU_CLWB_FLAGS",
- "CpuCLWB" },
+ "CLWB" },
{ "CPU_CLZERO_FLAGS",
- "CpuCLZERO" },
+ "CLZERO" },
{ "CPU_MWAITX_FLAGS",
- "CpuMWAITX" },
+ "MWAITX" },
{ "CPU_OSPKE_FLAGS",
- "CPU_XSAVE_FLAGS|CpuOSPKE" },
+ "CPU_XSAVE_FLAGS|OSPKE" },
{ "CPU_RDPID_FLAGS",
- "CpuRDPID" },
+ "RDPID" },
{ "CPU_PTWRITE_FLAGS",
- "CpuPTWRITE" },
+ "PTWRITE" },
{ "CPU_IBT_FLAGS",
- "CpuIBT" },
+ "IBT" },
{ "CPU_SHSTK_FLAGS",
- "CpuSHSTK" },
+ "SHSTK" },
{ "CPU_GFNI_FLAGS",
- "CpuGFNI" },
+ "GFNI" },
{ "CPU_VAES_FLAGS",
- "CpuVAES" },
+ "VAES" },
{ "CPU_VPCLMULQDQ_FLAGS",
- "CpuVPCLMULQDQ" },
+ "VPCLMULQDQ" },
{ "CPU_WBNOINVD_FLAGS",
- "CpuWBNOINVD" },
+ "WBNOINVD" },
{ "CPU_PCONFIG_FLAGS",
- "CpuPCONFIG" },
+ "PCONFIG" },
{ "CPU_WAITPKG_FLAGS",
- "CpuWAITPKG" },
+ "WAITPKG" },
{ "CPU_UINTR_FLAGS",
- "CpuUINTR" },
+ "UINTR" },
{ "CPU_CLDEMOTE_FLAGS",
- "CpuCLDEMOTE" },
+ "CLDEMOTE" },
{ "CPU_AMX_INT8_FLAGS",
- "CPU_AMX_TILE_FLAGS|CpuAMX_INT8" },
+ "CPU_AMX_TILE_FLAGS|AMX_INT8" },
{ "CPU_AMX_BF16_FLAGS",
- "CPU_AMX_TILE_FLAGS|CpuAMX_BF16" },
+ "CPU_AMX_TILE_FLAGS|AMX_BF16" },
{ "CPU_AMX_FP16_FLAGS",
- "CPU_AMX_TILE_FLAGS|CpuAMX_FP16" },
+ "CPU_AMX_TILE_FLAGS|AMX_FP16" },
{ "CPU_AMX_TILE_FLAGS",
- "CpuAMX_TILE" },
+ "AMX_TILE" },
{ "CPU_MOVDIRI_FLAGS",
- "CpuMOVDIRI" },
+ "MOVDIRI" },
{ "CPU_MOVDIR64B_FLAGS",
- "CpuMOVDIR64B" },
+ "MOVDIR64B" },
{ "CPU_ENQCMD_FLAGS",
- "CpuENQCMD" },
+ "ENQCMD" },
{ "CPU_SERIALIZE_FLAGS",
- "CpuSERIALIZE" },
+ "SERIALIZE" },
{ "CPU_AVX512_VP2INTERSECT_FLAGS",
- "CpuAVX512_VP2INTERSECT" },
+ "AVX512_VP2INTERSECT" },
{ "CPU_TDX_FLAGS",
- "CpuTDX" },
+ "TDX" },
{ "CPU_RDPRU_FLAGS",
- "CpuRDPRU" },
+ "RDPRU" },
{ "CPU_MCOMMIT_FLAGS",
- "CpuMCOMMIT" },
+ "MCOMMIT" },
{ "CPU_SEV_ES_FLAGS",
- "CpuSEV_ES" },
+ "SEV_ES" },
{ "CPU_TSXLDTRK_FLAGS",
- "CpuTSXLDTRK"},
+ "TSXLDTRK"},
{ "CPU_KL_FLAGS",
- "CpuKL" },
+ "KL" },
{ "CPU_WIDEKL_FLAGS",
- "CpuWideKL" },
+ "WideKL" },
{ "CPU_HRESET_FLAGS",
- "CpuHRESET"},
+ "HRESET"},
{ "CPU_INVLPGB_FLAGS",
- "CpuINVLPGB" },
+ "INVLPGB" },
{ "CPU_TLBSYNC_FLAGS",
- "CpuTLBSYNC" },
+ "TLBSYNC" },
{ "CPU_SNP_FLAGS",
- "CpuSNP" },
+ "SNP" },
{ "CPU_RMPQUERY_FLAGS",
- "CpuRMPQUERY" },
+ "RMPQUERY" },
{ "CPU_ANY_X87_FLAGS",
- "CPU_ANY_287_FLAGS|Cpu8087" },
+ "CPU_ANY_287_FLAGS|8087" },
{ "CPU_ANY_287_FLAGS",
- "CPU_ANY_387_FLAGS|Cpu287" },
+ "CPU_ANY_387_FLAGS|287" },
{ "CPU_ANY_387_FLAGS",
- "CPU_ANY_687_FLAGS|Cpu387" },
+ "CPU_ANY_687_FLAGS|387" },
{ "CPU_ANY_687_FLAGS",
- "Cpu687|CpuFISTTP" },
+ "687|FISTTP" },
{ "CPU_ANY_CMOV_FLAGS",
- "CpuCMOV" },
+ "CMOV" },
{ "CPU_ANY_FXSR_FLAGS",
- "CpuFXSR" },
+ "FXSR" },
{ "CPU_ANY_MMX_FLAGS",
"CPU_3DNOWA_FLAGS" },
{ "CPU_ANY_SSE_FLAGS",
- "CPU_ANY_SSE2_FLAGS|CpuSSE" },
+ "CPU_ANY_SSE2_FLAGS|SSE" },
{ "CPU_ANY_SSE2_FLAGS",
- "CPU_ANY_SSE3_FLAGS|CpuSSE2" },
+ "CPU_ANY_SSE3_FLAGS|SSE2" },
{ "CPU_ANY_SSE3_FLAGS",
- "CPU_ANY_SSSE3_FLAGS|CpuSSE3|CpuSSE4a" },
+ "CPU_ANY_SSSE3_FLAGS|SSE3|SSE4a" },
{ "CPU_ANY_SSSE3_FLAGS",
- "CPU_ANY_SSE4_1_FLAGS|CpuSSSE3" },
+ "CPU_ANY_SSE4_1_FLAGS|SSSE3" },
{ "CPU_ANY_SSE4_1_FLAGS",
- "CPU_ANY_SSE4_2_FLAGS|CpuSSE4_1" },
+ "CPU_ANY_SSE4_2_FLAGS|SSE4_1" },
{ "CPU_ANY_SSE4_2_FLAGS",
- "CpuSSE4_2" },
+ "SSE4_2" },
{ "CPU_ANY_SSE4A_FLAGS",
- "CpuSSE4a" },
+ "SSE4a" },
{ "CPU_ANY_AVX_FLAGS",
- "CPU_ANY_AVX2_FLAGS|CpuF16C|CpuFMA|CpuFMA4|CpuXOP|CpuAVX" },
+ "CPU_ANY_AVX2_FLAGS|F16C|FMA|FMA4|XOP|AVX" },
{ "CPU_ANY_AVX2_FLAGS",
- "CPU_ANY_AVX512F_FLAGS|CpuAVX2|CpuAVX_VNNI|CpuAVX_IFMA|CpuAVX_VNNI_INT8|CpuAVX_NE_CONVERT" },
+ "CPU_ANY_AVX512F_FLAGS|AVX2|AVX_VNNI|AVX_IFMA|AVX_VNNI_INT8|AVX_NE_CONVERT" },
{ "CPU_ANY_AVX512F_FLAGS",
- "CpuAVX512F|CpuAVX512CD|CpuAVX512ER|CpuAVX512PF|CpuAVX512DQ|CPU_ANY_AVX512BW_FLAGS|CpuAVX512VL|CpuAVX512IFMA|CpuAVX512VBMI|CpuAVX512_4FMAPS|CpuAVX512_4VNNIW|CpuAVX512_VPOPCNTDQ|CpuAVX512_VBMI2|CpuAVX512_VNNI|CpuAVX512_BITALG|CpuAVX512_BF16|CpuAVX512_VP2INTERSECT" },
+ "AVX512F|AVX512CD|AVX512ER|AVX512PF|AVX512DQ|CPU_ANY_AVX512BW_FLAGS|AVX512VL|AVX512IFMA|AVX512VBMI|AVX512_4FMAPS|AVX512_4VNNIW|AVX512_VPOPCNTDQ|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_BF16|AVX512_VP2INTERSECT" },
{ "CPU_ANY_AVX512CD_FLAGS",
- "CpuAVX512CD" },
+ "AVX512CD" },
{ "CPU_ANY_AVX512ER_FLAGS",
- "CpuAVX512ER" },
+ "AVX512ER" },
{ "CPU_ANY_AVX512PF_FLAGS",
- "CpuAVX512PF" },
+ "AVX512PF" },
{ "CPU_ANY_AVX512DQ_FLAGS",
- "CpuAVX512DQ" },
+ "AVX512DQ" },
{ "CPU_ANY_AVX512BW_FLAGS",
- "CpuAVX512BW|CPU_ANY_AVX512_FP16_FLAGS" },
+ "AVX512BW|CPU_ANY_AVX512_FP16_FLAGS" },
{ "CPU_ANY_AVX512VL_FLAGS",
- "CpuAVX512VL" },
+ "AVX512VL" },
{ "CPU_ANY_AVX512IFMA_FLAGS",
- "CpuAVX512IFMA" },
+ "AVX512IFMA" },
{ "CPU_ANY_AVX512VBMI_FLAGS",
- "CpuAVX512VBMI" },
+ "AVX512VBMI" },
{ "CPU_ANY_AVX512_4FMAPS_FLAGS",
- "CpuAVX512_4FMAPS" },
+ "AVX512_4FMAPS" },
{ "CPU_ANY_AVX512_4VNNIW_FLAGS",
- "CpuAVX512_4VNNIW" },
+ "AVX512_4VNNIW" },
{ "CPU_ANY_AVX512_VPOPCNTDQ_FLAGS",
- "CpuAVX512_VPOPCNTDQ" },
+ "AVX512_VPOPCNTDQ" },
{ "CPU_ANY_IBT_FLAGS",
- "CpuIBT" },
+ "IBT" },
{ "CPU_ANY_SHSTK_FLAGS",
- "CpuSHSTK" },
+ "SHSTK" },
{ "CPU_ANY_AVX512_VBMI2_FLAGS",
- "CpuAVX512_VBMI2" },
+ "AVX512_VBMI2" },
{ "CPU_ANY_AVX512_VNNI_FLAGS",
- "CpuAVX512_VNNI" },
+ "AVX512_VNNI" },
{ "CPU_ANY_AVX512_BITALG_FLAGS",
- "CpuAVX512_BITALG" },
+ "AVX512_BITALG" },
{ "CPU_ANY_AVX512_BF16_FLAGS",
- "CpuAVX512_BF16" },
+ "AVX512_BF16" },
{ "CPU_ANY_AMX_INT8_FLAGS",
- "CpuAMX_INT8" },
+ "AMX_INT8" },
{ "CPU_ANY_AMX_BF16_FLAGS",
- "CpuAMX_BF16" },
+ "AMX_BF16" },
{ "CPU_ANY_AMX_TILE_FLAGS",
- "CpuAMX_TILE|CpuAMX_INT8|CpuAMX_BF16|CpuAMX_FP16" },
+ "AMX_TILE|AMX_INT8|AMX_BF16|AMX_FP16" },
{ "CPU_ANY_AVX_VNNI_FLAGS",
- "CpuAVX_VNNI" },
+ "AVX_VNNI" },
{ "CPU_ANY_MOVDIRI_FLAGS",
- "CpuMOVDIRI" },
+ "MOVDIRI" },
{ "CPU_ANY_UINTR_FLAGS",
- "CpuUINTR" },
+ "UINTR" },
{ "CPU_ANY_MOVDIR64B_FLAGS",
- "CpuMOVDIR64B" },
+ "MOVDIR64B" },
{ "CPU_ANY_ENQCMD_FLAGS",
- "CpuENQCMD" },
+ "ENQCMD" },
{ "CPU_ANY_SERIALIZE_FLAGS",
- "CpuSERIALIZE" },
+ "SERIALIZE" },
{ "CPU_ANY_AVX512_VP2INTERSECT_FLAGS",
- "CpuAVX512_VP2INTERSECT" },
+ "AVX512_VP2INTERSECT" },
{ "CPU_ANY_TDX_FLAGS",
- "CpuTDX" },
+ "TDX" },
{ "CPU_ANY_TSXLDTRK_FLAGS",
- "CpuTSXLDTRK" },
+ "TSXLDTRK" },
{ "CPU_ANY_KL_FLAGS",
- "CpuKL|CpuWideKL" },
+ "KL|WideKL" },
{ "CPU_ANY_WIDEKL_FLAGS",
- "CpuWideKL" },
+ "WideKL" },
{ "CPU_ANY_HRESET_FLAGS",
- "CpuHRESET" },
+ "HRESET" },
{ "CPU_ANY_AVX512_FP16_FLAGS",
- "CpuAVX512_FP16" },
+ "AVX512_FP16" },
{ "CPU_ANY_AVX_IFMA_FLAGS",
- "CpuAVX_IFMA" },
+ "AVX_IFMA" },
{ "CPU_ANY_AVX_VNNI_INT8_FLAGS",
- "CpuAVX_VNNI_INT8" },
+ "AVX_VNNI_INT8" },
{ "CPU_ANY_CMPCCXADD_FLAGS",
- "CpuCMPCCXADD" },
+ "CMPCCXADD" },
{ "CPU_ANY_WRMSRNS_FLAGS",
- "CpuWRMSRNS" },
+ "WRMSRNS" },
{ "CPU_ANY_MSRLIST_FLAGS",
- "CpuMSRLIST" },
+ "MSRLIST" },
{ "CPU_ANY_AVX_NE_CONVERT_FLAGS",
- "CpuAVX_NE_CONVERT" },
+ "AVX_NE_CONVERT" },
{ "CPU_ANY_RAO_INT_FLAGS",
- "CpuRAO_INT"},
+ "RAO_INT"},
};
typedef struct bitfield
@@ -484,149 +484,152 @@ typedef struct bitfield
const char *name;
} bitfield;
-#define BITFIELD(n) { n, 0, #n }
+#define BITFIELD(n) { Cpu##n, 0, #n }
static bitfield cpu_flags[] =
{
- BITFIELD (Cpu186),
- BITFIELD (Cpu286),
- BITFIELD (Cpu386),
- BITFIELD (Cpu486),
- BITFIELD (Cpu586),
- BITFIELD (Cpu686),
- BITFIELD (CpuCMOV),
- BITFIELD (CpuFXSR),
- BITFIELD (CpuClflush),
- BITFIELD (CpuNop),
- BITFIELD (CpuSYSCALL),
- BITFIELD (Cpu8087),
- BITFIELD (Cpu287),
- BITFIELD (Cpu387),
- BITFIELD (Cpu687),
- BITFIELD (CpuFISTTP),
- BITFIELD (CpuMMX),
- BITFIELD (CpuSSE),
- BITFIELD (CpuSSE2),
- BITFIELD (CpuSSE3),
- BITFIELD (CpuSSSE3),
- BITFIELD (CpuSSE4_1),
- BITFIELD (CpuSSE4_2),
- BITFIELD (CpuAVX),
- BITFIELD (CpuAVX2),
- BITFIELD (CpuAVX512F),
- BITFIELD (CpuAVX512CD),
- BITFIELD (CpuAVX512ER),
- BITFIELD (CpuAVX512PF),
- BITFIELD (CpuAVX512VL),
- BITFIELD (CpuAVX512DQ),
- BITFIELD (CpuAVX512BW),
- BITFIELD (CpuIAMCU),
- BITFIELD (CpuSSE4a),
- BITFIELD (Cpu3dnow),
- BITFIELD (Cpu3dnowA),
- BITFIELD (CpuPadLock),
- BITFIELD (CpuSVME),
- BITFIELD (CpuVMX),
- BITFIELD (CpuSMX),
- BITFIELD (CpuXsave),
- BITFIELD (CpuXsaveopt),
- BITFIELD (CpuAES),
- BITFIELD (CpuPCLMUL),
- BITFIELD (CpuFMA),
- BITFIELD (CpuFMA4),
- BITFIELD (CpuXOP),
- BITFIELD (CpuLWP),
- BITFIELD (CpuBMI),
- BITFIELD (CpuTBM),
- BITFIELD (CpuLM),
- BITFIELD (CpuMovbe),
- BITFIELD (CpuCX16),
- BITFIELD (CpuEPT),
- BITFIELD (CpuRdtscp),
- BITFIELD (CpuFSGSBase),
- BITFIELD (CpuRdRnd),
- BITFIELD (CpuF16C),
- BITFIELD (CpuBMI2),
- BITFIELD (CpuLZCNT),
- BITFIELD (CpuPOPCNT),
- BITFIELD (CpuHLE),
- BITFIELD (CpuRTM),
- BITFIELD (CpuINVPCID),
- BITFIELD (CpuVMFUNC),
- BITFIELD (CpuRDSEED),
- BITFIELD (CpuADX),
- BITFIELD (CpuPRFCHW),
- BITFIELD (CpuSMAP),
- BITFIELD (CpuSHA),
- BITFIELD (CpuClflushOpt),
- BITFIELD (CpuXSAVES),
- BITFIELD (CpuXSAVEC),
- BITFIELD (CpuPREFETCHWT1),
- BITFIELD (CpuSE1),
- BITFIELD (CpuCLWB),
- BITFIELD (CpuMPX),
- BITFIELD (CpuAVX512IFMA),
- BITFIELD (CpuAVX512VBMI),
- BITFIELD (CpuAVX512_4FMAPS),
- BITFIELD (CpuAVX512_4VNNIW),
- BITFIELD (CpuAVX512_VPOPCNTDQ),
- BITFIELD (CpuAVX512_VBMI2),
- BITFIELD (CpuAVX512_VNNI),
- BITFIELD (CpuAVX512_BITALG),
- BITFIELD (CpuAVX512_BF16),
- BITFIELD (CpuAVX512_VP2INTERSECT),
- BITFIELD (CpuTDX),
- BITFIELD (CpuAVX_VNNI),
- BITFIELD (CpuAVX512_FP16),
- BITFIELD (CpuPREFETCHI),
- BITFIELD (CpuAVX_IFMA),
- BITFIELD (CpuAVX_VNNI_INT8),
- BITFIELD (CpuCMPCCXADD),
- BITFIELD (CpuWRMSRNS),
- BITFIELD (CpuMSRLIST),
- BITFIELD (CpuAVX_NE_CONVERT),
- BITFIELD (CpuRAO_INT),
- BITFIELD (CpuMWAITX),
- BITFIELD (CpuCLZERO),
- BITFIELD (CpuOSPKE),
- BITFIELD (CpuRDPID),
- BITFIELD (CpuPTWRITE),
- BITFIELD (CpuIBT),
- BITFIELD (CpuSHSTK),
- BITFIELD (CpuGFNI),
- BITFIELD (CpuVAES),
- BITFIELD (CpuVPCLMULQDQ),
- BITFIELD (CpuWBNOINVD),
- BITFIELD (CpuPCONFIG),
- BITFIELD (CpuWAITPKG),
- BITFIELD (CpuUINTR),
- BITFIELD (CpuCLDEMOTE),
- BITFIELD (CpuAMX_INT8),
- BITFIELD (CpuAMX_BF16),
- BITFIELD (CpuAMX_FP16),
- BITFIELD (CpuAMX_TILE),
- BITFIELD (CpuMOVDIRI),
- BITFIELD (CpuMOVDIR64B),
- BITFIELD (CpuENQCMD),
- BITFIELD (CpuSERIALIZE),
- BITFIELD (CpuRDPRU),
- BITFIELD (CpuMCOMMIT),
- BITFIELD (CpuSEV_ES),
- BITFIELD (CpuTSXLDTRK),
- BITFIELD (CpuKL),
- BITFIELD (CpuWideKL),
- BITFIELD (CpuHRESET),
- BITFIELD (CpuINVLPGB),
- BITFIELD (CpuTLBSYNC),
- BITFIELD (CpuSNP),
- BITFIELD (CpuRMPQUERY),
- BITFIELD (Cpu64),
- BITFIELD (CpuNo64),
+ BITFIELD (186),
+ BITFIELD (286),
+ BITFIELD (386),
+ BITFIELD (486),
+ BITFIELD (586),
+ BITFIELD (686),
+ BITFIELD (CMOV),
+ BITFIELD (FXSR),
+ BITFIELD (Clflush),
+ BITFIELD (Nop),
+ BITFIELD (SYSCALL),
+ BITFIELD (8087),
+ BITFIELD (287),
+ BITFIELD (387),
+ BITFIELD (687),
+ BITFIELD (FISTTP),
+ BITFIELD (MMX),
+ BITFIELD (SSE),
+ BITFIELD (SSE2),
+ BITFIELD (SSE3),
+ BITFIELD (SSSE3),
+ BITFIELD (SSE4_1),
+ BITFIELD (SSE4_2),
+ BITFIELD (AVX),
+ BITFIELD (AVX2),
+ BITFIELD (AVX512F),
+ BITFIELD (AVX512CD),
+ BITFIELD (AVX512ER),
+ BITFIELD (AVX512PF),
+ BITFIELD (AVX512VL),
+ BITFIELD (AVX512DQ),
+ BITFIELD (AVX512BW),
+ BITFIELD (IAMCU),
+ BITFIELD (SSE4a),
+ BITFIELD (3dnow),
+ BITFIELD (3dnowA),
+ BITFIELD (PadLock),
+ BITFIELD (SVME),
+ BITFIELD (VMX),
+ BITFIELD (SMX),
+ BITFIELD (Xsave),
+ BITFIELD (Xsaveopt),
+ BITFIELD (AES),
+ BITFIELD (PCLMUL),
+ BITFIELD (FMA),
+ BITFIELD (FMA4),
+ BITFIELD (XOP),
+ BITFIELD (LWP),
+ BITFIELD (BMI),
+ BITFIELD (TBM),
+ BITFIELD (LM),
+ BITFIELD (Movbe),
+ BITFIELD (CX16),
+ BITFIELD (EPT),
+ BITFIELD (Rdtscp),
+ BITFIELD (FSGSBase),
+ BITFIELD (RdRnd),
+ BITFIELD (F16C),
+ BITFIELD (BMI2),
+ BITFIELD (LZCNT),
+ BITFIELD (POPCNT),
+ BITFIELD (HLE),
+ BITFIELD (RTM),
+ BITFIELD (INVPCID),
+ BITFIELD (VMFUNC),
+ BITFIELD (RDSEED),
+ BITFIELD (ADX),
+ BITFIELD (PRFCHW),
+ BITFIELD (SMAP),
+ BITFIELD (SHA),
+ BITFIELD (ClflushOpt),
+ BITFIELD (XSAVES),
+ BITFIELD (XSAVEC),
+ BITFIELD (PREFETCHWT1),
+ BITFIELD (SE1),
+ BITFIELD (CLWB),
+ BITFIELD (MPX),
+ BITFIELD (AVX512IFMA),
+ BITFIELD (AVX512VBMI),
+ BITFIELD (AVX512_4FMAPS),
+ BITFIELD (AVX512_4VNNIW),
+ BITFIELD (AVX512_VPOPCNTDQ),
+ BITFIELD (AVX512_VBMI2),
+ BITFIELD (AVX512_VNNI),
+ BITFIELD (AVX512_BITALG),
+ BITFIELD (AVX512_BF16),
+ BITFIELD (AVX512_VP2INTERSECT),
+ BITFIELD (TDX),
+ BITFIELD (AVX_VNNI),
+ BITFIELD (AVX512_FP16),
+ BITFIELD (PREFETCHI),
+ BITFIELD (AVX_IFMA),
+ BITFIELD (AVX_VNNI_INT8),
+ BITFIELD (CMPCCXADD),
+ BITFIELD (WRMSRNS),
+ BITFIELD (MSRLIST),
+ BITFIELD (AVX_NE_CONVERT),
+ BITFIELD (RAO_INT),
+ BITFIELD (MWAITX),
+ BITFIELD (CLZERO),
+ BITFIELD (OSPKE),
+ BITFIELD (RDPID),
+ BITFIELD (PTWRITE),
+ BITFIELD (IBT),
+ BITFIELD (SHSTK),
+ BITFIELD (GFNI),
+ BITFIELD (VAES),
+ BITFIELD (VPCLMULQDQ),
+ BITFIELD (WBNOINVD),
+ BITFIELD (PCONFIG),
+ BITFIELD (WAITPKG),
+ BITFIELD (UINTR),
+ BITFIELD (CLDEMOTE),
+ BITFIELD (AMX_INT8),
+ BITFIELD (AMX_BF16),
+ BITFIELD (AMX_FP16),
+ BITFIELD (AMX_TILE),
+ BITFIELD (MOVDIRI),
+ BITFIELD (MOVDIR64B),
+ BITFIELD (ENQCMD),
+ BITFIELD (SERIALIZE),
+ BITFIELD (RDPRU),
+ BITFIELD (MCOMMIT),
+ BITFIELD (SEV_ES),
+ BITFIELD (TSXLDTRK),
+ BITFIELD (KL),
+ BITFIELD (WideKL),
+ BITFIELD (HRESET),
+ BITFIELD (INVLPGB),
+ BITFIELD (TLBSYNC),
+ BITFIELD (SNP),
+ BITFIELD (RMPQUERY),
+ BITFIELD (64),
+ BITFIELD (No64),
#ifdef CpuUnused
- BITFIELD (CpuUnused),
+ BITFIELD (Unused),
#endif
};
+#undef BITFIELD
+#define BITFIELD(n) { n, 0, #n }
+
static bitfield opcode_modifiers[] =
{
BITFIELD (D),
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -136,21 +136,21 @@
// operands may allow to switch from 3-byte to 2-byte VEX encoding.
#define C StaticRounding
-#define CpuFP Cpu387|Cpu287|Cpu8087
+#define FP 387|287|8087
### MARKER ###
// Move instructions.
-mov, 0xa0, CpuNo64, D|W|CheckRegSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
-mov, 0xa0, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
-movabs, 0xa0, Cpu64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
+mov, 0xa0, No64, D|W|CheckRegSize|No_sSuf|No_qSuf, { Disp16|Disp32|Unspecified|Byte|Word|Dword, Acc|Byte|Word|Dword }
+mov, 0xa0, 64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
+movabs, 0xa0, 64, D|W|CheckRegSize|No_sSuf, { Disp64|Unspecified|Byte|Word|Dword|Qword, Acc|Byte|Word|Dword|Qword }
mov, 0x88, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixRelease, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
// In the 64bit mode the short form mov immediate is redefined to have
// 64bit value.
mov, 0xb0, 0, W|No_sSuf|No_qSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32 }
mov, 0xc6/0, 0, W|Modrm|No_sSuf|HLEPrefixRelease|Optimize, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-mov, 0xb8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 }
-movabs, 0xb8, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 }
+mov, 0xb8, 64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|Optimize, { Imm64, Reg64 }
+movabs, 0xb8, 64, No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Imm64, Reg64 }
// The segment register moves accept WordReg so that a segment register
// can be copied to a 32 bit register, and vice versa, without using a
// size prefix. When moving to a 32 bit register, the upper 16 bits
@@ -161,57 +161,57 @@ mov, 0x8c, 0, D|Modrm|IgnoreSize|No_bSuf
mov, 0x8e, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
// Move to/from control debug registers. In the 16 or 32bit modes
// they are 32bit. In the 64bit mode they are 64bit.
-mov, 0xf20, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 }
-mov, 0xf20, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 }
-mov, 0xf21, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 }
-mov, 0xf21, Cpu64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 }
-mov, 0xf24, Cpu386|CpuNo64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 }
+mov, 0xf20, 386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Control, Reg32 }
+mov, 0xf20, 64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Control, Reg64 }
+mov, 0xf21, 386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Debug, Reg32 }
+mov, 0xf21, 64, D|RegMem|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Debug, Reg64 }
+mov, 0xf24, 386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Test, Reg32 }
// Move after swapping the bytes
-movbe, 0x0f38f0, CpuMovbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movbe, 0x0f38f0, Movbe, D|Modrm|CheckRegSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Move with sign extend.
-movsb, 0xfbe, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movsw, 0xfbf, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 }
-movsl, 0x63, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 }
-movsx, 0xfbe, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movsx, 0x63, Cpu64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
-movsxd, 0x63, Cpu64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
-movsxd, 0x63, Cpu64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
-movsxd, 0x63, Cpu64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 }
+movsb, 0xfbe, 386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movsw, 0xfbf, 386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Unspecified|BaseIndex, Reg32|Reg64 }
+movsl, 0x63, 64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg32|Unspecified|BaseIndex, Reg64 }
+movsx, 0xfbe, 386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movsx, 0x63, 64, Modrm|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
+movsxd, 0x63, 64, Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg32|Reg64 }
+movsxd, 0x63, 64, Amd64|Modrm|NoSuf, { Reg32|Unspecified|BaseIndex, Reg16 }
+movsxd, 0x63, 64, Intel64|Modrm|NoSuf, { Reg16|Unspecified|BaseIndex, Reg16 }
// Move with zero extend.
-movzb, 0xfb6, Cpu386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-movzw, 0xfb7, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
+movzb, 0xfb6, 386, Modrm|No_bSuf|No_sSuf, { Reg8|Byte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movzw, 0xfb7, 386, Modrm|No_bSuf|No_wSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg32|Reg64 }
// The 64-bit variant is not particularly useful since the zero extend
// 32->64 is implicit, but we can encode them.
-movzx, 0xfb6, Cpu386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+movzx, 0xfb6, 386, W|Modrm|No_lSuf|No_sSuf|No_qSuf, { Reg8|Reg16|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Push instructions.
-push, 0x50, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
-push, 0xff/6, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
-push, 0x6a, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S }
-push, 0x68, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 }
-push, 0x6, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
+push, 0x50, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
+push, 0xff/6, No64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
+push, 0x6a, 186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm8S }
+push, 0x68, 186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16|Imm32 }
+push, 0x6, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
// In 64bit mode, the operand size is implicitly 64bit.
-push, 0x50, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
-push, 0xff/6, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
-push, 0x6a, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S }
-push, 0x68, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S }
-push, 0xfa0, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
+push, 0x50, 64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
+push, 0xff/6, 64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
+push, 0x6a, 64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm8S }
+push, 0x68, 64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16|Imm32S }
+push, 0xfa0, 64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
-pusha, 0x60, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+pusha, 0x60, 186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
// Pop instructions.
-pop, 0x58, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
-pop, 0x8f/0, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
-pop, 0x7, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
+pop, 0x58, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
+pop, 0x8f/0, No64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
+pop, 0x7, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { SReg }
// In 64bit mode, the operand size is implicitly 64bit.
-pop, 0x58, Cpu64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
-pop, 0x8f/0, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
-pop, 0xfa1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
+pop, 0x58, 64, No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64 }
+pop, 0x8f/0, 64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
+pop, 0xfa1, 64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { SReg }
-popa, 0x61, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+popa, 0x61, 186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
// Exchange instructions.
// xchg commutes: we allow both operand orders.
@@ -234,27 +234,27 @@ out, 0xee, 0, W|No_sSuf|No_qSuf, { InOut
lea, 0x8d, 0, Modrm|Anysize|No_bSuf|No_sSuf|Optimize, { BaseIndex, Reg16|Reg32|Reg64 }
// Load segment registers from memory.
-lds, 0xc5, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-les, 0xc4, CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lfs, 0xfb4, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lfs, 0xfb4, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lgs, 0xfb5, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lgs, 0xfb5, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lss, 0xfb2, Cpu386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
-lss, 0xfb2, Cpu64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lds, 0xc5, No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+les, 0xc4, No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { DWord|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lfs, 0xfb4, 386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lfs, 0xfb4, 64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lgs, 0xfb5, 386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lgs, 0xfb5, 64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lss, 0xfb2, 386, Amd64|Modrm|No_bSuf|No_sSuf|No_qSuf, { Dword|Fword|Unspecified|BaseIndex, Reg16|Reg32 }
+lss, 0xfb2, 64, Intel64|Modrm|No_bSuf|No_sSuf, { Dword|Fword|Tbyte|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// Flags register instructions.
clc, 0xf8, 0, NoSuf, {}
cld, 0xfc, 0, NoSuf, {}
cli, 0xfa, 0, NoSuf, {}
-clts, 0xf06, Cpu286, NoSuf, {}
+clts, 0xf06, 286, NoSuf, {}
cmc, 0xf5, 0, NoSuf, {}
lahf, 0x9f, 0, NoSuf, {}
sahf, 0x9e, 0, NoSuf, {}
-pushf, 0x9c, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-pushf, 0x9c, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
-popf, 0x9d, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-popf, 0x9d, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
+pushf, 0x9c, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+pushf, 0x9c, 64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
+popf, 0x9d, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+popf, 0x9d, 64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
stc, 0xf9, 0, NoSuf, {}
std, 0xfd, 0, NoSuf, {}
sti, 0xfb, 0, NoSuf, {}
@@ -265,7 +265,7 @@ add, 0x83/0, 0, Modrm|No_bSuf|No_sSuf|HL
add, 0x4, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
add, 0x80/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-inc, 0x40, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
+inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sub, 0x28, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
@@ -273,7 +273,7 @@ sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HL
sub, 0x2c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword }
sub, 0x80/5, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-dec, 0x48, CpuNo64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
+dec, 0x48, No64, No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32 }
dec, 0xfe/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sbb, 0x18, 0, D|W|CheckRegSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
@@ -316,30 +316,30 @@ adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefi
neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-aaa, 0x37, CpuNo64, NoSuf, {}
-aas, 0x3f, CpuNo64, NoSuf, {}
-daa, 0x27, CpuNo64, NoSuf, {}
-das, 0x2f, CpuNo64, NoSuf, {}
-aad, 0xd50a, CpuNo64, NoSuf, {}
-aad, 0xd5, CpuNo64, NoSuf, { Imm8 }
-aam, 0xd40a, CpuNo64, NoSuf, {}
-aam, 0xd4, CpuNo64, NoSuf, { Imm8 }
+aaa, 0x37, No64, NoSuf, {}
+aas, 0x3f, No64, NoSuf, {}
+daa, 0x27, No64, NoSuf, {}
+das, 0x2f, No64, NoSuf, {}
+aad, 0xd50a, No64, NoSuf, {}
+aad, 0xd5, No64, NoSuf, { Imm8 }
+aam, 0xd40a, No64, NoSuf, {}
+aam, 0xd4, No64, NoSuf, { Imm8 }
// Conversion insns.
// Intel naming
cbw, 0x98, 0, Size16|NoSuf, {}
-cwde, 0x98, Cpu386, Size32|NoSuf, {}
-cdqe, 0x98, Cpu64, Size64|NoSuf, {}
+cwde, 0x98, 386, Size32|NoSuf, {}
+cdqe, 0x98, 64, Size64|NoSuf, {}
cwd, 0x99, 0, Size16|NoSuf, {}
-cdq, 0x99, Cpu386, Size32|NoSuf, {}
-cqo, 0x99, Cpu64, Size64|NoSuf, {}
+cdq, 0x99, 386, Size32|NoSuf, {}
+cqo, 0x99, 64, Size64|NoSuf, {}
// AT&T naming
cbtw, 0x98, 0, Size16|NoSuf, {}
-cwtl, 0x98, Cpu386, Size32|NoSuf, {}
-cltq, 0x98, Cpu64, Size64|NoSuf, {}
+cwtl, 0x98, 386, Size32|NoSuf, {}
+cltq, 0x98, 64, Size64|NoSuf, {}
cwtd, 0x99, 0, Size16|NoSuf, {}
-cltd, 0x99, Cpu386, Size32|NoSuf, {}
-cqto, 0x99, Cpu64, Size64|NoSuf, {}
+cltd, 0x99, 386, Size32|NoSuf, {}
+cqto, 0x99, 64, Size64|NoSuf, {}
// Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are
// expanding 64-bit multiplies, and *cannot* be selected to accomplish
@@ -347,14 +347,14 @@ cqto, 0x99, Cpu64, Size64|NoSuf, {}
// These multiplies can only be selected with single operand forms.
mul, 0xf6/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
imul, 0xf6/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-imul, 0xfaf, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 }
-imul, 0x6b, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-imul, 0x69, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0xfaf, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|Word|Dword|Qword|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0x6b, 186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+imul, 0x69, 186, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
// imul with 2 operands mimics imul with 3 by putting the register in
// both i.rm.reg & i.rm.regmem fields. RegKludge enables this
// transformation.
-imul, 0x6b, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 }
-imul, 0x69, Cpu186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
+imul, 0x6b, 186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 }
+imul, 0x69, 186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
div, 0xf6/6, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
div, 0xf6/6, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
@@ -362,97 +362,97 @@ idiv, 0xf6/7, 0, W|Modrm|No_sSuf, { Reg8
idiv, 0xf6/7, 0, W|CheckRegSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rol, 0xc0/0, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rol, 0xc0/0, 186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rol, 0xd2/0, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rol, 0xd0/0, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ror, 0xc0/1, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+ror, 0xc0/1, 186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ror, 0xd2/1, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
ror, 0xd0/1, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rcl, 0xc0/2, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rcl, 0xc0/2, 186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-rcr, 0xc0/3, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+rcr, 0xc0/3, 186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rcr, 0xd2/3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sal, 0xc0/4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sal, 0xc0/4, 186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sal, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shl, 0xc0/4, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shl, 0xc0/4, 186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shl, 0xd2/4, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shl, 0xd0/4, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shr, 0xc0/5, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+shr, 0xc0/5, 186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shr, 0xd2/5, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
shr, 0xd0/5, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-sar, 0xc0/7, Cpu186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
+sar, 0xc0/7, 186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sar, 0xd2/7, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
sar, 0xd0/7, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-shld, 0xfa4, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shld, 0xfa5, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shld, 0xfa5, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-
-shrd, 0xfac, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shrd, 0xfad, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-shrd, 0xfad, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shld, 0xfa4, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shld, 0xfa5, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shld, 0xfa5, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+
+shrd, 0xfac, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shrd, 0xfad, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { ShiftCount, Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+shrd, 0xfad, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
// Control transfer instructions.
-call, 0xe8, CpuNo64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 }
-call, 0xe8, Cpu64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 }
-call, 0xe8, Cpu64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 }
-call, 0xff/2, CpuNo64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
-call, 0xff/2, Cpu64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
-call, 0xff/2, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
+call, 0xe8, No64, JumpDword|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk, { Disp16|Disp32 }
+call, 0xe8, 64, Amd64|JumpDword|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp16|Disp32 }
+call, 0xe8, 64, Intel64|JumpDword|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk, { Disp32 }
+call, 0xff/2, No64, Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
+call, 0xff/2, 64, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
+call, 0xff/2, 64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
// Intel Syntax remaining call instances.
-call, 0x9a, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+call, 0x9a, No64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
call, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|NoSuf, { Dword|Fword|BaseIndex }
-call, 0xff/3, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
-lcall, 0x9a, CpuNo64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+call, 0xff/3, 64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
+lcall, 0x9a, No64, JumpInterSegment|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
lcall, 0xff/3, 0, Amd64|Modrm|JumpAbsolute|DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex }
-lcall, 0xff/3, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
+lcall, 0xff/3, 64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
jmp, 0xeb, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
-jmp, 0xeb, Cpu64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 }
-jmp, 0xff/4, CpuNo64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
-jmp, 0xff/4, Cpu64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
-jmp, 0xff/4, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
+jmp, 0xeb, 64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 }
+jmp, 0xff/4, No64, Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg32|Unspecified|BaseIndex }
+jmp, 0xff/4, 64, Amd64|Modrm|JumpAbsolute|No_bSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg16|Reg64|Unspecified|BaseIndex }
+jmp, 0xff/4, 64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|BNDPrefixOk|NoTrackPrefixOk, { Reg64|Unspecified|BaseIndex }
// Intel Syntax remaining jmp instances.
-jmp, 0xea, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+jmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
jmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|BaseIndex }
-jmp, 0xff/5, Cpu64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
-ljmp, 0xea, CpuNo64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
+jmp, 0xff/5, 64, Intel64|Modrm|JumpAbsolute|NoSuf, { Dword|Fword|Tbyte|BaseIndex }
+ljmp, 0xea, No64, JumpInterSegment|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm16|Imm32 }
ljmp, 0xff/5, 0, Amd64|Modrm|JumpAbsolute|No_bSuf|No_sSuf|No_qSuf, { Unspecified|BaseIndex }
-ljmp, 0xff/5, Cpu64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
+ljmp, 0xff/5, 64, Intel64|Modrm|JumpAbsolute|No_bSuf|No_sSuf, { Unspecified|BaseIndex }
-ret, 0xc3, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
-ret, 0xc3, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, Cpu64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
-ret, 0xc3, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
-ret, 0xc2, Cpu64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0xc3, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, {}
+ret, 0xc2, No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0xc3, 64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
+ret, 0xc2, 64, Amd64|DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
+ret, 0xc3, 64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, {}
+ret, 0xc2, 64, Intel64|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64|RepPrefixOk|BNDPrefixOk, { Imm16 }
lret, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {}
lret, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 }
// Intel Syntax.
retf, 0xcb, 0, DefaultSize|No_bSuf|No_sSuf, {}
retf, 0xca, 0, DefaultSize|No_bSuf|No_sSuf, { Imm16 }
-enter, 0xc8, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 }
-enter, 0xc8, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 }
-leave, 0xc9, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
-leave, 0xc9, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
+enter, 0xc8, 186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, { Imm16, Imm8 }
+enter, 0xc8, 64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, { Imm16, Imm8 }
+leave, 0xc9, 186|No64, DefaultSize|No_bSuf|No_sSuf|No_qSuf, {}
+leave, 0xc9, 64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|NoRex64, {}
<cc:opc, o:0, no:1, b:2, c:2, nae:2, nb:3, nc:3, ae:3, e:4, z:4, ne:5, nz:5, be:6, na:6, nbe:7, a:7, +
s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
@@ -461,37 +461,37 @@ leave, 0xc9, Cpu64, DefaultSize|No_bSuf|
j<cc>, 0x7<cc:opc>, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
// jcxz vs. jecxz is chosen on the basis of the address size prefix.
-jcxz, 0xe3, CpuNo64, JumpByte|Size16|NoSuf, { Disp8 }
-jecxz, 0xe3, Cpu386, JumpByte|Size32|NoSuf, { Disp8 }
-jrcxz, 0xe3, Cpu64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 }
+jcxz, 0xe3, No64, JumpByte|Size16|NoSuf, { Disp8 }
+jecxz, 0xe3, 386, JumpByte|Size32|NoSuf, { Disp8 }
+jrcxz, 0xe3, 64, JumpByte|Size64|NoSuf|NoRex64, { Disp8 }
// The loop instructions also use the address size prefix to select
// %cx rather than %ecx for the loop count, so the `w' form of these
// instructions emit an address size prefix rather than a data size
// prefix.
-loop, 0xe2, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loop, 0xe2, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopz, 0xe1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopz, 0xe1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loope, 0xe1, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loope, 0xe1, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopnz, 0xe0, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopnz, 0xe0, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
-loopne, 0xe0, CpuNo64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
-loopne, 0xe0, Cpu64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loop, 0xe2, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loop, 0xe2, 64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loopz, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loopz, 0xe1, 64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loope, 0xe1, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loope, 0xe1, 64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loopnz, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loopnz, 0xe0, 64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
+loopne, 0xe0, No64, JumpByte|No_bSuf|No_sSuf|No_qSuf, { Disp8 }
+loopne, 0xe0, 64, JumpByte|No_bSuf|No_wSuf|No_sSuf|NoRex64, { Disp8 }
// Set byte on flag instructions.
-set<cc>, 0xf9<cc:opc>/0, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex }
+set<cc>, 0xf9<cc:opc>/0, 386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf, { Reg8|Byte|Unspecified|BaseIndex }
// String manipulation.
cmps, 0xa6, 0, W|No_sSuf|RepPrefixOk, {}
cmps, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
scmp, 0xa6, 0, W|No_sSuf|RepPrefixOk, {}
scmp, 0xa6, 0, W|No_sSuf|IsStringEsOp0|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Byte|Word|Dword|Qword|Unspecified|BaseIndex }
-ins, 0x6c, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
-ins, 0x6c, Cpu186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex }
-outs, 0x6e, Cpu186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
-outs, 0x6e, Cpu186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
+ins, 0x6c, 186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
+ins, 0x6c, 186, W|No_sSuf|No_qSuf|IsStringEsOp1|RepPrefixOk, { InOutPortReg, Byte|Word|Dword|Unspecified|BaseIndex }
+outs, 0x6e, 186, W|No_sSuf|No_qSuf|RepPrefixOk, {}
+outs, 0x6e, 186, W|No_sSuf|No_qSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Unspecified|BaseIndex, InOutPortReg }
lods, 0xac, 0, W|No_sSuf|RepPrefixOk, {}
lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex }
lods, 0xac, 0, W|No_sSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex, Acc|Byte|Word|Dword|Qword }
@@ -518,16 +518,16 @@ xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|N
xlat, 0xd7, 0, No_wSuf|No_lSuf|No_sSuf|No_qSuf|IsString, { Byte|Unspecified|BaseIndex }
// Bit manipulation.
-bsf, 0xfbc, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-bsr, 0xfbd, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-bt, 0xfa3, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-bt, 0xfba/4, Cpu386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-btc, 0xfbb, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-btc, 0xfba/7, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-btr, 0xfb3, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-btr, 0xfba/6, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-bts, 0xfab, Cpu386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
-bts, 0xfba/5, Cpu386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+bsf, 0xfbc, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+bsr, 0xfbd, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf|RepPrefixOk, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+bt, 0xfa3, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+bt, 0xfba/4, 386, Modrm|No_bSuf|No_sSuf, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+btc, 0xfbb, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+btc, 0xfba/7, 386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+btr, 0xfb3, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+btr, 0xfba/6, 386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+bts, 0xfab, 386, Modrm|CheckRegSize|No_bSuf|No_sSuf|HLEPrefixLock, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+bts, 0xfba/5, 386, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
// Interrupts & op. sys insns.
// See gas/config/tc-i386.c for conversion of 'int $3' into the special
@@ -535,291 +535,291 @@ bts, 0xfba/5, Cpu386, Modrm|No_bSuf|No_s
int, 0xcd, 0, NoSuf, { Imm8 }
int1, 0xf1, 0, NoSuf, {}
int3, 0xcc, 0, NoSuf, {}
-into, 0xce, CpuNo64, NoSuf, {}
+into, 0xce, No64, NoSuf, {}
iret, 0xcf, 0, DefaultSize|No_bSuf|No_sSuf, {}
// i386sl, i486sl, later 486, and Pentium.
-rsm, 0xfaa, Cpu386, NoSuf, {}
+rsm, 0xfaa, 386, NoSuf, {}
-bound, 0x62, Cpu186|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex }
+bound, 0x62, 186|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Reg16|Reg32, Dword|Qword|Unspecified|BaseIndex }
hlt, 0xf4, 0, NoSuf, {}
-nop, 0xf1f/0, CpuNop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
+nop, 0xf1f/0, Nop, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex }
// nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
// 32bit mode and "xchg %rax,%rax" in 64bit mode.
nop, 0x90, 0, NoSuf|RepPrefixOk, {}
// Protection control.
-arpl, 0x63, Cpu286|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
-lar, 0xf02, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lar, 0xf02, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-lgdt, 0xf01/2, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
-lgdt, 0xf01/2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-lidt, 0xf01/3, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
-lidt, 0xf01/3, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-lldt, 0xf00/2, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-lmsw, 0xf01/6, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-lsl, 0xf03, Cpu286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
-lsl, 0xf03, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
-ltr, 0xf00/3, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-
-sgdt, 0xf01/0, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
-sgdt, 0xf01/0, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-sidt, 0xf01/1, Cpu286|CpuNo64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
-sidt, 0xf01/1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
-sldt, 0xf00/0, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
-sldt, 0xf00/0, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-smsw, 0xf01/4, Cpu286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 }
-smsw, 0xf01/4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-str, 0xf00/1, Cpu286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
-str, 0xf00/1, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+arpl, 0x63, 286|No64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16, Reg16|Word|Unspecified|BaseIndex }
+lar, 0xf02, 286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lar, 0xf02, 286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+lgdt, 0xf01/2, 286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+lgdt, 0xf01/2, 64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
+lidt, 0xf01/3, 286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+lidt, 0xf01/3, 64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
+lldt, 0xf00/2, 286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+lmsw, 0xf01/6, 286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+lsl, 0xf03, 286, Modrm|CheckRegSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Reg16|Reg32|Reg64 }
+lsl, 0xf03, 286, Modrm|No_bSuf|No_sSuf, { Reg16|Word|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
+ltr, 0xf00/3, 286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+
+sgdt, 0xf01/0, 286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+sgdt, 0xf01/0, 64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
+sidt, 0xf01/1, 286|No64, Modrm|No_bSuf|No_sSuf|No_qSuf, { Fword|Unspecified|BaseIndex }
+sidt, 0xf01/1, 64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Tbyte|Unspecified|BaseIndex }
+sldt, 0xf00/0, 286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+sldt, 0xf00/0, 286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+smsw, 0xf01/4, 286, Modrm|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64 }
+smsw, 0xf01/4, 286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+str, 0xf00/1, 286, Modrm|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+str, 0xf00/1, 286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-verr, 0xf00/4, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
-verw, 0xf00/5, Cpu286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+verr, 0xf00/4, 286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
+verw, 0xf00/5, 286, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Reg16|Word|Unspecified|BaseIndex }
// Floating point instructions.
// load
-fld, 0xd9c0, CpuFP, NoSuf, { FloatReg }
-fld, 0xd9/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fld, 0xd9c0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+fld, 0xd9c0, FP, NoSuf, { FloatReg }
+fld, 0xd9/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fld, 0xd9c0, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
// Intel Syntax
-fld, 0xdb/5, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
-fild, 0xdf/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fild, 0xdf/5, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex }
-fildll, 0xdf/5, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex }
-fldt, 0xdb/5, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex }
-fbld, 0xdf/4, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
+fld, 0xdb/5, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
+fild, 0xdf/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fild, 0xdf/5, FP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex }
+fildll, 0xdf/5, FP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex }
+fldt, 0xdb/5, FP, Modrm|NoSuf, { Unspecified|BaseIndex }
+fbld, 0xdf/4, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
// store (no pop)
-fst, 0xddd0, CpuFP, NoSuf, { FloatReg }
-fst, 0xd9/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fst, 0xddd0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
-fist, 0xdf/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fst, 0xddd0, FP, NoSuf, { FloatReg }
+fst, 0xd9/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fst, 0xddd0, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+fist, 0xdf/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
// store (with pop)
-fstp, 0xddd8, CpuFP, NoSuf, { FloatReg }
-fstp, 0xd9/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fstp, 0xddd8, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+fstp, 0xddd8, FP, NoSuf, { FloatReg }
+fstp, 0xd9/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fstp, 0xddd8, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
// Intel Syntax
-fstp, 0xdb/7, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
-fistp, 0xdf/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fistp, 0xdf/7, CpuFP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex }
-fistpll, 0xdf/7, CpuFP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex }
-fstpt, 0xdb/7, CpuFP, Modrm|NoSuf, { Unspecified|BaseIndex }
-fbstp, 0xdf/6, CpuFP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
+fstp, 0xdb/7, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
+fistp, 0xdf/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fistp, 0xdf/7, FP, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|NoRex64, { Qword|Unspecified|BaseIndex }
+fistpll, 0xdf/7, FP, Modrm|NoSuf|ATTSyntax, { Unspecified|BaseIndex }
+fstpt, 0xdb/7, FP, Modrm|NoSuf, { Unspecified|BaseIndex }
+fbstp, 0xdf/6, FP, Modrm|NoSuf, { Tbyte|Unspecified|BaseIndex }
// exchange %st<n> with %st0
-fxch, 0xd9c8, CpuFP, NoSuf, { FloatReg }
+fxch, 0xd9c8, FP, NoSuf, { FloatReg }
// alias for fxch %st(1)
-fxch, 0xd9c9, CpuFP, NoSuf, {}
+fxch, 0xd9c9, FP, NoSuf, {}
// comparison (without pop)
-fcom, 0xd8d0, CpuFP, NoSuf, { FloatReg }
+fcom, 0xd8d0, FP, NoSuf, { FloatReg }
// alias for fcom %st(1)
-fcom, 0xd8d1, CpuFP, NoSuf, {}
-fcom, 0xd8/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fcom, 0xd8d0, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
-ficom, 0xde/2, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fcom, 0xd8d1, FP, NoSuf, {}
+fcom, 0xd8/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fcom, 0xd8d0, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+ficom, 0xde/2, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
// comparison (with pop)
-fcomp, 0xd8d8, CpuFP, NoSuf, { FloatReg }
+fcomp, 0xd8d8, FP, NoSuf, { FloatReg }
// alias for fcomp %st(1)
-fcomp, 0xd8d9, CpuFP, NoSuf, {}
-fcomp, 0xd8/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fcomp, 0xd8d8, CpuFP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
-ficomp, 0xde/3, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fcompp, 0xded9, CpuFP, NoSuf, {}
+fcomp, 0xd8d9, FP, NoSuf, {}
+fcomp, 0xd8/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fcomp, 0xd8d8, FP, IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|Ugh, { FloatReg }
+ficomp, 0xde/3, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fcompp, 0xded9, FP, NoSuf, {}
// unordered comparison (with pop)
-fucom, 0xdde0, Cpu387, NoSuf, { FloatReg }
+fucom, 0xdde0, 387, NoSuf, { FloatReg }
// alias for fucom %st(1)
-fucom, 0xdde1, Cpu387, NoSuf, {}
-fucomp, 0xdde8, Cpu387, NoSuf, { FloatReg }
+fucom, 0xdde1, 387, NoSuf, {}
+fucomp, 0xdde8, 387, NoSuf, { FloatReg }
// alias for fucomp %st(1)
-fucomp, 0xdde9, Cpu387, NoSuf, {}
-fucompp, 0xdae9, Cpu387, NoSuf, {}
+fucomp, 0xdde9, 387, NoSuf, {}
+fucompp, 0xdae9, 387, NoSuf, {}
-ftst, 0xd9e4, CpuFP, NoSuf, {}
-fxam, 0xd9e5, CpuFP, NoSuf, {}
+ftst, 0xd9e4, FP, NoSuf, {}
+fxam, 0xd9e5, FP, NoSuf, {}
// load constants into %st0
-fld1, 0xd9e8, CpuFP, NoSuf, {}
-fldl2t, 0xd9e9, CpuFP, NoSuf, {}
-fldl2e, 0xd9ea, CpuFP, NoSuf, {}
-fldpi, 0xd9eb, CpuFP, NoSuf, {}
-fldlg2, 0xd9ec, CpuFP, NoSuf, {}
-fldln2, 0xd9ed, CpuFP, NoSuf, {}
-fldz, 0xd9ee, CpuFP, NoSuf, {}
+fld1, 0xd9e8, FP, NoSuf, {}
+fldl2t, 0xd9e9, FP, NoSuf, {}
+fldl2e, 0xd9ea, FP, NoSuf, {}
+fldpi, 0xd9eb, FP, NoSuf, {}
+fldlg2, 0xd9ec, FP, NoSuf, {}
+fldln2, 0xd9ed, FP, NoSuf, {}
+fldz, 0xd9ee, FP, NoSuf, {}
// Arithmetic.
// add
-fadd, 0xd8c0, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fadd, 0xd8c0, FP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fadd %st(i), %st
-fadd, 0xd8c0, CpuFP, NoSuf, { FloatReg }
+fadd, 0xd8c0, FP, NoSuf, { FloatReg }
// alias for faddp
-fadd, 0xdec1, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fadd, 0xd8/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fiadd, 0xde/0, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fadd, 0xdec1, FP, NoSuf|Ugh|ATTMnemonic, {}
+fadd, 0xd8/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fiadd, 0xde/0, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-faddp, 0xdec0, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg }
-faddp, 0xdec0, CpuFP, NoSuf, { FloatReg }
+faddp, 0xdec0, FP, D|NoSuf|Ugh, { FloatAcc, FloatReg }
+faddp, 0xdec0, FP, NoSuf, { FloatReg }
// alias for faddp %st, %st(1)
-faddp, 0xdec1, CpuFP, NoSuf, {}
+faddp, 0xdec1, FP, NoSuf, {}
// subtract
-fsub, 0xd8e0, CpuFP, NoSuf, { FloatReg }
-fsub, 0xd8e0, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fsub, 0xd8e0, FP, NoSuf, { FloatReg }
+fsub, 0xd8e0, FP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fsubp
-fsub, 0xdee1, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fsub, 0xdee9, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fsub, 0xd8/4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fisub, 0xde/4, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-
-fsubp, 0xdee0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fsubp, 0xdee0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fsubp, 0xdee1, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
-fsubp, 0xdee8, CpuFP, NoSuf, { FloatAcc, FloatReg }
-fsubp, 0xdee8, CpuFP, NoSuf, { FloatReg }
-fsubp, 0xdee9, CpuFP, NoSuf, {}
+fsub, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
+fsub, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic, {}
+fsub, 0xd8/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fisub, 0xde/4, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+
+fsubp, 0xdee0, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fsubp, 0xdee0, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fsubp, 0xdee1, FP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fsubp, 0xdee8, FP, NoSuf, { FloatAcc, FloatReg }
+fsubp, 0xdee8, FP, NoSuf, { FloatReg }
+fsubp, 0xdee9, FP, NoSuf, {}
// subtract reverse
-fsubr, 0xd8e8, CpuFP, NoSuf, { FloatReg }
-fsubr, 0xd8e8, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fsubr, 0xd8e8, FP, NoSuf, { FloatReg }
+fsubr, 0xd8e8, FP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fsubrp
-fsubr, 0xdee9, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fsubr, 0xdee1, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fsubr, 0xd8/5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fisubr, 0xde/5, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-
-fsubrp, 0xdee8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fsubrp, 0xdee8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fsubrp, 0xdee9, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
-fsubrp, 0xdee0, CpuFP, NoSuf, { FloatAcc, FloatReg }
-fsubrp, 0xdee0, CpuFP, NoSuf, { FloatReg }
-fsubrp, 0xdee1, CpuFP, NoSuf, {}
+fsubr, 0xdee9, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
+fsubr, 0xdee1, FP, NoSuf|Ugh|ATTMnemonic, {}
+fsubr, 0xd8/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fisubr, 0xde/5, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+
+fsubrp, 0xdee8, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fsubrp, 0xdee8, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fsubrp, 0xdee9, FP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fsubrp, 0xdee0, FP, NoSuf, { FloatAcc, FloatReg }
+fsubrp, 0xdee0, FP, NoSuf, { FloatReg }
+fsubrp, 0xdee1, FP, NoSuf, {}
// multiply
-fmul, 0xd8c8, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
-fmul, 0xd8c8, CpuFP, NoSuf, { FloatReg }
+fmul, 0xd8c8, FP, D|NoSuf, { FloatReg, FloatAcc }
+fmul, 0xd8c8, FP, NoSuf, { FloatReg }
// alias for fmulp
-fmul, 0xdec9, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fmul, 0xd8/1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fimul, 0xde/1, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+fmul, 0xdec9, FP, NoSuf|Ugh|ATTMnemonic, {}
+fmul, 0xd8/1, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fimul, 0xde/1, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-fmulp, 0xdec8, CpuFP, D|NoSuf|Ugh, { FloatAcc, FloatReg }
-fmulp, 0xdec8, CpuFP, NoSuf, { FloatReg }
+fmulp, 0xdec8, FP, D|NoSuf|Ugh, { FloatAcc, FloatReg }
+fmulp, 0xdec8, FP, NoSuf, { FloatReg }
// alias for fmulp %st, %st(1)
-fmulp, 0xdec9, CpuFP, NoSuf, {}
+fmulp, 0xdec9, FP, NoSuf, {}
// divide
-fdiv, 0xd8f0, CpuFP, NoSuf, { FloatReg }
-fdiv, 0xd8f0, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fdiv, 0xd8f0, FP, NoSuf, { FloatReg }
+fdiv, 0xd8f0, FP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fdivp
-fdiv, 0xdef1, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fdiv, 0xdef9, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fdiv, 0xd8/6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fidiv, 0xde/6, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-
-fdivp, 0xdef0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fdivp, 0xdef0, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fdivp, 0xdef1, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
-fdivp, 0xdef8, CpuFP, NoSuf, { FloatAcc, FloatReg }
-fdivp, 0xdef8, CpuFP, NoSuf, { FloatReg }
-fdivp, 0xdef9, CpuFP, NoSuf, {}
+fdiv, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
+fdiv, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic, {}
+fdiv, 0xd8/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fidiv, 0xde/6, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+
+fdivp, 0xdef0, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fdivp, 0xdef0, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fdivp, 0xdef1, FP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fdivp, 0xdef8, FP, NoSuf, { FloatAcc, FloatReg }
+fdivp, 0xdef8, FP, NoSuf, { FloatReg }
+fdivp, 0xdef9, FP, NoSuf, {}
// divide reverse
-fdivr, 0xd8f8, CpuFP, NoSuf, { FloatReg }
-fdivr, 0xd8f8, CpuFP, D|NoSuf, { FloatReg, FloatAcc }
+fdivr, 0xd8f8, FP, NoSuf, { FloatReg }
+fdivr, 0xd8f8, FP, D|NoSuf, { FloatReg, FloatAcc }
// alias for fdivrp
-fdivr, 0xdef9, CpuFP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
-fdivr, 0xdef1, CpuFP, NoSuf|Ugh|ATTMnemonic, {}
-fdivr, 0xd8/7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
-fidivr, 0xde/7, CpuFP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
-
-fdivrp, 0xdef8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
-fdivrp, 0xdef8, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
-fdivrp, 0xdef9, CpuFP, NoSuf|ATTMnemonic|ATTSyntax, {}
-fdivrp, 0xdef0, CpuFP, NoSuf, { FloatAcc, FloatReg }
-fdivrp, 0xdef0, CpuFP, NoSuf, { FloatReg }
-fdivrp, 0xdef1, CpuFP, NoSuf, {}
-
-f2xm1, 0xd9f0, CpuFP, NoSuf, {}
-fyl2x, 0xd9f1, CpuFP, NoSuf, {}
-fptan, 0xd9f2, CpuFP, NoSuf, {}
-fpatan, 0xd9f3, CpuFP, NoSuf, {}
-fxtract, 0xd9f4, CpuFP, NoSuf, {}
-fprem1, 0xd9f5, Cpu387, NoSuf, {}
-fdecstp, 0xd9f6, CpuFP, NoSuf, {}
-fincstp, 0xd9f7, CpuFP, NoSuf, {}
-fprem, 0xd9f8, CpuFP, NoSuf, {}
-fyl2xp1, 0xd9f9, CpuFP, NoSuf, {}
-fsqrt, 0xd9fa, CpuFP, NoSuf, {}
-fsincos, 0xd9fb, Cpu387, NoSuf, {}
-frndint, 0xd9fc, CpuFP, NoSuf, {}
-fscale, 0xd9fd, CpuFP, NoSuf, {}
-fsin, 0xd9fe, Cpu387, NoSuf, {}
-fcos, 0xd9ff, Cpu387, NoSuf, {}
-fchs, 0xd9e0, CpuFP, NoSuf, {}
-fabs, 0xd9e1, CpuFP, NoSuf, {}
+fdivr, 0xdef9, FP, NoSuf|Ugh|ATTMnemonic|ATTSyntax, {}
+fdivr, 0xdef1, FP, NoSuf|Ugh|ATTMnemonic, {}
+fdivr, 0xd8/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Dword|Qword|Unspecified|BaseIndex }
+fidivr, 0xde/7, FP, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf, { Word|Dword|Unspecified|BaseIndex }
+
+fdivrp, 0xdef8, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
+fdivrp, 0xdef8, FP, NoSuf|ATTMnemonic|ATTSyntax, { FloatReg }
+fdivrp, 0xdef9, FP, NoSuf|ATTMnemonic|ATTSyntax, {}
+fdivrp, 0xdef0, FP, NoSuf, { FloatAcc, FloatReg }
+fdivrp, 0xdef0, FP, NoSuf, { FloatReg }
+fdivrp, 0xdef1, FP, NoSuf, {}
+
+f2xm1, 0xd9f0, FP, NoSuf, {}
+fyl2x, 0xd9f1, FP, NoSuf, {}
+fptan, 0xd9f2, FP, NoSuf, {}
+fpatan, 0xd9f3, FP, NoSuf, {}
+fxtract, 0xd9f4, FP, NoSuf, {}
+fprem1, 0xd9f5, 387, NoSuf, {}
+fdecstp, 0xd9f6, FP, NoSuf, {}
+fincstp, 0xd9f7, FP, NoSuf, {}
+fprem, 0xd9f8, FP, NoSuf, {}
+fyl2xp1, 0xd9f9, FP, NoSuf, {}
+fsqrt, 0xd9fa, FP, NoSuf, {}
+fsincos, 0xd9fb, 387, NoSuf, {}
+frndint, 0xd9fc, FP, NoSuf, {}
+fscale, 0xd9fd, FP, NoSuf, {}
+fsin, 0xd9fe, 387, NoSuf, {}
+fcos, 0xd9ff, 387, NoSuf, {}
+fchs, 0xd9e0, FP, NoSuf, {}
+fabs, 0xd9e1, FP, NoSuf, {}
// processor control
-fninit, 0xdbe3, CpuFP, NoSuf, {}
-finit, 0xdbe3, CpuFP, NoSuf|FWait, {}
-fldcw, 0xd9/5, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-fnstcw, 0xd9/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-fstcw, 0xd9/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex }
-fnstsw, 0xdfe0, Cpu287|Cpu387, IgnoreSize|NoSuf, { Acc|Word }
-fnstsw, 0xdd/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
-fnstsw, 0xdfe0, Cpu287|Cpu387, NoSuf, {}
-fstsw, 0xdfe0, Cpu287|Cpu387, IgnoreSize|NoSuf|FWait, { Acc|Word }
-fstsw, 0xdd/7, CpuFP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex }
-fstsw, 0xdfe0, Cpu287|Cpu387, NoSuf|FWait, {}
-fnclex, 0xdbe2, CpuFP, NoSuf, {}
-fclex, 0xdbe2, CpuFP, NoSuf|FWait, {}
+fninit, 0xdbe3, FP, NoSuf, {}
+finit, 0xdbe3, FP, NoSuf|FWait, {}
+fldcw, 0xd9/5, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+fnstcw, 0xd9/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+fstcw, 0xd9/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex }
+fnstsw, 0xdfe0, 287|387, IgnoreSize|NoSuf, { Acc|Word }
+fnstsw, 0xdd/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+fnstsw, 0xdfe0, 287|387, NoSuf, {}
+fstsw, 0xdfe0, 287|387, IgnoreSize|NoSuf|FWait, { Acc|Word }
+fstsw, 0xdd/7, FP, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|FWait, { Word|Unspecified|BaseIndex }
+fstsw, 0xdfe0, 287|387, NoSuf|FWait, {}
+fnclex, 0xdbe2, FP, NoSuf, {}
+fclex, 0xdbe2, FP, NoSuf|FWait, {}
// Short forms of fldenv, fstenv, fsave, and frstor use data size prefix.
-fnstenv, 0xd9/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fstenv, 0xd9/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
-fldenv, 0xd9/4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fnsave, 0xdd/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
-fsave, 0xdd/6, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
-frstor, 0xdd/4, CpuFP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fnstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fstenv, 0xd9/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
+fldenv, 0xd9/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fnsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
+fsave, 0xdd/6, FP, Modrm|No_bSuf|No_wSuf|No_qSuf|FWait, { Unspecified|BaseIndex }
+frstor, 0xdd/4, FP, Modrm|No_bSuf|No_wSuf|No_qSuf, { Unspecified|BaseIndex }
// 8087 only
-fneni, 0xdbe0, Cpu8087, NoSuf, {}
-feni, 0xdbe0, Cpu8087, NoSuf|FWait, {}
-fndisi, 0xdbe1, Cpu8087, NoSuf, {}
-fdisi, 0xdbe1, Cpu8087, NoSuf|FWait, {}
+fneni, 0xdbe0, 8087, NoSuf, {}
+feni, 0xdbe0, 8087, NoSuf|FWait, {}
+fndisi, 0xdbe1, 8087, NoSuf, {}
+fdisi, 0xdbe1, 8087, NoSuf|FWait, {}
// 287 only
-fnsetpm, 0xdbe4, Cpu287, NoSuf, {}
-fsetpm, 0xdbe4, Cpu287, NoSuf|FWait, {}
-frstpm, 0xdbe5, Cpu287, NoSuf, {}
+fnsetpm, 0xdbe4, 287, NoSuf, {}
+fsetpm, 0xdbe4, 287, NoSuf|FWait, {}
+frstpm, 0xdbe5, 287, NoSuf, {}
-ffree, 0xddc0, CpuFP, NoSuf, { FloatReg }
+ffree, 0xddc0, FP, NoSuf, { FloatReg }
// P6:free st(i), pop st
-ffreep, 0xdfc0, Cpu687, NoSuf, { FloatReg }
-fnop, 0xd9d0, CpuFP, NoSuf, {}
-fwait, 0x9b, CpuFP, NoSuf, {}
+ffreep, 0xdfc0, 687, NoSuf, { FloatReg }
+fnop, 0xd9d0, FP, NoSuf, {}
+fwait, 0x9b, FP, NoSuf, {}
// Opcode prefixes; we allow them as separate insns too.
-addr16, 0x67, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {}
-addr32, 0x67, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {}
-aword, 0x67, Cpu386|CpuNo64, Size16|IgnoreSize|NoSuf|IsPrefix, {}
-adword, 0x67, Cpu386, Size32|IgnoreSize|NoSuf|IsPrefix, {}
-data16, 0x66, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {}
-data32, 0x66, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {}
-word, 0x66, Cpu386, Size16|IgnoreSize|NoSuf|IsPrefix, {}
-dword, 0x66, Cpu386|CpuNo64, Size32|IgnoreSize|NoSuf|IsPrefix, {}
+addr16, 0x67, 386|No64, Size16|IgnoreSize|NoSuf|IsPrefix, {}
+addr32, 0x67, 386, Size32|IgnoreSize|NoSuf|IsPrefix, {}
+aword, 0x67, 386|No64, Size16|IgnoreSize|NoSuf|IsPrefix, {}
+adword, 0x67, 386, Size32|IgnoreSize|NoSuf|IsPrefix, {}
+data16, 0x66, 386, Size16|IgnoreSize|NoSuf|IsPrefix, {}
+data32, 0x66, 386|No64, Size32|IgnoreSize|NoSuf|IsPrefix, {}
+word, 0x66, 386, Size16|IgnoreSize|NoSuf|IsPrefix, {}
+dword, 0x66, 386|No64, Size32|IgnoreSize|NoSuf|IsPrefix, {}
lock, 0xf0, 0, NoSuf|IsPrefix, {}
wait, 0x9b, 0, NoSuf|IsPrefix, {}
cs, 0x2e, 0, NoSuf|IsPrefix, {}
ds, 0x3e, 0, NoSuf|IsPrefix, {}
-es, 0x26, CpuNo64, NoSuf|IsPrefix, {}
-fs, 0x64, Cpu386, NoSuf|IsPrefix, {}
-gs, 0x65, Cpu386, NoSuf|IsPrefix, {}
-ss, 0x36, CpuNo64, NoSuf|IsPrefix, {}
+es, 0x26, No64, NoSuf|IsPrefix, {}
+fs, 0x64, 386, NoSuf|IsPrefix, {}
+gs, 0x65, 386, NoSuf|IsPrefix, {}
+ss, 0x36, No64, NoSuf|IsPrefix, {}
rep, 0xf3, 0, NoSuf|IsPrefix, {}
repe, 0xf3, 0, NoSuf|IsPrefix, {}
repz, 0xf3, 0, NoSuf|IsPrefix, {}
@@ ...
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] x86: omit Cpu prefixes from opcode table
2022-12-12 13:14 ` [PATCH 2/2] x86: omit Cpu prefixes from opcode table Jan Beulich
@ 2022-12-13 7:29 ` Jan Beulich
0 siblings, 0 replies; 4+ messages in thread
From: Jan Beulich @ 2022-12-13 7:29 UTC (permalink / raw)
To: Binutils; +Cc: H.J. Lu
On 12.12.2022 14:14, Jan Beulich wrote:
> These enumerators can be used in only one specific field, and hence the
> Cpu prefix isn't needed ther for disambiguation / name space separation.
> ---
> RFC: I will admit that I'm not entirely happy with the result,
> specifically because of the purely numeric "identifiers" which we
> end up with now (e.g. 286 or 64). Since for things like AVX the
> change is (imo) a clear improvement, I wonder whether some hybrid
> approach might be best to take, or whether we could go with e.g.
> CpuI286 and CpuX64.
It was only early in the morning today when I realized that there's a
pretty simple way to address this: We can add
#define i386 386
etc to i386-opc.tbl (or alternatively something functionally equivalent
to i386-gen.c). Which is what I'm going to do then.
Jan
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-12-13 7:29 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-12 13:10 [PATCH 0/2] x86: further opcode table line length reduction Jan Beulich
2022-12-12 13:12 ` [PATCH 1/2] x86: change representation of extension opcode Jan Beulich
2022-12-12 13:14 ` [PATCH 2/2] x86: omit Cpu prefixes from opcode table Jan Beulich
2022-12-13 7:29 ` Jan Beulich
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